Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.

Abstract: A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.

Abstract: A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type ca

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A single-supply digital voltage level shifter has a first inverter having a first input for receiving an input signal with a first voltage swing, and a first output for outputting a first output signal. A second inverter has a second input for receiving the first output signal, and a second output for outputting a second output signal with a second voltage swing, where the second output signal is a level-shifted version of the input signal. A comparison stage includes a first comparison stage input for receiving the input signal, a second comparison stage input for receiving the second output signal, and a comparison stage output for outputting a comparison stage output control signal. A control stage is connected in a circuit branch of the first inverter and has a control stage switch that assumes a non-conducting state dependent on a logical state of the comparison stage output control signal.

Abstract: A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low.

Abstract: Level shifter and related apparatus are provided. The level shifter has first to sixth transistors, wherein drains of the first and the second transistors respectively are coupled to drains of the fifth and the sixth transistors as two output nodes of the level shifter, gates of the fifth and the sixth transistors are two input nodes of the level shifter. A source, a drain and a gate of the third transistor are respectively coupled to a gate of the first transistor, the drain of the sixth transistor and a first bias voltage, and a source, a drain and a gate of the fourth transistor are respectively coupled to a gate of the second transistor, the drain of the fifth transistor and a second bias voltage.

Abstract: Circuit blocks and respectively convert high-voltage logic signals in which two logical values are expressed by a first signal potential and a second signal potential into low-voltage logic signals in which the two logical values are expressed by a third signal potential at least as large as the first signal potential and a fourth signal potential that is the third signal potential to which a positive voltage has been added and which is no greater than the second signal potential, and outputs the converted logic signals. The transistors in the circuit block are of the form of replacing the respective transistors of the circuit block with elements of opposite polarity, so that when the third signal potential is changed and operation of one of the circuit blocks and becomes difficult, the other operates normally. Consequently, stable level conversion can be accomplished.

Abstract: An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (VIN), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N1) and a first PMOS transistor (P1) coupled in parallel between the input terminal and the second node(B). Furthermore, a second PMOS transistor (P2) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N2) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P1) is coupled to the first node (A). The gate of the second NMOS transistor (N2) and the gate of the second PMOS transistor (P2) are coupled to the supply voltage (VDDE).

Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.

Abstract: A data transfer circuit includes: plural transfer lines transferring data; plural data output units connected to end portions of the respective transfer lines, detecting and outputting data transferred through the transfer lines with drive performance in accordance with a control signal; plural data transmission units arranged in parallel, transferring data to the corresponding transfer lines in response to selection signals; a selection control unit generating selection signals and outputting the selection signals to the corresponding data transmission units; and a control unit generating the control signal for controlling drive performance of the data output units to adjust data transfer delay and outputting the control signal to the respective output units. The transfer lines are arranged in the arrangement direction of the data transmission units and connected to the corresponding data output units. The control unit generates the control signal in accordance with the length of the data transfer distance.

Abstract: A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.

Abstract: A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a level of a pumping voltage in response to the select signal and the driving control signal; a first switching unit configured to apply a program voltage to a word line when the first shifting signal is enabled to the level of the pumping voltage; and a second switching unit configured to apply a pass voltage to the word line when the second shifting signal is enabled to the level of the pumping voltage.

Abstract: A high voltage tolerant bus holder circuit and method of operating the bus holder circuit utilizes first and second control transistors connected in parallel between a control terminal of a pull-up transistor and a bus. The first control transistor is used to turn on the pull-up transistor during a pull-up mode of operation. The second control transistor is used to turn off the pull-down transistor when a voltage on the bus exceeds a threshold.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node ? into a floating state. When the node ? is in the floating state, a potential of the node ? is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.

Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.

Abstract: Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract: A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed.

Abstract: A level shifter includes first and second NMOS transistors with gates connected to inverted circuit and circuit inputs, respectively, sources connected to the ground, and drains connected to circuit and inverted circuit outputs, respectively. First and second PMOS transistors have their gates connected to the inverted circuit and circuit outputs, respectively, and sources connected to the high voltage supply. A third PMOS transistor of the multiple independent gate type has its source connected to the drain of the first PMOS transistor, drain and back-gate connected to the circuit output, and front-gate connected to the inverted circuit input. A fourth PMOS transistor of the multiple independent gate type has its source connected to the drain of the second PMOS transistor, drain and back-gate connected to the inverted circuit output, and front-gate connected to the circuit input.

Abstract: In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: A lever shifter is provided for receiving a signal in a first voltage domain and providing an output signal in a second voltage domain. The level shifter reduces propagation delay and power consumption by mitigating contention between NFETs and PFETs during signal propagation.

Abstract: A leakage current reduction circuit comprising a transmission gate, a feedback channel and a controller is placed between a first device supplied with a first voltage potential and a second device supplied with a second voltage potential. The voltage potential mismatch between the first device and the second device may cause a leakage current flowing through the input stage of the second device. By employing the low leakage power detection circuit, a logic high state generated from the first device can be converted into a logic high state having an amplitude approximately equal to the second voltage potential.

Abstract: A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages.

Abstract: An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.

Abstract: Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled to a common-mode pre-emphasis module, the center-swing signal generator to receive a low swing current mode logic (CML) signal and output a center-swing signal, and a full-swing cross-coupled inverter coupled to the center-swing signal generator, the full-swing cross-coupled inverter to receive the center-swing signal and output a full-rail single-ended swing signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.

Abstract: An output driving device prevents an inflow of external current through an output terminal even when there is no power supply. The output driving device includes an output circuit that maintains an output terminal at a low impedance state by receiving a supply of power in an output drive operation and maintains the output terminal at a high impedance state by receiving the supply of power in a non-output drive operation and a leakage prevention unit coupled to the output terminal of the output circuit, the leakage prevention unit preventing a current inflow to the output circuit through the output terminal when the supply of power is not supplied to the output circuit.

Abstract: Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.

Abstract: An integrated circuit (IC) includes an input/output (I/O) circuit supporting high-speed operation and multiple I/O logic-level swings. The I/O circuit includes a first output signal chain to generate outputs with a first logic level swing, and a second output signal chain to generate outputs with a second logic level swing. The outputs of the first output signal chain and the second output signal chain are connected to a same output pad of the IC. Transistors in the first output signal chain and the second output signal chain are fabricated using corresponding gate oxide characteristics. The second output signal chain includes protection circuitry to prevent transistors in the second output signal chain from being subjected to voltage stresses beyond a safe limit. An input circuit in the I/O circuit similarly includes multiple input signal chains to enable reception of input signals of different logic-level swings from a same input pad.

Abstract: A semiconductor structure operation method. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.

Abstract: A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.

Abstract: A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.

Abstract: An integrated circuit (IC) system includes a plurality of ICs configured in a stacked voltage domain arrangement such that a low side supply rail of at least one of ICs is common with a high side supply rail of at least another of the ICs; a reversible voltage converter coupled to power rails of each of the plurality of ICs, the reversible voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.

Abstract: A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode and activates the second input circuit in a second mode. The control circuit controls the first input circuit and the second input circuit such that the first input circuit and the second input circuit are activated during a certain time period when switching between the first mode and the second mode.

Abstract: A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

Abstract: A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

Abstract: A level shifting circuit includes a string of diodes and an active load across which the control voltage is applied. A resistor is coupled across the lowermost diode to develop a switch control voltage. At low control voltage, the diode string allows no current to be developed across the resistor. At higher control voltage, the diodes conduct and the active load takes up the difference between the control voltage and the diode string voltage. A switch responds to the resistor voltage, for switching a load On and OFF. A second active load takes up excess load supply voltage.

Abstract: A level shift circuit is disclosed. The circuit includes a series circuit of a resistor and a switching device connected between a high voltage side power supply voltage in a secondary side voltage system and a low voltage side power supply voltage in a primary side voltage system, a series circuit of a resistor and a switching device connected between the high voltage side power supply voltage in the secondary side voltage system and the low voltage side power supply voltage in the primary side voltage system, and a latch malfunction protecting circuit operated in the secondary side voltage system to have voltages at a connection point of the resistor and the switching device and at a connection point of the resistor and the switching device inputted.

Abstract: A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

Abstract: A semiconductor circuit is provided in which no error signal is generated even when the circuit is exposed to a transient voltage noise that occurs with a transition from a first state indicating a conduction of a high-potential side switching device to a second state indicating a non-conduction of the high potential side switching device, or vice versa. A high potential switching device drive circuit 1 includes short circuit devices 31 and 32 that are controlled by the second level shifted signals S6 and S7 simultaneously generated across the second load resistances 30 and 29, respectively, to thereby serving to prevent a signal from being generated at one of the output sections where the other one of the first level shifted signals S4 and S5 is to be generated, when either one of the first shifted signals S4 and S5 in level shift circuit ON and OFF sections is generated across first load resistance 28 or 27 in a level shift circuit 2.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.