Abstract: A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an evaluating cycle to form a discharging path; a precharging device which is turned on at a precharging cycle before an evaluating cycle to provide a precharging voltage; a first pair of transistors, having first terminals coupled to the precharging voltage, first gate terminals coupled to receive pair of complementary signals whose logic values decide whether the first pair of transistors are turned on or not, and second terminals; a second pair of transistors, having third terminals coupled to the second terminals of the first pair of transistors, second gate terminals coupled to receive a pair of complementary address bit signals whose logic values decide whether the second pair of transistors are turned on or not, and fourth terminals coupled to the discharging device; and a fuse device, having a fuse which is coupled to t

Abstract: Integrated circuit devices include a data buffer that is responsive to a control signal, enabled to pass data received at a data input thereof to a data output thereof when the control signal is in an active logic state and disabled to block passage of data from the data input to the data output when the control signal is in an inactive logic state. A data buffer control circuit is also provided. The data buffer control circuit latches a latency signal in response to a control clock, generates the control signal from the latched latency signal and comprises a pulse generator that drives the control signal to its inactive logic state in-sync with an edge of the latency signal. This inactive control signal can be used to disable the data buffer.

Abstract: A system and method with a self-reset circuit for synchronizing an input data path with a timing control path. The self-resetting circuit includes a normal-mode input detect circuit which detects an arrival of data from the input data path into the self-reset circuit and generates a normal-mode control signal in response thereto. The self-resetting circuit also includes a delay-mode input detect circuit for detecting the arrival of the data from the input data path and which generates a delay-mode control signal in response thereto. A toggle circuit is provided for disabling the normal-mode input detect circuit while simultaneously enabling the delay-mode input detect circuit. In response to the toggle circuit disabling the normal-mode input detect circuit, the delay-mode control signal propagates through a delay gate, such that said delay-mode control signal synchronizes said timing control path with respect to said data input path.

Abstract: Disclosed herein is a semiconductor integrated circuit comprising: a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of said second conductivity-type connected in series between the drain of said first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal, said second transistor and at least one and not all of said third transistors having a threshold voltage lower than a threshold voltage of the others of said third transistors. The circuit of the present invention including the transistors having the different threshold values can achieve the high speed operation of the circuit, the extension of the signal retention time secured by the reduction of a leakage current and the decrease of the power consumption.

Abstract: In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal.

Abstract: A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground line VSS, a low-threshold logic (combinational) circuit connected between QVCC and VSS, and a data storage (sequential) circuit, connected between VCC and VSS. The data storage circuit includes a low-threshold input section for receiving data from the logic circuit and a high-threshold latch section for latching the data received by the input section. Mode switching transistors are inserted between the low-threshold logic circuit and VSS, between low-threshold input section and VCC and between the low-threshold input section and VSS, for effecting a sleep mode of the semiconductor integrated circuit. Low power dissipation is maintained with a reduced circuit scale.

Abstract: In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor.

Abstract: A top clock stacked circuit is provided that substantially prevents charge sharing and that prevents any deleterious bipolar effect. The top clock stacked circuit comprises a primary pre-charge circuit coupled to a primary node, a first device coupled between the primary node and a first secondary node, and a second device coupled between the first secondary node and a second secondary node. A second pre-charge circuit is coupled to the first secondary node and a pre-discharge circuit is coupled to the second secondary node. In response to a first clock polarity, the primary and the second pre-charge circuits pre-charge the primary and the first secondary nodes, respectively, and the pre-discharge circuit pre-discharges the second secondary node. Thereafter, in response to a second clock polarity, the first device creates a path between the primary node and the first secondary node. Because both nodes are pre-charged to the same voltage, charge sharing is substantially prevented.

Abstract: A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.

Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

Abstract: A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one embodiment of the circuit, an evaluation transistor is positioned between a precharge transistor and a dynamic logic block. The evaluation transistor separates a precharge node from the logic block during a precharge clock phase so that the logic block is not charged. A delay coupled to the precharge transistor allows the precharge transistor to remain activated during a portion of an evaluation clock phase to overcome any effects of charge-sharing between the precharge node and the dynamic logic block. Because the evaluation transistor separates the logic block from the precharge node, the precharge node can be charged independently of the number of inputs present in the dynamic logic block.

Abstract: A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when docks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.

Abstract: A power saving clock buffer comprises a first control stage installed between a clock output and a first switch stage for controlling the state of the first switch stage. A second switch stage installed between the clock output and a second switch stage for controlling the state of the second switch stage. A clock input stage is formed by connecting an PMOS with a NMOSs, and is installed between a clock input and the first and second switch stages and is connected to the clock output through a phase inverting logic circuit. By the aforementioned circuit structure, the clock circuit will stop working as the related circuit does not work and, therefore, the power is saved and a high reliability is attained.

Abstract: A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication processes has a precharge transistor connected between a precharge volt source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value.

Abstract: A bus circuit of this invention has a bus line. A bus input circuit and a bus output circuit are connected to the bus line. The bus line is charged by a precharge circuit. The bus output circuit outputs an output signal to the bus line by discharging or not discharging potential of the bus line. The bus input circuit inputs a signal from the bus line. The bus input circuit includes a feedback circuit which inputs potential of the bus line as the signal, amplifies the signal in accordance with a change of the signal, and feeds back the amplified result to the bus line.

Abstract: A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops.

Abstract: The present invention comprises a method and apparatus for a logic circuit with constant power consumption. The logic circuit comprises a 1 of P first input signal that further comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The logic circuit additionally comprises a 1 of Q second input signal that comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. A logic tree circuit couples to the first input signal and the second input signal. The logic tree circuit generates a result for a 1 of R output signal, which couples to the logic tree circuit. The 1 of R output signal comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The power consumption of the logic circuit is independent of the value of the first signal or the second signal, which results in the logic circuit having constant power consumption.

Abstract: An embodiment of the present invention includes a switchable conductive pathway between a number of intermediate nodes in a domino stage, up to and including every intermediate node, and a voltage source. In operation, this circuit configuration prevents the problems associated with charge sharing. The voltage, at the voltage source which is coupled to the intermediate nodes, is substantially equal to the voltage at a voltage source that is coupled by way of a domino precharge circuit to the output node of the domino stage. The switchable conductive pathways are switched on at the start of the precharge phase, and switched off at the beginning of the evaluation phase. In this way, intermediate node voltages in a domino stage are actively maintained, even after the main precharge control signal has been deasserted. Active maintenance of the intermediate nodes is suspended during the evaluation phase.

Abstract: A domino CMOS circuit has a number of domino gates, a common virtual ground node and a common evaluation NFET device. Each domino gate provides a PFET precharge device, an NFET device tree, an output inverter stage, a dynamic node, a plurality of input nodes, a clock input node and an output node. The PFET precharge device is coupled to a high voltage supply rail, the clock input node and the dynamic node and an NFET device tree is coupled to the common virtual ground node, to the plurality of inputs and to the dynamic node. An output inverter stage is coupled to the high voltage supply rail, to said dynamic node, to a low voltage supply rail and to said output node. And for improving performance, a common evaluation NFET device is coupled to said clock inputnode, to the to said low voltage supply rail and to the common virtual ground node. The virtual ground node is coupled to the low voltage supply rail when a high voltage is applied to clock input node.

Abstract: A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit blocks out one or more of the clock cycles of the external clock signal to generate the internal clock signal. The clock control circuit can be used in any semiconductor device, and especially in synchronous flash memory devices with a burst operation. In the synchronous flash memory devices, one or more of the internal clock cycles are blocked out to account for increased delays during certain data sensing operations such as word line switching during data reading. In the synchronous flash memory devices, the sensed data is stored in input/output buffers and transferred out synchronously to the external clock signal.

Abstract: A domino circuit design for handling high stress conditions. The domino logic circuit includes a programmable mechanism for choosing whether the circuit is operating during normal operations or during a stress test, such as a burn-in procedure. In particular, the circuit includes a dual purpose transistor that is controllable by either a precharge signal or an output signal, and includes a mechanism for selecting whether the precharge signal or the output signal is to control the gate input of the dual purpose transistor. Accordingly, the dual purpose transistor will either act in parallel with the precharge device, or a keeper device depending on the mode of operation chosen.

Abstract: An exclusive OR circuit (10) includes an input stage (11) and a control arrangement (12,13) for controlling an exclusive OR logical evaluation. The control arrangement includes a pre-charge stage (12) which responds to a first level clock signal to enable the desired exclusive OR logical evaluation. The input stage (11) is connected to receive a first input signal and a second input signal and is also connected to an evaluation node (23). When the logic state of one input signal is unequal to the logic state of the other input signal, the input stage (11) couples the evaluation node (23) to ground. An output stage (13) of the control arrangement inverts the signal at an internal node (24) to produce the output from the exclusive OR circuit. A pre-charge stage (12) couples the internal node (24) to the evaluation node (23) only in response to a "high" clock signal.

Abstract: A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.

Abstract: According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Abstract: A method and apparatus for precharging a dynamic bus on either phase of a clock signal is presented. An intelligent precharger in accordance with the invention monitors a dynamic bus and detects and signals a discharge event on the bus during a current phase of a clock signal. The current phase of the clock signal can be either one of a first phase or second phase of the clock signal. On the subsequent phase of the clock signal, which is the other of the first phase or second phase of the clock signal, the bus is then precharged.

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Abstract: A bi-phase, single-wire dynamic bus for allowing communication during either of a first phase or a second phase of a clock signal is presented. A data signal that is to be written onto a single bus wire is written onto the bus, via a write enable circuit, during one of the first or second clock phase. A precharger circuit precharges the bus on the subsequent clock phase, which is the other of the first or second clock phase.

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Abstract: An impedance control circuit is provided which controls the output impedance of drivers which are coupled to the impedance control circuit. Accordingly, a desired driver output impedance can advantageously be established and maintained over a wide range of variations in operating conditions and manufacturing processes. Thereby shortening the signal settling time and increasing the attainable signaling frequency.

Abstract: A circuit arrangement, system, and method provide asynchronous control of a state logic circuit to facilitate testing of the state logic circuit. The state logic circuit includes stages selectively enabled by a clock signal that generate an output signal as a function of a history of a data signal. Upon application of a control signal, the alternate enabling circuit enables at least one of the stages regardless of the state of the clock signal, such that the output signal does not depend on the history of the data signal.

Abstract: A dynamic multiplexer circuit (20) comprising an integer number N of data providing circuits (26, 28, 30), wherein the integer number N is greater than one. Each of the plurality of data providing circuits comprises a precharge node (26.sub.PN, 28.sub.PN, 30.sub.PN) to be precharged to a precharge voltage during a precharge phase, and a conditional series discharge path (26.sub.L and 26.sub.DT, 28.sub.L and 28.sub.DT, 30.sub.L and 30.sub.DT) conrected to the precharge node Each discharge path is operable in response to at least one enabling input signal (INPUTS.sub.26, INPUTS.sub.28, INPUTS.sub.30) to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node. Each of the plurality of data providing circuits further comprises an inverter (26.sub.INV, 28.sub.INV, 30.sub.INV) coupled to the precharge node and having an output for providing a second monotonic transitioning data signal.

Abstract: A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit.

Abstract: A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage.

Abstract: A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.

Abstract: A dynamic current mode circuit for low-voltage and high performance VLSI applications, comprising a MOS current mode logic block and dynamic circuitry for precharging the outputs of the MOS current mode logic block, cross-coupled latches for enhancing performance of the MOS current mode logic block during an evaluation phase thereof, and a dynamic current source for enhanced speed and low power consumption.

Abstract: A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which includes additional weighted static gain chains connected within the buffer circuit. The buffer circuit retains the benefits of the split-drive, dual output transistor configuration, and also substantially improves circuit gain per delay gate by connecting the weighted static gain chains between pulse generators and output transistors of the buffer circuit. The gain chains are designed to rapidly propagate the edge that fires their respective output transistors but slowly propagate the edge that turns the output transistor off, by reducing the devices that propagate the shut-off transition. N-type and p-type devices within the buffer circuit are arranged and sized to promote the gain characteristic of the split drive buffer circuit.

Abstract: A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.

Abstract: Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor logic circuit. In the logic circuit, the inverter having a clock input is provided on the output of a pass-transistor logic circuit. The inverter having a clock input includes the inverter circuit and write control means. A data holding circuit is connected to the output of the write control means. In the logic circuit, a clock is input to the inverter having a clock input after the output of the pass-transistor logic circuit is stabilized. Thus, the short circuit current which flows in the inverter circuit is restrained. In addition to the logic circuit, a positive feedback circuit for supplying an inverted signal from the inverter circuit to the output of the inverter having a clock input can be provided.

Abstract: A CMOS Critical Voltage Transition Logic device which reduces propagation delays in a circuit by preconditioning the voltage outputs of each stage of the circuit to a critical voltage value which is between the logic high and logic low values for the circuit. The transition time to achieve either the high or low logic output states which is responsive to the input signal from the previous stage is reduced due to the preconditioning. Each stage is synchronously clocked in order to achieve the preconditioned state in each stage before processing the input signal for the previous stage. This unique switching characteristic greatly reduces the propagation delay in the circuit.

Abstract: An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node.

Abstract: A dynamic circuit that prevents a malfunction, even when the operating temperature is high, including a pre-charging circuit connected between a power source node and a signal wiring, a plurality of discharging circuits being connected between a power source node and a signal wiring, a plurality f discharging circuit connected between the signal wiring and a ground potential respectively and for being selectively turn-ON/OFF controlled, a leakage current detecting circuit for detecting a current corresponding to a leakage current generated between the signal wiring and the ground potential in the turn-OFF state of each discharging circuit, and a leakage current correcting circuit connected between the power source node and the signal wiring and for continuously supplying to the signal wiring a leakage correction current equivalent to a leakage current of the signal wiring corresponding to a detected current of the leakage current detecting circuit during a leakage current correction period.

Abstract: A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an array of memory cells (12) aligned in an array. The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1-8), each having a plurality of wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub. 0, TA6.sub. 0, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31).

Abstract: In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting, thereby increasing the operation speed of the input circuit. The address buffer includes a differential amplifier Ai which receives an input signal Ai and outputs a pair of differential signals A-come-first-served latch circuit detects, latches and outputs one of the paired differential signals that has changed first. Activation/inactivation of the differential amplifier is done by turning on and off an N-channel MOS transistor through a Set signal. When activated, the differential amplifier generates a potential difference between the paired differential signals and, when inactivated, has its paired differential signals go low.

Abstract: A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers.

Abstract: A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication rocesses has a precharge transistor connected between a precharge voltage source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value.

Abstract: A dynamic logic circuit operates in a normal mode, and in a safe mode for which the circuit is less susceptible to noise than with the normal mode. The dynamic logic circuit includes a logic network having at least one input, a precharge device having a storage node connected to the logic network, and a device for varying a capacitance of the storage node to provide the normal and safe modes of operation. In one embodiment, the capacitance at the storage node is varied by selectively connecting the storage node to a capacitor, particularly to a DRAM cell capacitor. The DRAM cell is advantageously fabricated on a chip in close proximity to the storage node. A logic process using a plurality of such dynamic logic circuits can have means for independently operating each of the circuits in the safe mode, and the circuits can be monitored during the normal and safe operation modes to determine whether any are failing during the normal operation mode, e.g., due to excess noise.

Abstract: A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.

Abstract: A digital logic gate circuit including a logic block, clock transistor, bias transistor and a negative differential resistance (NDR) diode which acts as an active load for the circuit. The logic block, comprising a plurality of field effect transistors whose control terminals receive the set of input signals to the logic gate, determines the gate function such as inversion, NAND, NOR, MAJORITY, etc. The clock transistor is connected in series with the logic block and the bias transistor is connected in parallel across this series combination. The terminal of the NDR diode affixed to the common terminal of the bias transistor and the logic block forms the output for the logic circuit. NDR diodes include but are not limited to devices such as tunnel diodes and resonant tunneling diodes (RTDs). The folded I-V characteristic of an NDR diode allows the circuits to operate in a bistable clocked mode, where the circuit output latches its state and changes only when the clock signal is active.