Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: In one embodiment, a circuit is provided that includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body. The precharge device is connected to a precharge node for charging it during a precharge state. The DNG FET transistor is connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state. In addition, the DNG transistor has an associated precharge leakage current. The at least one pull-down FET transistor has an input threshold voltage whose value is inversely affected by its floating body voltage. The at least one pull-down transistor is connected between the precharge node and the DNG node for discharging the precharge node during the evaluate state if so dictated by logical function input values applied to the pull-down transistors during the evaluate state.

Abstract: A new family of pseudo-NMOS static logic gates is provided that use feedback from a shared output node to enhance the response of and applicability of such static logic gates. In architecture, the feedback-induced pseudo-NMOS static (FIPNS) logic gate comprises (a) a pulldown network having one or more pulldown NMOS transistors for receiving one or more inputs, (b) a primary pullup network having one or more primary pullup PMOS transistors connected to the NMOS transistor network at a shared output node, which produces a gate output, and (c) a secondary pullup network having one or more secondary pullup PMOS transistors connected to the NMOS transistor network by way of an actuation mechanism, which causes actuation of the secondary pullup PMOS transistor(s) based upon feedback from the shared output node to thereby increase pullup drive strength relative to pulldown drive strength.

Abstract: A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.

Abstract: A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.

Abstract: A non-overlapping clock generator that has its dead time adjustable without a complete re-design and re-fabrication. Certain terminals of certain devices of the non-overlapping clock generator are connected only by metal layers. This allows the circuit of the non-overlapping clock generator to be changed, adjusting the dead time, by changing only the masks used to fabricate the metal layers. This allows non-overlapping clock generators on wafers that have been partially fabricated to have their dead times altered from the original design.

Abstract: A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

Abstract: A circuit having a data input pin for receiving a data signal, a clock input pin for receiving a clock signal and having a low setup time and a zero hold time is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal.

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to coupl

Abstract: A semiconductor integrated circuit device includes a control circuit for coping with time differences in signals propagating along by differences in routes of the circuit device. In a definite data interval when changes of all signals have been completed, the control circuit outputs a received signal. In an indefinite data interval when changes of all signals have not been completed, the control circuit outputs a fixed signal irrespective of signal level of a received signal. The control circuit thus prevents irregular signal changes caused by the time differences before definition of data to subsequent circuits.

Abstract: In one embodiment, the present invention provides a multi-bit dynamic comparator for comparing first and second words having a plurality of comparative bit pairs with each pair having comparative first and second word bits. The multi-bit comparator includes a multiple number of precharge sub-stage comparators operably connected to a precharge NOR circuit. The multiple number of precharge sub-stage comparators each have inputs for receiving one or more separate comparative bit pairs. They each also have an output for providing a sub-stage output value that is inactive during a precharge state, active during an evaluate state if any of its received one or more comparative bit pairs has unequal bits, and inactive during the evaluate state if all of its received comparative bit pairs have equivalent bits. The multiple number of received separate one or more bit pairs constitutes the plurality of comparative bit pairs.

Abstract: A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.

Abstract: A noise suppression circuit is presented which improves signal quality on signal control lines of dynamic logic circuits. The noise suppression circuit provides dynamic line termination and immunity to cross-coupling of signals from other control lines. The line termination portion of the circuit suppresses high-transitioning pulses on low-drive control lines by referencing the low control line level to the local ground and low-transitioning pulses on high-drive control lines by referencing the control line level to a local power supply to immunize pass-gate logic. The input of a CMOS inverter is coupled to the control line. The drain of a FET is coupled to the output control line, and its gate is coupled to the output of the CMOS inverter. Suppression of high-transitioning and low-transitioning pulses is achieved by coupling the source of the FET to the local ground or local power supply respectively.

Abstract: A method and apparatus for operating logic circuitry with recycled energy. An energy storage device such as an inductor collects energy that used to operate logic circuitry during a first phase of a clock cycle and returns the collected energy back to the circuit during a second phase of the clock cycle. An adaptive circuit senses the collected energy that is returned to the logic circuit during the second phase of the clock cycle to determine whether the energy has fallen below a predetermined limit. If so, the adaptive circuit supplies any needed energy during the second phase of the clock cycle. The inductor that collects energy used to operate the logic circuitry and the inherent capacitance of the logic circuitry form a resonant circuit that operates in synchronism with the clock cycle, the inductor storing energy during the first phase and returning the energy to the inherent capacitance of the logic circuitry during the second phase.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Abstract: A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.

Abstract: The present invention relates to a circuit that prevents or reduces power consumption in a dynamic logic circuit. The circuit according to the present invention that inhibits power consumption effectively reduces subthreshold leakage current particularly when generated in a standby state of the dynamic logic. The present invention can include a dynamic logic provided with first and second MOS transistors of a conductive type different from each other and a power selection unit. The power selection unit outputs first and second voltages different from each other according to an output level of the dynamic logic. The power selection unit outputs a power voltage and a substrate voltage as first and second voltages when the output of the dynamic logic is at a high level, or outputs a boosting voltage and a ground voltage as the first and second voltages when the output of the dynamic logic is at a high level.

Abstract: The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Abstract: A fully dynamic logic network and method of operation thereof. The dynamic logic network includes a number of dynamic switching circuits, where each of dynamic switching circuits generates an output signal. In an advantageous embodiment, each of the dynamic switching circuits is a dynamic domino gate. The dynamic logic network also includes a dynamic logic circuit that is coupled to the dynamic switching circuits. The dynamic logic circuit, in turn, includes a clock generation circuit and a logic switching circuit that in a preferred embodiment is a dynamic NOR, or alternatively, NAND gate. The clock generation circuit receives the output signals from the dynamic switching circuits and generates, in response thereto, a control signal. The logic switching circuit also receives the output signals from the dynamic switching circuits and generates a logic output signal in response to a state of the control signal generated by the clock generation circuit.

Abstract: A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes first and second complementary control logic circuits (e.g., pass transistor circuits), first and second capacitors each having one plate connected to a first potential and another plate connected to a respective one of first and second complementary outputs of said logic circuit, a differential cascode voltage switch circuit, comprising at least first and second transistors each having gates cross-coupled to said first and second complementary outputs, and precharge circuitry configured to precharge said first and second complementary outputs to a desired (e.g., high) state.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit capable of stable operating at high speed. A semiconductor integrated circuit according to the present invention includes three pieces of first logic operation circuits 1a, 1b and 1c, keeper circuits 2a, 2b and 2c each of which holds output logics of the first logic operation circuits 1a, 1b and 1c, and three inverters IVa, IVb and IVc connected to output terminals of the first logic operation circuits 1a, 1b and 1c, respectively. When an output of any one first logic operation circuit turns to a low level, outputs of the other first logic operation circuits are forcibly set to a high level, and any one output terminal can be hence solely set on the high level.

Abstract: An improved sense amplifier ad method for sensing signals in a silicon-on-insulator (SOI) integrated circuit improve the performance of semiconductor memories and other circuits implemented in SOI technology. The bodies of amplifier transistors within the sense amplifier and bodies of input transistors to the sense amplifier are coupled to corresponding input signals, eliminating the history dependance that would result from unconnected bodies, while achieving faster switching times due to a dynamically produced difference in threshold voltage of the input transistors and amplifier transistors. The switching time is improved over circuits using input transistors and amplifier transistors having statically biased bodies.

Abstract: A configurable dynamic PLA in accordance with the present invention provides for multiple programs onto one dynamic PLA and allows one of the multiple programs to be selected at any given time, making the array “configurable” after the array is built. In addition, if the evaluate modules are made reprogrammable, the PLA is both configurable and reprogrammable. The capability to reprogram the array allows new functions to be realized after the array is built. The capability to configure the array allows any one of the preprogrammed functions—be it hardwired or reprogrammed—to be selected for each evaluation cycle. This is especially useful since reprogramming the array may take multiple cycles.

Abstract: A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.

Abstract: The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches which supply power to the logic circuit block, and a switch control circuit which controls the power supply switches. The switch control circuit switch-controls the power supply switches so as to bring a period shorter than the cycle of the clock signal to an on operation period in synchronism with a clock signal. When the logic circuit block is supposed to be activated in synchronism with a clock signal having a frequency lower than a clock signal frequency for defining the maximum operation speed of the logic circuit block, the logic circuit block does not develop a malfunction theoretically if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed.

Abstract: A coincidence determining circuit determines whether first and second digital data each consisting of a plurality of bits coincide with one another. The coincidence determining circuit includes a wiring and a plurality of bit comparison circuits corresponding in number to the bits. Each bit comparison circuit includes first and second transistors connected in series between the wiring and a power supply line and third and fourth transistors connected in series between the wiring and the power supply line. The first and second transistors receive a first logical signal of an associated bit of the first digital data and an inverted signal of a second logical signal of an associated bit of the second digital data. The third and fourth transistors receive an inverted signal of the first logical signal and the second logical signal. The four transistors of each bit comparison circuit suppress an increase in circuit area.

Abstract: A semiconductor integrated circuit includes a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of the second conductivity-type connected in series between the drain of the first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal. The second transistor and at least one and not all of the third transistors have a threshold voltage lower than a threshold voltage of the others of the third transistors.

Abstract: A precharge device is connected to an intermediate precharge node and is arranged to minimize leakage current through the precharge device when deactivated. An input transistor network receiving a plurality of data inputs is connected to the intermediate precharge node. An output inverter is connected to the intermediate precharge node and includes a pair of transistors. A predefined transistor of the pair of transistors is arranged to minimize leakage current through the output inverter. A standby control signal is asserted for a standby mode of the domino circuit and is unasserted for an active mode of the domino circuit. The standby control signal and a clock signal are combined to provide a combined standby clock signal. The combined standby clock signal controls the precharge device. A standby discharge device is connected to the intermediate precharge node and controlled by the standby control signal.

Abstract: A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.

Abstract: A semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; a plurality of logic circuits which are connected to the clock wiring to be synchronously operated in response to the clock signal; and a plurality of delay circuits, each of which is provided between a corresponding one of the logic circuits and the clock wiring for delaying the clock signal, wherein a delay amount of each of the delay circuits is designed so that the delay amounts of the clock signal from the output of the clock driver to the inputs of the logic circuits are equal to each other. Thus, it is possible to reduce clock skew and to evade an increase in layout area.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A logic circuit (200) having a critical path input signal (C2) that can have a reduced input capacitance and a logic output (D2) that can have a reduced voltage swing is disclosed. According to one embodiment, the logic circuit may include an input circuit (210), a driver circuit (220), and a load circuit (230). Driver circuit (220) can include stacked transistors (N4 and N5) of the same conductivity type, which can generate a logic output (D2) that can have a reduced voltage swing. Driver circuit (220) can generate a feedback signal that can control the impedance of a load circuit (230). Load circuit (230) can be actively controlled to improve the response of a logic evaluation node (V2).

Abstract: A high-speed sense amplifier includes a pair of cross-coupled inverters coupled to intermediate nodes and then to differential inputs nodes by a control circuit. The intermediate nodes are coupled together by a accelerator transistor that forms a current path when the sense amplifier is placed in a sensing state to provide parallel discharge paths for one or the other of output nodes. During precharge, the accelerator transistor operates to equalize the intermediate nodes to ready them for the next sense phase.

Abstract: A dynamic logic system is disclosed that uses transmission gates coupled between the inputs and output of inverting CMOS logic gates creating a “vented” CMOS logic gate (VCMOS). A clock is used to turn the transmission gates on during a pre-charge or “vent” cycle which causes the inputs and output of the VCMOS to go to an intermediate or vented state between a logic one and a logic zero. During an evaluation phase, inputs are applied to the VCMOS gate which will evaluate to a logic one or zero depending on the states of the inputs and the logic of the VCMOS gate. A family of vented CMOS gates are constructed by adding transmission gates in series with inputs or outputs to create input VCMOS (IVCMOS) and output VCMOS (OVCMOS) which are used to construct vented dynamic logic blocks (VDLB). A VDLB comprises groups of VCMOS gates which may be vented and isolated from other gates during venting.

Abstract: A vertical multi-threading processor includes one or more execution pipelines that are formed from a plurality of multiple-bit pipeline register flip-flops. The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage.

Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. The signal comparison system includes a plurality of latches that receive a first signal and a second signal and that transmit a respective value of the first signal in response to a transition of the second signal. Delay mechanisms delay the transition of the second signal before the transition is received by latches so that the transition is delayed different amounts relative to each of the latches. A feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.

Abstract: One embodiment of the present invention provides a system for asynchronously controlling state information within a circuit. This system includes a first conductor that carries a voltage indicating a state of the circuit, as well as a first drive circuit coupled to the first conductor that is configured to drive the first conductor to a first voltage level to indicate a first state. The system also includes a second drive circuit coupled to the first conductor that is configured to drive the first conductor to a second voltage level to indicate a second state. The system additionally includes a condition input that indicates a condition. The system is configured so that the first drive circuit drives the first conductor to the first voltage level based upon the condition indicated by the condition input.

Abstract: A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

Abstract: A dynamic logic gate receives a bias voltage at a data input terminal thereof that is designed to reduce leakage current within the gate. This reduction in leakage current improves the robustness of the dynamic logic gate without requiring the use of performance reducing high threshold voltage transistors within the gate. In one embodiment, the bias voltage is generated using a bootstrap capacitor that is connected to a virtual ground node of a static inverter in a domino logic chain. The bootstrap capacitor causes a small negative voltage to be applied to the virtual ground node in response to a clock signal. Under certain data conditions, the small negative voltage will be coupled to the input terminal of a subsequent dynamic logic gate in the logic chain to reduce leakage current within the subsequent gate.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.

Abstract: A charge booster for a node in a dynamic logic circuit having a logic function evaluation network that includes a switching network and a dominant input switching device adapted to receive a plurality of input signals. In one aspect of the present invention, a precharge transistor is first turned on by a clock signal during a precharge phase to precharge the node that is coupled to an output of the dynamic logic circuit. Concurrently, during the precharge phase, an evaluate transistor is turned off. Next, during an evaluate phase, the evaluate transistor is turned on by the control signal, i.e., clock signal, permitting the logic function evaluation network to perform the predefined logic function in accordance with the input signals received by the logic function evaluation network. The logic function evaluation network selectively charges or discharges the node to a voltage level based on the predefined logic function.

Abstract: A dynamic circuit having reduced dynamic node switching latency. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which data at the input of the dynamic circuit may or may not precipitate a dynamic node discharge. Each evaluation phase may be characterized as including an initial standby interval prior to the evaluation discharge, followed by an evaluate interval over which the dynamic node completes an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during an standby interval in which dynamic circuit inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance.

Abstract: A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.

Abstract: A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.

Abstract: In a semiconductor integrated circuit, the number of rows of transistors in each of first driver circuits is increased or decreased using MOS transistors group in clock driver circuits regions arranged in an array, such as in portions of circuit cell regions into which a core region is divided, in order to supply clock signals to cell, such as a megacell, through a mesh of interconnected clock signal supply lines, in the core region.

Abstract: A digital leakage compensation circuit for compensating for leakage in a dynamic circuit includes a dummy precharge circuit, a dummy input circuit, a dummy evaluation circuit, a dummy latching circuit, a sense circuit and a storage circuit. The dummy circuitry matches the size and layout of corresponding precharge, input, evaluation and latching circuitry in the dynamic circuit so that the leakage can be accurately modeled. The sense circuit senses the leakage and generates a signal, stored in the storage circuit, which causes an adjustable latching circuit to provide additional leakage compensation in the dynamic circuit. Alternatively, the dynamic circuit may include a driving circuit with an adjustable trip point. The sense circuit provides the signal to the driving circuit to adjust the trip point to compensate for the leakage.

Abstract: A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.

Abstract: Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.

Abstract: A logic circuit includes a dynamic logic stage driving a dynamic evaluation stage. The dynamic logic stage responds to input signals and a clock wave to derive an output signal that is a logic function of the input signals. The output signal is derived only during a first portion of each cycle of the clock wave. The evaluation stage responds to the output signal only during an initial segment of the first portion of each clock wave cycle.