Abstract: A circuit includes at least one input, an evaluate pulsed clock, and an output. In one embodiment, the circuit precharges an intermediate node in the circuit in response to a precharge pulsed clock and the evaluate pulsed clock.

Abstract: A control circuit of a control part sets the gate potential of a p-channel MOSFET of a driver part to a level lowering from a supply potential by at least the threshold voltage of the p-channel MOSFET while setting the gate potential of an n-channel MOSFET to a level rising from a low level of an input signal by at least the threshold voltage of the n-channel MOSFET in response to the input signal, thereby strongly turning on one of the p-channel MOSFET and the n-channel MOSFET and weakly turning on the other MOSFET.

Abstract: A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

Abstract: The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Abstract: A data transfer arrangement. The data transfer arrangement includes two active pull up/active pull down bus drivers and a voltage precharge source. A differential bus is coupled to the bus drivers and to the voltage precharge source. A latching sense amplifier is coupled to the differential bus and serves as the bus receiver. The bus drivers operate in a precharge phase and a data transfer phase. The bus receiver operates in an analogous but opposite manner, i.e., when the bus drivers are in the precharge phase, the bus receiver is in the data transfer phase and when the bus drivers are in the data transfer phase, the bus receiver is in a precharge phase.

Abstract: CMOS semiconductor dynamic logic (300) is disclosed, comprising dynamic logic circuitry (302) and tunneling structure circuitry (328) coupled to the dynamic logic circuitry; where the tunneling structure circuitry is adapted to hold a node (308) voltage stable by compensating leakage current originating from said dynamic logic circuitry.

Abstract: In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node. In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes. In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.

Abstract: One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage.

Abstract: A transistor is added to prior art domino logic circuits to create a modified domino logic circuit with a resistor divider connected between a first internal node and a second internal node. The resistor divider keeps the second internal node at a voltage that is higher than a second supply voltage VSS at the beginning of the evaluation phase of modified domino logic circuit. Consequently, the first internal node of the modified domino logic circuit will not start discharging until a higher voltage is reached by input signals. Thus, the input noise rejection of the modified domino logic circuits of the present invention is improved compared with prior art domino logic circuits.

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract: A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.

Abstract: A domino logic circuit includes a precharge device precharging a precharge node during a precharge phase and a logic block receiving plural input signals to conditionally discharge the precharge node. In this improvement a second precharge device precharges an intermediate node when a particular input signal controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device controlled by a second input signal different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node.

Abstract: In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit capable of stable operating at high speed.

Abstract: A method and apparatus for reducing bipolar current effects in dynamic logic circuits that are fabricated using the SOI technology is disclosed. A dynamic logic circuit capable of reducing bipolar current effects includes a precharge transistor (or a discharge transistor), a pass transistor, a functional logic circuit block, and an inverter. Connected in series with the precharge transistor, the functional logic circuit block, which includes multiple transistors, receives signal inputs. The pass transistor, connected in parallel with the precharge transistor, receives an identical input as one of the many transistors within the functional logic circuit block. The inverter, connected to a node between the precharge transistor and the functional logic circuit block, provides an output for the dynamic logic circuit.

Abstract: A logic gate for producing an output signal representing a logical operation of a first logic signal and a second logic signal includes a first input terminal for receiving the first logic signal and a second input terminal for receiving the second logic signal. The logic gate further includes a first transistor, a second transistor, and an evaluation node which is connected to a pre-charge device. The first transistor has a first terminal coupled to the first input, a second terminal coupled to the evaluation node, and a third terminal coupled to the second input. The second transistor has a first terminal coupled to the second input, a second terminal coupled to the evaluation node, and a third terminal coupled to the first input. A change in either of the logic signals triggers the logic gate, and a change in both of the logic signals within a predetermined time period results in the logic signals simultaneously canceling each other out.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

Abstract: A charge-redistribution low-swing differential logic circuit combining a differential logic network and a charge-redistribution circuit so as to provide a pair of complementary signals having only a small difference, thereby avoiding a time delay. Further, after a sense amplifier is used to amplify the signals, the resulting signals are outputted to sequential differential logic network, wherein the output swing can be reduced by a threshold voltage Vtn (Vtp) on a transistor. In addition, a pipeline is formed by the series connection structure controlled by a true-single-phase clock or by pseudo-single-phase clock, thereby achieving a designed circuit having high-speed and low power dissipation.

Abstract: Logic functions using dual rail dynamic logic circuits are implemented by cross-coupling a pair shunt transistors to the outputs. Preferably, the precharge nodes provide input to the gates of respective inverter drivers, each inverter formed as a p-channel field-effect transistor (pFET) and an n-channel field-effect transistor (nFET). The circuit's logic functions discharge the precharge nodes to ground. Therefore, one of the precharge nodes discharges to ground, while the other retains its positive precharge. The inverter drivers drive the discharged precharge node high, while the precharge node which retains its original charge is driven low. The shunt transistors are nFETs which connect the outputs of the inverter drivers to ground. The gate of each shunt transistor is driven by the output of the opposite inverter driver. The output which is driven by a discharged precharge node is relatively immune from noise, since there is a path from the precharge node to ground through several open transistors.

Abstract: A pipelined domino architecture includes pairs of pipeline stages each comprising a first active clocked stage and a number of subsequent self-reset logic gates. Each pipeline stage is clocked by one or the other of a clock signal. Each active clocked stage and self-reset logic gate of any particular pipeline state includes a reset circuit to reset the output of such stage or gate at the conclusion of an evaluation period that is initiated by a phase of the clock signal. Only the active clocked stage is clocked; the self-reset logic stages rely upon the reset of the output of the active clocked stage to generate the necessary reset signals that will reset their respective outputs.

Abstract: A MOS logic circuit includes: a pass-transistor logic circuit, including at least one first MOS transistor, for performing a predetermined logic operation to provide an output; and an amplifying circuit, including at least one second MOS transistor, for enhancing a driving capability of the output of the pass-transistor logic circuit. Each of the first MOS transistor and the second MOS transistor is a DTMOS transistor having a gate connected to an associated well in which a channel thereof is formed.

Abstract: A dynamic logic element and a dynamic logic circuit realized by using such dynamic logic elements which is not affected by a clock skew and is capable of operating at high speed. The dynamic logic element comprises a detecting circuit portion which receives an output signal of the dynamic logic element fed back thereto, which detects completion of a precharge operation, and which, upon detection of completion of a precharge operation, autonomously finishes a precharge phase and starts an evaluation phase. A plurality of the dynamic logic elements are coupled in tandem to form a domino logic circuit. A plurality of the domino logic circuits are coupled in tandem without interposing a buffer circuit therebetween to realize a high speed dynamic logic circuit.

Abstract: A domino logic circuit includes input connections to receive a clock signal and an input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal. The n-channel pull-up transistor has a low threshold voltage. The dynamic stage can include an n-channel pull-down transistor which has a gate connection coupled to receive the clock signal. First and second inverter circuits can also be provided to latch a voltage on a drain of the pull-down transistor. Static logic circuits coupled to the dynamic stage have skewed rise and fall times to increase the propagation time of the domino circuit.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A data storage circuit (50) has a data input (12′) for receiving a data voltage (D″) and a node (44) for receiving an interim voltage in response to the data voltage. The data storage circuit also includes an output enable circuit (34) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit has a transistor (40p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data retention circuit (46 and 48) has at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage. The data storage circuit includes a second node (58) for receiving a second interim voltage in response to the first interim voltage. A second output enable circuit (52) provides at least one conditional path for coupling the second interim voltage to the second node.

Abstract: An oscilator circuit for a integrated circuit memory device to optimize the refresh operating circuit and suppress wasteful power consumption in which the oscillator frequency is set high during high temperatures and the oscillator frequency is set low during low temperatures. A current I1 is generated by means of the current source 100a having characteristics in which it is increased during high temperatures and decreased during low temperatures, and is supplied to the ring oscillator 200.

Abstract: The OR gate circuit according to the present invention comprises a PMOS transistor for supplying a supply power depending on the clock signal, a plurality of PMOS transistors for outputting the supply power supplied from the PMOS transistor depending on inverted input signals, and a NMOS transistor for controlling the output depending on the clock signal.

Abstract: A low power differential signaling technique for reducing power in CMOS circuits. An input signal is provided to the input of a transmitter which uses transitions of the input signal to switch between two complementary resistive paths between upper and lower voltages across a common resistive element to develop a differential signal pair. In particular, during a high transition, a first pair of resistive switches are coupled across the common resistor causing current flow in a first direction and, during a low transition of the input signal, a second pair of resistive switches are coupled across the same common resistive element to cause current to flow in the opposite direction. The switching action converts a single-ended input signal to a differential signal pair across the common resistive element. The voltage swing across the differential signal pair is reduced to less than one half of the voltage differential between the upper and lower voltages which represent the source voltages.

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

Abstract: A method and apparatus for reducing leakage in dynamic Silicon-On-Insulator (SOI) logic circuits improves the performance of dynamic gates implemented in SOI technology. A bias generator is used to create a negative potential by using the pre-charge input signal to bootstrap a bulk capacitor charging circuit, shifting a positively charged bulk capacitor terminal to ground, causing a negative potential at the other terminal. A bias control circuit applies this negative potential to intermediate nodes of logic input ladders of a dynamic logic gate to reduce leakage and threshold lowering effects due to the voltage variation on the bodies of logic input transistors implemented in SOI logic.

Abstract: Circuit for reducing a standby current, is disclosed, including a PMOS transistor connected to a power supply voltage terminal, an NMOS transistor connected to a ground voltage terminal, and a switching device between the PMOS transistor and the NMOS transistor for cutting off a leakage current flowing to the NMOS transistor through the PMOS transistor, whereby minimizing a leakage current and shortening a time period for going from a standby state to an active state.

Abstract: A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on an external clock, several “one-shot” internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented ir the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.

Abstract: Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.

Abstract: In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced.

Abstract: A domino logic circuit includes input connections to receive a clock signal and at least one input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising precharge circuitry, and a static stage that comprises discharge circuitry. In another embodiment, the domino logic circuit includes a dynamic stage comprising discharge circuitry, and a static stage that comprises precharge circuitry. Different configurations and transistor types have also been described. The circuitry can provide improved speed performance, or increase noise immunity.

Abstract: An integrated circuit (100) includes an input buffer circuit (122) having an input stage (150), a delay element (178), inverter (176), and a level shifter (156). The input stage (150) receives an input signal and a first power supply voltage. The level shifter (156) has a pair of cross-coupled P-channel transistors (158 and 160) coupled to a second power supply voltage. The second power supply voltage is different than the first power supply voltage. The cross-coupled P-channel transistors (158 and 160) are coupled to first and second N-channel transistors (162 and 164). Each of the first and second N-channel transistors (162 and 164) and transistors (152, 154) of the input stage (150) have relatively thick oxide layers. A gate of the first N-channel transistor (162) is coupled to the output of the input stage (150). A gate of the second N-channel transistor (164) is coupled to receive the input signal.

Abstract: A circuit for stalling data in a domino pipeline. The circuit includes a logic network having multiple inputs coupled to receive multiple input data signals. The logic network generates an output signal on an output node based on a logic evaluation of the multiple input data signals. The circuit also includes a feedback circuit coupled to the logic network to maintain the output signal on the output node based on a stall input signal.

Abstract: A pseudo-NMOS logic gate of an integrated circuit chip is enabled for a time interval that is substantially less than one-half a clock cycle of the integrated circuit. A latch responds to an output signal of the pseudo-NMOS logic gate for a period that is simultaneous with or slightly less than the time while the pseudo-NMOS logic gate is enabled. The latch derives an output signal commensurate with the output signal of the pseudo-NMOS logic gate while the pseudo-NMOS logic gate is enabled, until the next clock cycle occurs.

Abstract: A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal path to form both an output signal and a complement of the output signal for use in subsequent logic stages.

Abstract: A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two binary inputs adapted to receive corresponding input binary digits, the circuit includes: (1) a combinatorial logic power down circuit that develops a power down signal as a function of an input-data signal and at least one of the input binary digits and (2) a switch, coupled to the power down circuit, that interrupts DC current to at least a portion of the logic gate as a function of the power down signal.

Abstract: An integrated circuit (10) is disclosed that has a dynamic logic stage (12) with reduced standby leakage current. The integrated circuit (10) includes a logic gate (20) coupled to a dynamic node (NODE 1) of the dynamic logic stage (12). The logic gate (20) has a first voltage supply terminal and a second voltage supply terminal. The logic gate (20) consumes standby leakage current when the dynamic logic stage (12) is not in an evaluation phase or when the clock is idle. A transistor (30) has a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal. The drain of the transistor (30) provides an intermediate node (NODE 4) for supplying voltage to the logic gate (20).

Abstract: An integrated circuit having dynamic logic (20) is disclosed that includes a dynamic node (NODE 1). A feedback stage protects the dynamic node (NODE 1) and includes a controllable current path (26) connected between a voltage supply and the dynamic node (NODE 1), where the controllable current path (26) has a control terminal. The feedback stage also includes a feedback path from the dynamic node (NODE 1) to the control terminal, where the feedback path includes a delay stage (27) providing a delay greater than intrinsic circuit delay.

Abstract: A logic gate is provided that comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. The sensing circuit is adapted to sense a voltage on the internal node and to output a signal indicating a level of the voltage. The sensing circuit is not used during normal operation of the logic gate and preferably comprises only a single FET that is directly coupled to both the internal node and to the test output. The logic gate also preferably comprises a pre-charge circuit for pre-charging the test output to a predetermined voltage level prior to testing. An IC chip may be formed from a plurality of the logic gates wherein each logic gate comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. Each sensing circuit may be coupled to the same test output or to a unique test output for the sensing circuit's logic gate. The sensing circuits are not used during normal operation of the IC chip.

Abstract: A dynamic logic circuit (16) operable in an active mode and in a power down mode, where the active mode comprises a precharge phase and an evaluate phase. The dynamic logic circuit comprises a precharge node (18PN) coupled to be precharged to a precharge voltage (VDD) during the precharge phase and operable to be discharged during the evaluate phase. The dynamic logic circuit further comprises a conditional series discharge path connected to the precharge node and comprising a plurality of transistors (18L, 18DT, 20SDVN) operable to conditionally couple the precharge node to a voltage different than the precharge voltage. Further, the dynamic logic circuit comprises an output inverter (18INV) having an input connected to the precharge node and comprising a plurality of transistors (18INVP, 18INVN) for providing an output signal representative of a voltage at the precharge node during the evaluate phase.

Abstract: A semiconductor integrated logic circuit device with a sequential circuit includes a transferring section, an inverting section, a bistable circuit section, and a blocking section. The transferring section is provided between first and second nodes, and transfers a data signal from the first node to the second node in response to a clock signal. The inverting section is provided between the second node and a third node, and inverts the data signal on the second node to output on the third node as an inverted data signal. The bistable circuit section is connected to the second and third nodes, and holds the data signal. The blocking section is provided between the bistable circuit and the first node, and blocks off sub-threshold leakage current.

Abstract: A method is provided for precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after a second shorter predetermined delay.

Abstract: A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.