Abstract: A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.

Abstract: An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit, an output inverter and a feedback path circuit. The charge and discharge path circuit connects to a common output node and generates a potential on its output terminal in accordance with a first grounding path on or not. The voltage hold circuit controls a voltage of the common output node in accordance with both a second grounding path on or not and the potential on the output terminal of the charge and discharge path circuit. The output inverter generates and next outputs an inverted voltage on its output terminal in accordance with the potential on the output terminal of the charge and discharge path circuit. The feedback path circuit connects to output terminals of the charge and discharge path circuit and the output inverter.

Abstract: A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the transducer and a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET's threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed. The control circuit reduces switching time and reduces current spikes in the power supplies to the chip.

Abstract: A low power dynamic circuit with an inverter-like output is disclosed. The dynamic circuit includes a precharge circuit, a discharge circuit, and an output circuit. The precharge circuit charges a precharge node from the clock signal when the data input signal is low and the clock input is high. The discharge circuit discharges a discharge node to the clock signal when the data input signal is high and the clock input is low. The output circuit is an inverter-like configuration that uses the precharge node to generate a logic high and the discharge node to generate a logic low, as required by the data input signal. In one embodiment, the precharge circuit is operative with a first clock and the discharge circuit is operative with a second clock. In yet another embodiment, there is only a precharge circuit and an output circuit.

Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.

Abstract: A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.

Abstract: An improved logic methodology that combines the speed advantages of dynamic logic with the low contention of static logic, such that the logic circuits are not adversely affected by high-leakage transistors. The logic circuit of the present invention comprises first and second stages, wherein first logic stage comprises clocked precharge and evaluate transistors and full-complementary low-beta-ratio static logic. Subsequent stages of the logic circuit comprise full-complementary low-beta-ratio static logic, wherein the logic devices in the subsequent stages are not connected to a clock signal. The low-beta-ratio static logic devices in said subsequent stage comprise pMOS transistors that are not connected to a contention keeper. Furthermore, the low-beta-ratio static logic transistors in the subsequent stage comprise pMOS transistors that are significantly smaller than pMOS devices found in normal static logic.

Abstract: An apparatus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.

Abstract: Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In particular, to reduce delays related to gates between the input pin for the system clock and a normal input gate, dual, substantially independent paths are implemented: a scan path and a normal input path. Embodiments coordinate transmission of data from a normal input gate and a scan input gate to an output latch, a scan out pin, and/or combinational logic by incorporating buffers that isolate a wired-or node from either the scan input gate, the normal input gate, or both with a high impedance.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously.

Abstract: An LSDL circuit has both an output and a complementary output generated by inverting the output with an inverter logic gate. A keeper PFET is added by coupling its drain terminal to the dynamic node. The keeper PFET has its source terminal coupled to the positive power supply voltage and its gate terminal coupled to the complementary output. The output and the dynamic node may both be at a logic one when the output is a logic one from the previous evaluation cycle and the dynamic node is precharged. In this case, the complementary output is a logic zero which turns ON the keeper PFET and reinforces the precharge on the dynamic node. When the output is evaluating to a logic zero, the output will transition quickly to a logic zero. If the output is transitioning from a logic zero to a logic one, then the keeper PFET is OFF and does not affect the dynamic node.

Abstract: A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged internal nodes of the dynamic logic circuit, respectively. The second inputs of the first and second gates are connected to a first and second differential outputs of the dynamic logic circuit, respectively. The first inputs of the third and fourth gates are connected to an output of the first and second logic gates, respectively. The second input of the fourth gate is connected to an output of the third logic gate to provide a first output for the latch circuit. Similarly, the second input of the third logic gate is connected to the output of the fourth logic gate to provide a second output for the latch circuit.

Abstract: An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the request signal indicates the arrival of a distinct new data item. Each stage comprises a data latch that is normally enabled to allow data to pass through, and a latch controller that enables and disables the data latch. The request signal and the data are inputs to the data latch. Once the stage has latched the data, a done signal is produced, which is sent to the latch controller, to the previous stage as an acknowledgment signal, and to the next stage as a request signal. The latch controller disables the latch upon receipt of the done signal, and re-enables the data latch upon receipt of the acknowledgment signal from the next stage. For correct operation, the request signal must arrive at the stage after the data inputs have stabilized.

Abstract: A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.

Abstract: A teacher-pupil flip-flop with reduced register delay including a gate circuit, a stack circuit, a keeper circuit, a teacher output circuit, a latch circuit and a pupil output circuit. The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack circuit, coupled to the gate circuit output and to an input, switches an intermediate node pair to a preliminary state when the clock signal is low, and to a data state indicative of the input after the setup delay when the clock signal goes high. The keeper circuit maintains the data state and the teacher output circuit drives the output based on the data state while the clock is high. The latch circuit stores the data state and the pupil output circuit drives the output with valid data from the latch circuit after the clock signal goes low.

Abstract: It is an object of the invention to provide a circuit configuration wherein a decoder control signal ?2 is rendered unnecessary between an address buffer control signal ?1 and the decoder control signal ?2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.

Abstract: A data storage element for use in LSSD compliant circuit designs. The data storage element has an alternate, or scan, data input circuit that has increased immunity to electrical noise while maintaining lower power consumption than the circuits used for primary data input. This increased noise immunity reduces the probably that noise on the alternate data input will cause an unintended change of data state stored in the data storage element. Modification of latch circuits used in the data storage element allow a reduction in the number of transistors used in the latch circuits, thereby compensating for the increase in transistors used in the alternate data input circuit and allowing the data storage element to use the same number of transistors as prior designs that have less noise immunity on their alternate data inputs.

Abstract: A method of interstitial pre-discharge in a circuit includes providing the circuit, which includes a pre-charge node coupled to a clock evaluate node operable to receive a clock evaluate input cycle. Multiple pull-down stacks each including an interstitial node interconnect between the pre-charge node and ground. The interstitial node of each pull-down stack couples to an interstitial discharger device gated to ground. The method further includes operating the circuit in a pre-charge phase of the clock evaluate input cycle, including pre-charging the pre-charge node and the interstitial nodes, and keeping the devices in the pull-down stacks and the interstitial dischargers in a high impedance state. The method additionally includes operating the circuit in an evaluate phase of the clock cycle, including discharging the pre-charge node to ground through a pull-down stack, and discharging the interstitial node to ground through the interstitial discharger device to preclude charge share.

Abstract: An integrated circuit that converts a single rail signal into a dual-rail signal includes a clock signal connection, a data input to which a single-rail signal is applied, a data output on which a dual-rail signal is tapped off on output lines, and a converter, which is connected between the data input and the data output, that converts the single-rail signal into the dual-rail signal. The converter includes a memory cell having an input connected to the data input and output connections, wherein in a transparent state, the output connections provide the logically valid dual-rail signal, and a circuit arrangement, which is arranged between the output connections of the memory cell and the data output of the integrated circuit, that precharges the output lines connected to the output connections, and ensures a direct transition from a precharge phase to a logic state on the output lines, and vice versa.

Abstract: An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.

Abstract: An integrated circuit is disclosed that includes one or more blocks of switching logic (comprised of transistors) connected between a power supply and a common node. A control transistor connects the common node to ground. The control transistor has a higher threshold voltage level than the voltage threshold level(s) of the transistors that comprise the switching logic blocks. A bias generator provides a positive bias to the body of the control transistor when the control transistor is “on.” Further disclosed is an integrated circuit comprising a first plurality of serially connected transistors establishing a first current path from a voltage source to ground and a second plurality of serially connected transistors establishing a second current path from the voltage source to ground. The first and second plurality of transistors each includes at least one high-threshold transistor.

Abstract: A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.

Abstract: The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.

Abstract: An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.

Abstract: An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.

Abstract: A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.

Abstract: The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.

Abstract: A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Abstract: A high-speed domino logic with improved cascode keeper circuit uses an inverter delay element and an additional transistor to introduce a transition delay time and node isolation time to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of high-speed domino logic with improved cascode keeper circuit. The high-speed domino logic with improved cascode keeper circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only a minimum of one new inverter and one new are required, the modification of the invention is space efficient and readily incorporated into existing designs.

Abstract: A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second embodiment, a low-swing circuit at the output reduces the output and keeper transistor gate voltage swings. A third embodiment combines those two techniques.

Abstract: An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Abstract: LSDL logic is provided with circuitry that has logic controls to provide two modes of operation. The half latch and the PFET that normally forms the keeper function on the dynamic node are modified. The inverter function of the series connected PFET and NFET have their corresponding positive and negative power supply terminals coupled to logic gates. In this way, the inverter may be turned ON so that the half latch functions as a keeper or it may be turned OFF to remove it from operating at all in the mode where the LSDL logic circuit needs to operate with a fast pulse clock. Likewise, the positive supply voltage may be removed while allowing the NFET device to operate to turn ON the PFET pull-up device for burn-in operation.

Abstract: An apparatus and method for a pseudo-dynamic latch are disclosed. A deracer circuit includes a first logic gate configured to receive a data signal from a domino logic circuit and to invert the data signal. A second logic gate is configured to receive the inverted data signal and an inverted select signal and to generate a select signal. Thus, the deracer circuit is configured to prevent the select signal from being high when a precharge edge of a data signal arrives.

Abstract: Methods and arrangements for enhancing domino logic are disclosed. Embodiments include a keeper circuit to pull up a domino node in response an output of an output circuit when the domino node is at a high voltage and to stop pulling up the domino node before the output changes to a first logical output. Further embodiments include an accelerator circuit to pull down the domino node when the keeper circuit stops pulling up the domino node. The domino node may couple with a pre-charge circuit and be pre-charged to a high voltage during a first portion of a clock cycle. The domino node may also couple with a logic input circuit to pull down the domino node during a second portion of the clock cycle, causing the output circuit to change the output from low to high in response to logic signals.

Abstract: In a synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. Consequently, the synchronous clocked full-rail differential logic circuits with single-rail logic and shut-off of the invention are smaller, less complex and are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient and is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.

Abstract: A shift register includes at least one stage circuit that has at least three voltage control switches, a storage element, and a first clock signal, a second clock signal and a third clock signal to control various switches. Input signals are stored in the capacitor and sequentially transferred to the next stage. During transferring to the next stage, pixel switches of one row on the panel display are activated to receive information delivered from the data end for displaying on the pixels. The clock signals have the characteristics that the first clock signal, second clock signal and third clock signal are not at the same certain potential concurrently to prevent the switches of each stage (the second and third switches) from forming a DC path and burning out.

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to coupl

Abstract: A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto. By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%.

Abstract: A pulse clock is generated by a pulse generator from a system clock. This pulse determines when the output of a high fan-in gate is to be latched. The pulse clock also feeds a latch with no pass gate and sets the timing of the high fan-in dynamic gate. Because of the length of the active time of the pulse clock, the high fan-in dynamic gate does not have a holder.

Abstract: A pseudofooter circuit for a logic circuit includes a first FET (Field Effect Transistor) having a first source, a first drain, and a first gate, and a second FET having a second source, a second drain, and a second gate. The first source is connected to the second drain to become a first signal node. The first signal node is connected to at least one gate of an FET in the logic circuit. The first gate is connected to the second gate to become a second signal node receiving a second signal as an input signal. The second source is connected to ground. The first drain becomes a third signal node receiving a third signal as an input signal.

Abstract: Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.

Abstract: An embodiment of the invention provides a circuit and method for improving noise tolerance in multi-threaded memory circuits. A PFET is added to the receiving input of each memory cell. The gate of the PFET is connected to the output of the memory cell and the source of the PFET is connected to the control signal of the memory cell. In the case where the dataline is charged near ground and a memory cell, with a high value, is read, and the control signal is high, noise tolerance is improved by the addition of the PFET to the memory cell. The invention does not introduce additional drive fights during writes, when the control signal is low.

Abstract: A system and method, for converting a voltage input from a low voltage source to a voltage output at a high voltage source using a domino logic circuit design. An embodiment provides a low to high voltage conversion system. The system includes: a pull-up transistor coupled to a high voltage source for charging a node, when a precharge signal is received; a low voltage source used for setting an input voltage; a pull-down network for discharging the node depending, at least in part, on the input voltage; and an output voltage determined from the node.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

Abstract: A bulk input differential logic circuit. The circuit outputs a large signal high enough to assert a logic High and Low by variations of the threshold voltage controlled by the bulk input signal and amplification of the sense amplifier. A boost circuit is disposed on the bulk input terminal, which may receive multiple bulk input signals. This makes it possible to use fewer circuit elements and smaller circuit area for a complicated logic operation.

Abstract: In a synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. Consequently, the synchronous clocked full-rail differential logic circuits with single-rail logic and shut-off of the invention are smaller, less complex and are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient and is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure.