Abstract: A pre-charge control circuit includes a control unit, a conversion unit, and a pre-charge switch. The control unit provides a control signal according to a PWM signal, and the conversion unit provides a control voltage according to the control signal. The pre-charge switch adjusts a magnitude of the current flowing through the input path of the electronic circuit according to the control voltage.

Abstract: In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

Abstract: An electrical switching system includes a constant-power controller and a switching device electrically coupled between a first node and a second node. The constant-power controller is configured to (a) generate a digital control signal to control the switching device, (b) control a duration of an active phase of the digital control signal at least partially based on a voltage across the switching device, and (c) control a peak value of the digital control signal to regulate a peak magnitude of current flowing through the switching device.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: A power converter is provided. The power converter includes two or more hybrid switching circuits electrically connected to a source or storage element. Each switching circuit includes a wide bandgap device that is parallel-connected to a silicon-based device. The converter further includes a controller that is operatively coupled to each device of the first and second switching circuits. The controller is configured to operate each hybrid switching circuit by (i) activating the silicon-based device for an activation period, (ii) activating the wide bandgap device for a predetermined duty cycle less than the activation period, (iii) deactivating the silicon-based device while the wide bandgap device is activated, and (iv) deactivating the wide bandgap device. The hybrid switching circuits are sequentially operated to convert an alternating current of a power supply into a link voltage for a power converter, for example.

Abstract: A drive circuit has a control signal input for receiving a first control signal at a first circuit input, an optocoupler which is connected to the control signal input and which is adapted to generate a galvanically decoupled second control signal in accordance with the first control signal, an output circuit for controlling at least one circuit output terminal of the drive circuit in accordance with a third control signal, and an electronic control circuit comprising an energy supply, an input for receiving the second control signal, and an output for outputting the third control signal in accordance with the second control signal received at the input.

Abstract: A system and method for measuring optical power is described. The optical system and method may include a module configured to generate a secondly modulated signal based on secondly modulating a firstly modulated signal with an amplitude modulated signal. The firstly modulated signal may include data that is modulated for transmission by a laser diode array. The firstly modulated signal may then be secondly modulated using amplitude modulation techniques. The system may further include a photodiode configured to generate a photodiode current based on optically sensing a laser diode array. The laser diode array outputs an optical output power based on being driven by the secondly modulated signal. The system may yet further include a controller configured to calculate the optical output power from the photodiode current based on the amplitude modulated signal.

Abstract: The invention provides a voltage-following series power supply circuit, comprising a power supply end and a ground end; a power supply module comprising an input end connected to the power supply end, and an output end for providing a power supply to two or more to-be-powered chips, the power supply module and the to-be-powered chips connected in series between the power supply end and the ground end; and at least one auxiliary power supply module for supplying an auxiliary power supply to the to-be-powered chips, wherein a voltage following module is further connected between the power supply end and the auxiliary power supply module for adjusting a voltage of the auxiliary power supply.

Abstract: An apparatus leverages the existing power interconnect for DC power delivery by including a persistent DC power module into a power panel, thereby enabling a more efficient use of the energy. The persistent DC power module includes, in part, a control unit which is adaptive to the variations and availability of the external DC power source to ensure a constant and consistent delivery of DC voltage. The apparatus minimizes energy waste and e-waste, and is compatible with the existing legacy AC infrastructure.

Abstract: A driving circuit includes first and second driving units connected in parallel to each other, wherein both the first and second driving units start to supply a gate current to a gate of a switching device in a turn-on operation of the switching device, when a gate voltage of the switching device increases and has reached a threshold voltage of the switching device, the first driving unit continues to supply the gate current, and the second driving unit stops supply of the gate current before the gate voltage has reached the threshold voltage.

Abstract: A semiconductor device includes a normally-off power transistor integrated in a semiconductor die and a first failsafe pulldown circuit. A gate of the normally-off power transistor is electrically connected to a control terminal of the semiconductor die. The first failsafe pulldown circuit includes a first normally-on pulldown transistor integrated in the semiconductor die and a turn-off time control circuit. A gate of the first normally-on pulldown transistor is electrically connected to a first reference terminal of the semiconductor die. The first normally-on pulldown transistor is configured to pull down the gate of the normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal. The turn-off time control circuit is configured to control a turn-off time of the normally-off power transistor.

Abstract: A circuit and method for detecting a failure of a switching power device is disclosed. The circuit and method utilize a Kelvin connection of a four-terminal configuration of the switching power device to sense a resistance of at least one wire-bond. The resistance corresponds to a defect or defects in the at least one wire-bond and so it can be used to detect a failure before damage occurs. A threshold used for detecting the failure can be adjusted to accommodate variations in the switching power device and/or the application in which it is being used. Additionally, the failure detection is carried out at a period after the switching power device is turned ON to prevent switching transients from affecting the detection.

Abstract: The present disclosure relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor, in which a barrier region is in a mesa between adjacent trench gates to divide the width of the mesa, thereby inducing the accumulation of hole carriers, and thus reducing an on-resistance (e.g., of the IGBT).

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: injecting charge carriers at a first rate into an upper base of the transistor, the injecting at the first rate results in current flow through the transistor from an upper collector-emitter to a lower collector-emitter, and the current flow results in first voltage drop measured across the upper collector-emitter and the lower collector-emitter; and then, within a predetermined period of time before the end of a first conduction period of the transistor, injecting charge carriers into the upper base at a second rate lower than the first rate, the injecting at the second rate results in second voltage drop measured across the upper collector-emitter and the lower collector-emitter, the second voltage drop higher than the first voltage drop; and then making the transistor non-conductive at the end of the conduction period.

Abstract: In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

Abstract: Driver circuitry for driving a power semiconductor switch having a control input and main terminals is described. The driver circuitry includes control terminal driver circuitry coupled to the control input and configured to provide a drive signal, a sense terminal coupled to the main terminal, a current mirror coupled to the sense terminal to mirror a current input into the sense terminal during turn-off, a first current comparator configured to compare a current signal received from the current mirror to a first current threshold and output a first signal representative of the comparison, and a second comparator configured to compare a signal received from the sense terminal to a turn-on threshold and output a second signal representative of the comparison. The turn-on threshold represents a highest voltage of the main terminal during turn-on. The first current threshold represents a highest voltage of the main terminal during turn-off.

Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.

Abstract: A semiconductor device includes: a test transistor which is formed over a substrate; a test pattern structure which is formed in an upper portion of the substrate to be spaced apart from the test transistor; and a protection transistor which is positioned between the test pattern structure and the test transistor.

Abstract: Techniques for controlling a power converter with a control signal and circuitry configured to translate the control signal into one or more pulse modulated drive signal(s) to operate the power converter. The translation circuitry may receive the control signal, extract frequency information, duty cycle, dead time, and other information from the control signal, and output at least one pulse modulated drive signal, based on the extracted information, to a driving stage that may operate the power converter. The control signal may be a digital signal that includes rising edges and falling edges. The edges of the first type may define the frequency information. The edges of the second type may define other information extracted by the translation circuitry, e.g., duty cycle, dead time and so on. In some examples the power converter may be a resonant power converter.

Abstract: A driver circuit controls an output unit that switches whether or not to supply a current to an output line, in accordance with a potential difference between a first control signal to be input and a voltage of the output line. The driver circuit has a control line transmitting the first control signal to the output unit; a connection switching unit switching whether or not to connect the control line and the output line; a pre-stage control unit that is provided between a high potential line and a low potential line and selects and outputs a potential of any one of the high potential line and the low potential line in accordance with a second control signal; and a post-stage control unit causing the connection switching unit to connect the control line and the output line when the pre-stage control unit outputs a voltage higher than a predetermined threshold value.

Abstract: Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be coreless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.

Abstract: The present invention discloses a double-gate trench-type insulated-gate bipolar transistor device. A first trench and a second trench, which are located in a P-type doped well layer, and separate from each other, are extended into a lightly-doped N-type drift layer. A heavily-doped P-type source region and a heavily-doped N-type source region, which are sequentially connected, are located between the first trench and the second trench, and are arranged at an upper part of the P-type doped well layer in a horizontal direction. The heavily-doped P-type source region is located at a periphery of the second trench, a middle part and the upper part of the P-type doped well layer are provided with an N-type doped well layer and a P-type doped base region layer, respectively. The heavily-doped P-type source region and the heavily-doped N-type source region are both located at an upper part of the P-type doped base region layer.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.

Abstract: Systems and methods are provided for implementing a phased array antenna having a boresight direction. A scan angle within a defined range of scan angles is selected for the phased array antenna such that the selected scan angle is different from a scan angle associated with the boresight direction. An antenna port impedance associated with each of a plurality of antenna elements comprising the phased array antenna varies with the scan angle of the phased array antenna. A plurality of amplifiers are each coupled to an antenna port of one of the plurality of antenna elements. Each of the plurality of amplifiers is configured such that a maximum value for a performance characteristic of the plurality of amplifiers is achieved when an impedance at the antenna port corresponds to the selected scan angle.

Abstract: To prevent an output of an intermediate potential by suppressing sneaking of a current from a signal line to a power line at the time of disconnection of a power supply. A control circuit which receives a power supply voltage from a power line L11 and outputs an output signal to a signal line L12 includes: a load R11 which is provided between the power line and the signal line; a first transistor P11 which is provided between the load and the signal line; a second transistor P12 which is provided between a well of the first transistor and the power line; and a gate control circuit 15 which connects a gate terminal of the first transistor and a gate terminal of the second transistor to the signal line and turns off the first transistor and the second transistor, at the time of disconnection of a power supply.

Abstract: An output driving circuit includes a pull-down driver and a voltage stabilizer. The pull-down driver includes first, second, and third transistors connected in series between a pad and a ground node. The voltage stabilizer generates a stabilization voltage based on a voltage of the pad and a power voltage, and outputs the stabilization voltage to a control terminal of the second transistor.

Abstract: Apparatuses and methods for setting operational parameters of a memory based on location are disclosed. The operational parameters may include operational parameters for an input/output circuit. For example, operational parameters may be for output driver circuit impedance, equalization for input receiver circuits, termination impedance, as well as others. Location information is provided to a memory device and used for setting the operational parameter. A nominal operational parameter setting may be offset based on the location information, thereby tailoring the operational parameter of the memory device according to location in some examples. The location information may be memory slot address for location based on memory module location. The location information may be related to a location of a memory device within a sub-system. The location information may be provided to unused terminals of a memory device, for example, unused data terminals in some examples.

Abstract: According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor.

Abstract: A switch drive circuit is provided with a surge detecting unit that detects a surge voltage produced in response to a change in a switching state of the switch; an adjusting unit that adjusts, based on the surge voltage detected by the surge detecting unit, a switching speed of the switch when changing the switching state of the switch; and a mask processing unit that prevents a voltage, detected by the surge voltage detecting unit in a period other than a period where the surge voltage is assumed to be produced in response to a change in the switching state of the switch, from being used by the adjusting unit for adjusting the switching speed.

Abstract: A circuit device and a method for safely disconnecting a semiconductor switching element, in particular a MOSFET, are provided, wherein the semiconductor switching element comprises a gate terminal, a source terminal and a drain terminal, wherein, during operation of the semiconductor switching element, a current path between the drain terminal and the source terminal can be reversibly disconnected by the gate terminal, and the gate terminal comprises a gate voltage potential and the source terminal comprises a source voltage potential. A fuse unit is arranged between the gate terminal and the source terminal, which fuse unit is set up and designed, as a function of a potential difference between the gate voltage potential and the source voltage potential, so as to electrically connect the gate terminal to the source terminal after the current path is disconnected, so that the gate voltage potential and the source voltage potential are adapted.

Abstract: This disclosure relates to a discrete semiconductor device and associated method of manufacture, the discrete semiconductor device includes: a high voltage depletion mode device die; and a low voltage enhancement mode device die connected in cascode configuration with the high voltage depletion mode device die. The high voltage depletion mode device includes a gate, source and drain terminals arranged on a first surface thereof and the gate source and drain terminals are inverted with respect to the low voltage enhancement mode device die and the low voltage device is arranged adjacent to the high voltage device.

Abstract: A controller comprising a driver interface referenced to a first reference potential, a drive circuit referenced to a second reference potential, and an inductive coupling. The driver interface comprises a first receiver configured to compare a portion of signals having a first polarity on the first terminal of the inductive coupling with a first threshold, and a second receiver configured to compare a portion of signals having a second polarity on the second terminal of the inductive coupling with a third threshold. The drive circuit comprises a first transmitter configured to drive current in a first direction in the second winding to transmit first signals, and a second transmitter configured to drive current in a second direction in the second winding to transmit second signals, the second direction opposite the first direction.

Abstract: A T-type DC circuit breaker includes a main branch, a first commutation switch, a second commutation switch, and a bypass branch. The first commutation switch and the second commutation switch are arranged at both ends of the main branch, respectively. The bypass branch is connected in parallel with the main branch. The main branch includes at least one half-controlled power electronic component. The bypass branch includes a bypass capacitor and a bypass diode connected in series. Each of the first commutation switch and the second commutation switch includes at least one fully-controlled power electronic component. The first commutation switch is connected in parallel with a first surge arrester, and the second commutation switch is connected in parallel with a second surge arrester. The grounded branch is arranged between the main branch and the second commutation switch and is grounded or connected to the negative terminal of the load.

Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.

Abstract: A circuit includes a protection circuit and a gate driver coupled to a power supply voltage node configured to have a power supply voltage level. The protection circuit generates a first signal having a first logical voltage level when the power supply voltage level is equal to or greater than a threshold voltage level, and having a second logical voltage level when the power supply voltage level is less than the threshold voltage level. The gate driver receives the first signal and a second signal, and, when the first signal has the first logical voltage level, outputs a third signal based on the second signal, and when the first signal has the second logical voltage level, outputs the third signal having a predetermined one of the first or second logical voltage levels.

Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

Abstract: A switching element 1 has a gate terminal connected to an output end Vout of a driving circuit 12 via a capacitor 11 and a resistor 13 connected in parallel. The switching element 1 has a source terminal connected to the driving circuit 12 via a capacitor 14 and a Zener diode 15 connected in parallel. The Zener diode 15 has an anode terminal connected to the source terminal of the switching element 1 and a cathode terminal connected to the driving circuit 12.

Abstract: A control circuit for driving a power switch in a switching power supply can include: a start-up transistor having a drain coupled to a drain of the power switch, and a source coupled to a drain voltage detecting circuit; a gate voltage detecting circuit configured to detect a gate voltage of the power switch, to compare the gate voltage against a first threshold voltage, and to change an on drive current and an off drive current in response thereto; and the drain voltage detecting circuit being configured to detect a drain voltage of the power switch, to compare the drain voltage against a second threshold voltage, and to change the on drive current and the off drive current in response thereto.

Abstract: Field-effect transistors and methods of manufacturing the same are described herein. An example field-effect transistor includes a substrate, a source above the substrate, a semiconductor region above the source, a drain above semiconductor region, a polarization layer disposed on the semiconductor region between the drain and an end of the semiconductor region, and a gate above the source adjacent the end of the semiconductor region.

Abstract: In an overcurrent determining apparatus, a temperature obtainer obtains a temperature parameter indicative of a temperature of a switching element as a temperature measurement value. A determination voltage has a first voltage value when the temperature measurement value is a first temperature. A setter sets the determination voltage to a second voltage value upon determining that the temperature measurement value is a second temperature higher than the first temperature. The second voltage value is lower than the first voltage value and higher than a value of a Miller voltage of the switching element at the second temperature.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: A semiconductor device includes a first terminal, a second terminal, a first transistor, and a switching circuitry. In the first transistor, an anode of a body diode is connected to the first terminal, and a cathode of the body diode is connected to the second terminal. The switching circuitry is connected between a gate and a source of the first transistor, and switches a connection state between the gate and the source of the first transistor.

Abstract: A power module includes: an embedding structure comprising an electrically insulating body; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a terminal of the embedding structure through one or more second electrically conductive paths embedded in the electrically insulating body.

Abstract: This invention provides a current self-checking regulation circuit based on voltage calibration including a bandgap reference unit, a self-calibration unit, a detection and regulation unit, current mirror units, and a current mirror control unit. The bandgap reference unit is configured to generate a voltage signal, the self-calibration unit is configured to respond to a digital signal of the detection and regulation unit and calibrate the voltage signal of the bandgap reference unit. The detection and regulation unit samples the reference current signal and a mirror current signal of the regulation group current mirror unit and generate a digital control signal according to the reference current signal. and the reference group current mirror unit responds to the digital control signal and outputs a regulated bias current signal meeting needs of the laser driver.

Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.

Abstract: The present invention concerns a device and a method for controlling the switching from a conducting state to a non conducting state or from a non conducting state to a conducting state of a semiconductor power switch providing current to a load, the device receiving an input signal that is intended to drive the semiconductor power switch. The invention: —senses the derivative of the drain to source current going through the semiconductor power switch in order to obtain a voltage representative of the sensed derivative of drain to source current, —amplifies the voltage representative of the sensed derivative of drain to source current, —adds the amplified voltage representative of the derivative of the sensed drain to source current to the input signal during a given time period.

Abstract: In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.

Abstract: A switching circuit includes; a switching element; a driver; a diode connected between a source terminal and a gate terminal of the switching element; a resistor connected between the driver and the gate terminal of the switching element; a series circuit connected in parallel with the resistor, and including a capacitor and a resistor; and a diode including an anode on a side of the gate terminal of the switching element and a cathode on a side of a second output terminal of the driver. The diode is connected in parallel with at least the capacitor out of the capacitor and the resistor connected in series.

Abstract: A protective device for protection of a semiconductor switch against overvoltages during a deactivation process. A compensation signal is provided at an input of a driver stage for a semiconductor switch to be deactivated if the voltage at the output of the semiconductor switch exceeds a specified threshold, and simultaneously a request to open the semiconductor switch is detected at an input of the driver stage for the semiconductor switch. The compensation signal is limited to a specified duration. On the basis of the compensation signal provided in the aforementioned manner, the driver stage for the semiconductor switch partly controls the semiconductor switch in order to prevent an excessively quick opening of the semiconductor switch.

Abstract: A power module includes a switching element, a temperature detection part which detects an operation temperature T of the switching element, a control electrode voltage control part which controls a control electrode voltage based on a threshold voltage Vth during an operation of the switching element which is calculated based on information including the operation temperature T of the switching element detected by the temperature detection part, and a switching speed control part which controls a switching speed of the switching element based on the operation temperature T of the switching element detected by the temperature detection part.