Abstract: Systems and methods are provided for implementing a phased array antenna having a boresight direction. A scan angle within a defined range of scan angles is selected for the phased array antenna such that the selected scan angle is different from a scan angle associated with the boresight direction. An antenna port impedance associated with each of a plurality of antenna elements comprising the phased array antenna varies with the scan angle of the phased array antenna. A plurality of amplifiers are each coupled to an antenna port of one of the plurality of antenna elements. Each of the plurality of amplifiers is configured such that a maximum value for a performance characteristic of the plurality of amplifiers is achieved when an impedance at the antenna port corresponds to the selected scan angle.

Abstract: To prevent an output of an intermediate potential by suppressing sneaking of a current from a signal line to a power line at the time of disconnection of a power supply. A control circuit which receives a power supply voltage from a power line L11 and outputs an output signal to a signal line L12 includes: a load R11 which is provided between the power line and the signal line; a first transistor P11 which is provided between the load and the signal line; a second transistor P12 which is provided between a well of the first transistor and the power line; and a gate control circuit 15 which connects a gate terminal of the first transistor and a gate terminal of the second transistor to the signal line and turns off the first transistor and the second transistor, at the time of disconnection of a power supply.

Abstract: An output driving circuit includes a pull-down driver and a voltage stabilizer. The pull-down driver includes first, second, and third transistors connected in series between a pad and a ground node. The voltage stabilizer generates a stabilization voltage based on a voltage of the pad and a power voltage, and outputs the stabilization voltage to a control terminal of the second transistor.

Abstract: Apparatuses and methods for setting operational parameters of a memory based on location are disclosed. The operational parameters may include operational parameters for an input/output circuit. For example, operational parameters may be for output driver circuit impedance, equalization for input receiver circuits, termination impedance, as well as others. Location information is provided to a memory device and used for setting the operational parameter. A nominal operational parameter setting may be offset based on the location information, thereby tailoring the operational parameter of the memory device according to location in some examples. The location information may be memory slot address for location based on memory module location. The location information may be related to a location of a memory device within a sub-system. The location information may be provided to unused terminals of a memory device, for example, unused data terminals in some examples.

Abstract: According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor.

Abstract: A switch drive circuit is provided with a surge detecting unit that detects a surge voltage produced in response to a change in a switching state of the switch; an adjusting unit that adjusts, based on the surge voltage detected by the surge detecting unit, a switching speed of the switch when changing the switching state of the switch; and a mask processing unit that prevents a voltage, detected by the surge voltage detecting unit in a period other than a period where the surge voltage is assumed to be produced in response to a change in the switching state of the switch, from being used by the adjusting unit for adjusting the switching speed.

Abstract: This disclosure relates to a discrete semiconductor device and associated method of manufacture, the discrete semiconductor device includes: a high voltage depletion mode device die; and a low voltage enhancement mode device die connected in cascode configuration with the high voltage depletion mode device die. The high voltage depletion mode device includes a gate, source and drain terminals arranged on a first surface thereof and the gate source and drain terminals are inverted with respect to the low voltage enhancement mode device die and the low voltage device is arranged adjacent to the high voltage device.

Abstract: A circuit device and a method for safely disconnecting a semiconductor switching element, in particular a MOSFET, are provided, wherein the semiconductor switching element comprises a gate terminal, a source terminal and a drain terminal, wherein, during operation of the semiconductor switching element, a current path between the drain terminal and the source terminal can be reversibly disconnected by the gate terminal, and the gate terminal comprises a gate voltage potential and the source terminal comprises a source voltage potential. A fuse unit is arranged between the gate terminal and the source terminal, which fuse unit is set up and designed, as a function of a potential difference between the gate voltage potential and the source voltage potential, so as to electrically connect the gate terminal to the source terminal after the current path is disconnected, so that the gate voltage potential and the source voltage potential are adapted.

Abstract: A controller comprising a driver interface referenced to a first reference potential, a drive circuit referenced to a second reference potential, and an inductive coupling. The driver interface comprises a first receiver configured to compare a portion of signals having a first polarity on the first terminal of the inductive coupling with a first threshold, and a second receiver configured to compare a portion of signals having a second polarity on the second terminal of the inductive coupling with a third threshold. The drive circuit comprises a first transmitter configured to drive current in a first direction in the second winding to transmit first signals, and a second transmitter configured to drive current in a second direction in the second winding to transmit second signals, the second direction opposite the first direction.

Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.

Abstract: A T-type DC circuit breaker includes a main branch, a first commutation switch, a second commutation switch, and a bypass branch. The first commutation switch and the second commutation switch are arranged at both ends of the main branch, respectively. The bypass branch is connected in parallel with the main branch. The main branch includes at least one half-controlled power electronic component. The bypass branch includes a bypass capacitor and a bypass diode connected in series. Each of the first commutation switch and the second commutation switch includes at least one fully-controlled power electronic component. The first commutation switch is connected in parallel with a first surge arrester, and the second commutation switch is connected in parallel with a second surge arrester. The grounded branch is arranged between the main branch and the second commutation switch and is grounded or connected to the negative terminal of the load.

Abstract: A circuit includes a protection circuit and a gate driver coupled to a power supply voltage node configured to have a power supply voltage level. The protection circuit generates a first signal having a first logical voltage level when the power supply voltage level is equal to or greater than a threshold voltage level, and having a second logical voltage level when the power supply voltage level is less than the threshold voltage level. The gate driver receives the first signal and a second signal, and, when the first signal has the first logical voltage level, outputs a third signal based on the second signal, and when the first signal has the second logical voltage level, outputs the third signal having a predetermined one of the first or second logical voltage levels.

Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

Abstract: A switching element 1 has a gate terminal connected to an output end Vout of a driving circuit 12 via a capacitor 11 and a resistor 13 connected in parallel. The switching element 1 has a source terminal connected to the driving circuit 12 via a capacitor 14 and a Zener diode 15 connected in parallel. The Zener diode 15 has an anode terminal connected to the source terminal of the switching element 1 and a cathode terminal connected to the driving circuit 12.

Abstract: A control circuit for driving a power switch in a switching power supply can include: a start-up transistor having a drain coupled to a drain of the power switch, and a source coupled to a drain voltage detecting circuit; a gate voltage detecting circuit configured to detect a gate voltage of the power switch, to compare the gate voltage against a first threshold voltage, and to change an on drive current and an off drive current in response thereto; and the drain voltage detecting circuit being configured to detect a drain voltage of the power switch, to compare the drain voltage against a second threshold voltage, and to change the on drive current and the off drive current in response thereto.

Abstract: In an overcurrent determining apparatus, a temperature obtainer obtains a temperature parameter indicative of a temperature of a switching element as a temperature measurement value. A determination voltage has a first voltage value when the temperature measurement value is a first temperature. A setter sets the determination voltage to a second voltage value upon determining that the temperature measurement value is a second temperature higher than the first temperature. The second voltage value is lower than the first voltage value and higher than a value of a Miller voltage of the switching element at the second temperature.

Abstract: Field-effect transistors and methods of manufacturing the same are described herein. An example field-effect transistor includes a substrate, a source above the substrate, a semiconductor region above the source, a drain above semiconductor region, a polarization layer disposed on the semiconductor region between the drain and an end of the semiconductor region, and a gate above the source adjacent the end of the semiconductor region.

Abstract: A semiconductor device includes a first terminal, a second terminal, a first transistor, and a switching circuitry. In the first transistor, an anode of a body diode is connected to the first terminal, and a cathode of the body diode is connected to the second terminal. The switching circuitry is connected between a gate and a source of the first transistor, and switches a connection state between the gate and the source of the first transistor.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: A power module includes: an embedding structure comprising an electrically insulating body; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a terminal of the embedding structure through one or more second electrically conductive paths embedded in the electrically insulating body.

Abstract: This invention provides a current self-checking regulation circuit based on voltage calibration including a bandgap reference unit, a self-calibration unit, a detection and regulation unit, current mirror units, and a current mirror control unit. The bandgap reference unit is configured to generate a voltage signal, the self-calibration unit is configured to respond to a digital signal of the detection and regulation unit and calibrate the voltage signal of the bandgap reference unit. The detection and regulation unit samples the reference current signal and a mirror current signal of the regulation group current mirror unit and generate a digital control signal according to the reference current signal. and the reference group current mirror unit responds to the digital control signal and outputs a regulated bias current signal meeting needs of the laser driver.

Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.

Abstract: In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.

Abstract: The present invention concerns a device and a method for controlling the switching from a conducting state to a non conducting state or from a non conducting state to a conducting state of a semiconductor power switch providing current to a load, the device receiving an input signal that is intended to drive the semiconductor power switch. The invention: —senses the derivative of the drain to source current going through the semiconductor power switch in order to obtain a voltage representative of the sensed derivative of drain to source current, —amplifies the voltage representative of the sensed derivative of drain to source current, —adds the amplified voltage representative of the derivative of the sensed drain to source current to the input signal during a given time period.

Abstract: A protective device for protection of a semiconductor switch against overvoltages during a deactivation process. A compensation signal is provided at an input of a driver stage for a semiconductor switch to be deactivated if the voltage at the output of the semiconductor switch exceeds a specified threshold, and simultaneously a request to open the semiconductor switch is detected at an input of the driver stage for the semiconductor switch. The compensation signal is limited to a specified duration. On the basis of the compensation signal provided in the aforementioned manner, the driver stage for the semiconductor switch partly controls the semiconductor switch in order to prevent an excessively quick opening of the semiconductor switch.

Abstract: A switching circuit includes; a switching element; a driver; a diode connected between a source terminal and a gate terminal of the switching element; a resistor connected between the driver and the gate terminal of the switching element; a series circuit connected in parallel with the resistor, and including a capacitor and a resistor; and a diode including an anode on a side of the gate terminal of the switching element and a cathode on a side of a second output terminal of the driver. The diode is connected in parallel with at least the capacitor out of the capacitor and the resistor connected in series.

Abstract: A power module includes a switching element, a temperature detection part which detects an operation temperature T of the switching element, a control electrode voltage control part which controls a control electrode voltage based on a threshold voltage Vth during an operation of the switching element which is calculated based on information including the operation temperature T of the switching element detected by the temperature detection part, and a switching speed control part which controls a switching speed of the switching element based on the operation temperature T of the switching element detected by the temperature detection part.

Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.

Abstract: A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die.

Abstract: The invention relates to a circuit arrangement (100) for the temperature-dependent actuation of a first switching element (S1), comprising an input terminal (EA) for accepting an input potential, an output terminal (AA) for transferring an output potential to a first control terminal (G1) of the first switching element (S1), and a temperature-dependent component (RT) which is connected between the input terminal (EA) and the output terminal (AA).

Abstract: A semiconductor device having a switch circuit and an integrated circuit. The switch circuit includes serially-connected first and second switching devices respectively on a power supply side and a ground side thereof, and first and second free-wheeling diodes connected respectively in parallel with the first and second switching devices. The integrated circuit performs switching of the second switching device, and including a detection circuit that detects a load current flowing through a load of the switch circuit, and a drive circuit that controls magnitude of a current flowing to the gate terminal of the second switching device, to thereby charge a gate capacitance of the second switching device according to a detection result of the detection circuit, when a received drive signal is at one logic level, and turns off the second switching device when the received drive signal is at another logic level.

Abstract: A transistor, e.g., field effect transistor FET, ringing adjustment circuit and method comprising the measuring of a voltage from a transistor (e.g., a node of a FET) during the transistor turning on and turning off, determining the voltage oscillation in the measured voltage by performing a derivative function on the measured voltage and detecting a switch in a voltage change rate from positive to negative or negative to positive, and comparing the voltage change rate after the detected switch to adjust drive current applied to the transistor to optimize efficiency while minimizing voltage oscillation and ringing.

Abstract: A drive circuit drives a switch that has first and second terminals and a control terminal. The drive circuit includes a discharge path, a capacitor, an AC suppressor and a DC voltage generator. The discharge path connects the control terminal and the second terminal. The capacitor has a high-potential terminal connected to the second terminal side and a low-potential terminal connected to the control terminal side. The AC suppressor has a first end connected to a part of the discharge path between the high-potential terminal the second terminal. The DC voltage generator has a connection terminal connected to a second end of the AC suppressor. The DC voltage generator regulates electric current flowing between the connection terminal and the AC suppressor so as to keep the potential of the part of the discharge path between the high-potential terminal and the second terminal higher than the potential of the low-potential terminal.

Abstract: A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.

Abstract: A system for monitoring a junction temperature of a semiconductor device includes a sensing resistor electrically coupled to a source terminal of the semiconductor device in a gate loop of the semiconductor device. The system includes a detection circuit electrically coupled to the gate loop of the semiconductor device and configured to measure a voltage difference across the sensing resistor. The system also includes an electronic control unit electrically coupled to the gate loop and the detection circuit. The electronic control unit is configured to determine a first gate current peak during a switching process of the semiconductor device, wherein the first gate current peak is determined based on the voltage detected by the detection circuit. The electronic control unit is configured to determine the junction temperature based on the first gate current peak.

Abstract: This disclosure includes systems, methods, and techniques for controlling delivery of power to a load. For example, a circuit includes a first switching device and a second switching device. The circuit is configured to activate, in response to a source voltage of a semiconductor device being lower than a first voltage, the first switching device in order to cause the circuit to deliver a first electrical signal to the semiconductor device, where the first electrical signal includes the first voltage and deactivate the first switching device in response to the source voltage of the semiconductor device not being lower than the first voltage. Additionally, the circuit is configured to activate, in response to the source voltage of the semiconductor device not being lower than the first voltage, the second switching device to cause the circuit to deliver a second electrical signal to the semiconductor device.

Abstract: The present disclosure provides an electrostatic protection circuit, an array substrate, and a display device. The electrostatic protection circuit includes: a first voltage line, to which a high level voltage is applied; a second voltage line, to which a low level voltage is applied; and a switch assembly, including a plurality of first switch units and a plurality of second switch units arranged along a straight line and sharing an active layer. The first switch units are respectively coupled between the signal lines and the first voltage line, and are turned on in response to negative static electricity on the signal lines. The second switch units are respectively coupled between the signal lines and the second voltage line, and are turned on in response to positive static electricity on the signal lines. The signal lines are arranged in a peripheral region of the array substrate.

Abstract: A waveform conversion circuit for converting a control signal of a control node ranging from a high voltage level to a low voltage level of a reference node into a driving signal of a first node is provided. The waveform conversion circuit includes a first resistor, a unidirectional conducting device, and a voltage clamp unit. The first resistor is coupled between the control node and the first node. The unidirectional conducting device unidirectionally discharges the first node to the control node. The voltage clamp unit is coupled between the first node and the reference node and is configured to clamp a driving signal.

Abstract: A power module includes: an embedding structure comprising an electrically insulating body, first terminals at a first side of the electrically insulating body, and second terminals at a second side of the electrically insulating body opposite the first side; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip contacting the first set of terminals at the first side of the electrically insulating body and comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a corresponding one of the second terminals through one or more second electrically conductive paths embedded in the electrically insulating body.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.

Abstract: A drive circuit includes: a signal generation circuit; a comparator; a comparator; and a short circuit determination unit. The signal generation circuit is configured to generate, as an output signal, a differential amplification signal of a voltage detection signal indicating a gate voltage of a semiconductor element and a delay signal of the voltage detection signal. The comparator is configured to compare a value of the differential amplification signal with a first reference voltage value. The comparator is configured to compare a voltage value indicating a gate current with a second reference voltage value. The short circuit determination unit is configured to determine whether or not the semiconductor element is in a short-circuited state, based on a result of comparison by each of the comparators, and generate a determination signal indicating a determination result.

Abstract: Circuits and methods for limiting excessive current in circuits (such as step-up DC-to-DC converter circuits) in which very low ohmic FETs (VLOFETs) are used in circuit pathways that are subjected to startup in-rush current. Embodiments include a current mirror driver circuit that can be coupled to the gates of a VLOFET to form a current mirror that limits current flow through the VLOFET. The current mirror driver circuit provides for pulsed operation so that a coupled VLOFET still toggles between an OFF state and a current limited mode, particularly during a startup period. By using the current mirror driver circuit in conjunction with VLOFETs in circuit pathways that are subjected to startup in-rush current, in-rush current can be regulated to an acceptable level. Notably, no additional impedances are required in circuit pathways that are subjected to startup in-rush current to limit in-rush current, thus avoiding loss of efficiency.

Abstract: There is provided a drive circuit for turning on/off a power element which controls a main current flow between a first main electrode and a second main electrode in response to a drive signal applied to a control electrode. The drive circuit includes first and second semiconductor switch elements which are connected in series and interposed between a power supply terminal and a ground terminal, a series connection point thereof being connected to the control electrode, third and fourth semiconductor switch elements which are connected in series and interposed between the power supply terminal and the ground terminal, a series connection point thereof being connected to the second main electrode, and a control circuit which controls turn-on/off of the power element by turning on/off the first to fourth semiconductor switch elements. The first semiconductor switch element has a larger on-resistance than the second to fourth semiconductor switch elements.

Abstract: A semiconductor device including: an output element including a power supply side electrode region and an output side electrode region and configured to flow main current between the power supply side electrode region and the output side electrode region; an internal circuit including a sensor circuit configured to detect an abnormality; and a package in which the output element and the internal circuit are built, the package including a primary lead terminal and a secondary lead terminal, wherein the primary lead terminal electrically draws out an intermediate node in wiring of a primary detection circuit constituting the sensor circuit to an outside, the secondary lead terminal electrically draws out a terminal of a secondary detection circuit separable from the primary detection circuit to the outside, and depending on a connection state between the primary and secondary lead terminals, a reference value for detecting the abnormality can be changed.

Abstract: An electronic power device formed by a plurality of FETs formed on a circuit board formed of a plurality of layers, the plurality of transistors being formed on a first surface of the circuit board, the plurality of layers including a plurality of gate drive layers, a plurality of gate return layers, and a plurality of power layers. A gate drive circuit is formed on a second surface of the circuit board, the second surface being opposite the first surface, the gate drive circuit being connected to the gate and source of each of the plurality of transistors through the plurality of gate drive layers and the plurality of gate return layers. A voltage supply is connected to the drain of each of the plurality of transistors, the connections of the voltage supply to each of the plurality of transistors being interleaved through the plurality of power layers.

Abstract: In accordance with an embodiment, a method includes monitoring a first voltage across a buffer capacitor; activating a first current path between a power supply node and the buffer capacitor when the monitored first voltage is below a first threshold voltage, activating a second current path between the power supply node and the buffer capacitor when the monitored first voltage is below a second threshold voltage, and transferring power from the buffer capacitor to a driver circuit coupled across the buffer capacitor.

Abstract: Disclosed are film packages, chip-on-film packages, and package modules. The film package including a film substrate having a first surface and a second surface facing each other, a plurality of output patterns on the film substrate and each including a first chip pad and an output pads electrically connected to the first chip pad and spaced apart in a first direction from the first chip pad, and a plurality of input patterns on the film substrate and each including a second chip pad adjacent to the first chip pad corresponding thereto and an input pad electrically connected to the second chip pad and spaced apart in the first direction from the second chip pad may be provided. At least portions of the output patterns overlap the input patterns across the film substrate.

Abstract: A gate driver of array (GOA) circuit and a display device are disclosed. An n-th sub-circuit in the GOA circuit includes a control module, an output module, a pull-up supplement module, and a leakage switch. The control module is electrically connected to a positive scan control terminal, a negative scan control terminal, an (n?2)th scan terminal, an (n+2)th scan terminal, an (n+1)th clock terminal, an (n?1)th clock terminal, a high voltage terminal, and a low voltage terminal. The output module is electrically connected to the high voltage terminal, the low voltage terminal, an n-th clock terminal, an n-th scan terminal, and a controllable terminal. The pull-up supplement module includes a supplement switch that is electrically connected to the high voltage terminal, the control module, and the output module. The leakage switch is electrically connected to the control module, the output module, the supplement switch, and the low voltage terminal.

Abstract: Systems and methods according to one or more embodiments are provided for improved reliability and efficiency of high side power stage output drivers used in switching amplifiers. In one example, a system includes a power device structure comprising an nwell structure formed within a semiconductor p substrate and a pwell structure formed within the nwell structure. The system further includes one or more NMOS electronic power devices formed on the pwell structure and a pwell guardring formed on the pwell structure configured to surround the one or more NMOS electronic power devices. The system further includes an nwell guardring formed on the nwell structure configured to surround the pwell structure and a p+ guardring formed on the nwell structure configured to surround the nwell guardring.