Abstract: An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.

Abstract: The present disclosure provides a gate driver on array (GOA) driving circuit and a liquid crystal display (LCD) device. The GOA driving circuit comprises a plurality of cascaded GOA units. An Nth cascaded GOA unit outputs a gate driving signal to an Nth horizontal scanning line Gn of an display area. The Nth cascaded GOA unit comprises a pull-up assembly, a pull-up control assembly, a pull-down maintaining assembly, a download assembly and a bootstrap capacitor assembly.

Abstract: A bicycle electronic system comprising a battery unit, at least one operating unit and a power supply and communication bus, each of said units being connected to said bus is provided. The system comprises first means or controller for switching-off/(re)switching-on able to be activated/deactivated by a user and second means or controller for switching-off/(re)switching-on suitable for disconnecting/connecting said battery unit from/to said power supply and communication bus in response to the activation/deactivation of said first means or controller for switching-off/(re)switching-on. A battery unit and a method for switching-off/(re)switching-on a bicycle electronic system are also described.

Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch configured to be selectively conductive according to one or more input signals, a high side power switch configured to be selectively conductive according to the one or more input signals, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a capacitor, and a logic circuit, wherein the capacitor is configured to capacitively couple a signal based on the input signals to the logic circuit, and the logic circuit is configured to control the conductivity of the high sigh power switch based on the capacitively coupled signal.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: Disclosed herein is a light emitting element driving circuit including: a capacitive element; a current limiting section limiting a charging current for the capacitive element; a first constant current source stabilizing a discharging current supplied from the capacitive element to a light emitting element; and a switch controlling ON and OFF in supplying the discharging current to the light emitting element. The capacitive element is charged with electricity from the power source circuit in the preceding stage through the current limiting section. Also, the electric charges in the capacitive element are discharged in the form of a given discharging current for the discharging time period, and the light emitting element emits light in accordance with the given discharging current. In this case, the charging current for the capacitive element is limited by the current limiting section in such a way that the current value thereof becomes small.

Abstract: A switching circuit for controlling supply of electrical power from a power pole input to a power pole output.

Abstract: A multi-channel dual-mode digital control LED driving circuit and an LED lamp. The driving circuit comprises a current sampling module (10), a comparison and detection module (30), a digital control module (40) and a constant current control module (20). By means of feeding back an adjustment current for the load (70) by the digital control module (40), and feeding back and adjusting a current of the load (70) in real time by the constant current control module (20), the driving circuit adjusts the load (70) in real time, so that dual-mode cooperation working is realized, and thus a response speed is greatly improved, the accuracy of an output voltage and the current of the load (70) is improved, and at the same time, the system stability is enhanced and wide universality is achieved.

Abstract: A gate charge and discharge adjustment regulating circuit for a gate control device belongs to the power electronics technology field. The switch control signal is connected to the control terminals of the four analog switches. The gate control signal is loaded on the gate of the correct field effect transistor under the action of the four analog switches to control the switching-on degree so as to achieve the purpose of adjusting the gate driving signal current, that is, regulating the gate charge and discharge currents of the gate control device to realize the change of the switching characteristics and conduction characteristics. The switch control signal is connected to the input terminal of the gate driving module to control the gate driving module to generate the gate driving signal.

Abstract: A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

Abstract: A gate driver includes a gate driving main circuit and a power sequence control circuit. The gate driving main circuit disposed between an operating voltage and ground is coupled to a first gate voltage and a second gate voltage. The operating voltage is higher than ground and first gate voltage is higher than second gate voltage. The power sequence control circuit includes first-type transistors, a second-type transistor, a transistor and a judging circuit. The first-type transistors are coupled in series between first gate voltage and a first node and their gates are coupled to a second node. The second-type transistor is coupled between first node and second gate voltage and its gate is coupled to second node. The transistor is coupled between first gate voltage and gate driving main circuit and its gate is coupled to first node. The judging circuit generates an output signal to second node.

Abstract: A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.

Abstract: A semiconductor device, including a main transistor configured to supply power from a power source to a load, and a current limiting device including a control transistor. The current limiting device is configured to detect that the current flowing from the main transistor is an overcurrent, and to limit the current upon determining that the current is equal to or greater than a current limit value, and an operating voltage of the control transistor is equal to or greater than a current limiting activation voltage. The current limit value is a threshold for determining whether the current is greater than an operating current of the main transistor for the load to operate in a steady state. The current limiting activation voltage is a sum of a correction voltage and a predetermined threshold voltage at the gate of the control transistor when the current rises to the current limit value.

Abstract: In a switching converter having an inductive load, a current may flow through the body diode of a transistor even though the gate of the transistor is being controlled to keep the transistor off. Then when the other transistor of the switch leg is turned on, a reverse recovery current flows in the reverse direction through the body diode. To reduce switching losses associated with such current flows, a gate driver integrated circuit detects when current flow through the body diode rises above a threshold current. The gate driver integrated circuit then controls the transistor to turn on. Then when the other transistor of the switch leg is made to turn on, the gate driver first turns the transistor off. When the gate-to-source voltage of the turning off transistor drops below a threshold voltage, then the gate driver integrated circuit allows and controls the other transistor to turn on.

Abstract: A circuit model of a Zener diode includes a forward bias diode, a reverse bias diode, a first resistor, a second resistor, and a voltage source. The forward bias diode and the first resistor are connected in series and form a first branch disposed between a positive terminal and a negative terminal. The voltage source, the reverse bias diode and the second resistor are connected in series and form a second branch, which is disposed between the positive terminal and the negative terminal and connected in parallel with the first branch. The circuit model can specifically describe the current-voltage characteristics of the Zener diode and significantly improve the accuracy of the circuit simulation.

Abstract: A vehicle powertrain includes an IGBT that conducts current between a supply and load. The vehicle powertrain also includes a controller that applies voltage to a gate of the IGBT at a first level for a first duration that depends on a capacitance of the gate, and increases the voltage over a second duration based on a rate of change of the current falling below a threshold defined by a supply voltage for the load.

Abstract: An amplifier feeds a current corresponding to a difference between a gradation voltage corresponding to a luminance level in a video signal and an amplified gradation voltage obtained by amplifying such a gradation voltage through an output current line in a current mirror circuit, and provides a voltage on the output current line to an output part via a driving line. The output part generates the amplified gradation voltage on the output line by feeding a current according to a voltage on the driving line through the output line.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: A circuit arrangement for controlling a transistor with an insulated gate, a gate driver for generating a driver signal, and a capacitor parallel to the gate-source path of the transistor, wherein the gate driver is designed for generating a driver signal greater than or equal to zero volts, an inductor is provided for forming a resonant circuit with the capacitor, and a switching element is provided in the resonant circuit, which is designed for interrupting the resonant circuit after recharging the capacitor. The part of the circuit arrangement downstream of the gate driver is designed for exclusive voltage supply using the driver signal of the gate driver, and the switching element is formed by an additional transistor, a first freewheeling diode is arranged parallel to the switching element, and the inductor of the resonant circuit is arranged between the additional transistor and the gate of the transistor.

Abstract: A semiconductor apparatus including a substrate having a substrate major surface, a dielectric material on the substrate major surface and having a second major surface distanced from the substrate major surface, and a plurality of fins extending from the substrate major surface through the dielectric material where the plurality of fins includes a first subset of fins and a second subset of fins, the first subset of fins located closer to a center of the plurality of fins than the second subset of fins, and an amount of heat generated during operation of the semiconductor device by each fin of the first subset of fins is less than an amount of heat generated by each fin of the second subset of fins during operation of the semiconductor device.

Abstract: A power semiconductor device driving circuit has a capacitor whose one end is connected with a first or a second main electrode of a power semiconductor device, a first switch for charging the capacitor and a control electrode of the power semiconductor device with electric charges, and a second switch for discharging electric charges; in the case where when the first switch turns on, the control electrode and the capacitor are charged with electric charges through different resistors, electric charges are discharged from the control electrode and the capacitor through one and the same resistor when the second switch turns on; in the case where when the first switch turns on, the control electrode and the capacitor are charged with electric charges through one and the same resistor, electric charges are discharged from the control electrode and the capacitor through different resistors when the second switch turns on.

Abstract: A nanosecond pulser may include a plurality of switch modules, a transformer, and an output. Each of the plurality of switch modules may include one or more solid state switches. The transformer may include a core, at least one primary winding wound around at least a portion of the core, each of the plurality of switch modules may be coupled with the primary windings, and a plurality of secondary windings wound at least partially around a portion of the core. The output may output electrical pulses having a peak voltage greater than about 1 kilovolt and having a pulse width of less than about 1000 nanoseconds. The output may output electrical pulses having a peak voltage greater than about 5 kilovolts, a peak power greater than about 100 kilowatts, a pulse width between 10 nanoseconds and 1000 nanoseconds, a rise time less than about 50 nanoseconds, or some combination thereof.

Abstract: An apparatus (10) is provided for controlling an actuatable restraint (14, 16) in a vehicle (12). An sensor (24) is mounted in the vehicle (12) and outputs an electrical signal having a characteristic indicative of a vehicle event. A discrimination circuit (42) is coupled to the sensor (24) and determines if a predetermined event occurred. A safing circuit (50) is copied to the sensor (24) signal and sequestered from the discrimination circuit (42) for determining if the predetermined event occurred. An actuation device is actuates the restraint when both the discrimination circuit (42) and the safing circuit (50) determine the predetermined event occurred.

Abstract: A commutation cell is configured for limiting switching overvoltage. The commutation cell includes a power electronic switch having a parasitic emitter inductance through which a voltage is generated upon turning off of the power electronic switch. The commutation cell also includes a dynamically controlled compensation circuit connected to the parasitic emitter inductance. The compensation circuit applies a controllable portion of the voltage generated through the parasitic emitter inductance at turn-off of the power electronic switch to control the voltage generated through the parasitic emitter inductance. A power converter includes a pair of commutation cells and a compensation circuit of the commutation cell.

Abstract: A circuit for controlling a first field-effect transistor of a power converter, intended for a converter including at least one first and one second transistor connected in series between two terminals for applying a first voltage, the circuit including a circuit for detecting the opening of the second transistor.

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract: A jitter control circuit within a chip comprises an adaptive PDN, a current generator and a jitter generator. The adaptive PDN is capable of being controlled/modulated to provide difference impedances. The current generator is coupled to the adaptive PDN, and is arranged for receiving a supply voltage provided by the adaptive PDN and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN, and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN.

Abstract: A motor control apparatus includes an inverter, a driver, a negative voltage circuit, a voltage dividing circuit, and a detection unit. The inverter includes an upper-arm switching element and a lower-arm switching element to supply a voltage of a node between the upper-arm switching element and the lower-arm switching element to a motor as a phase voltage. The driver applies a first voltage or a second voltage to the upper-arm switching element to control and turn the upper-arm switching element on and off. The negative voltage circuit supplies a voltage lower than the voltage of the node to the driver as the second voltage. The voltage dividing circuit performs voltage division between the negative voltage circuit and a negative power supply. The detection unit outputs a signal based on a voltage resulting from the voltage division by the voltage dividing circuit.

Abstract: A power converter includes a PCB and a semiconductor die coupled to the PCB. The semiconductor die includes first through fourth switching devices. The power converter further includes a first energy storage element electrically connected to the first and second switching devices and a second energy storage element electrically connected to the third and fourth switching devices. The first energy storage element is mounted over the first and second switching devices and the second energy storage element is mounted over the third and fourth switching devices.

Abstract: Provided is a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M?2th high frequency clock signals (CK(M), CK(M?2)), a stage transfer signal (ST(n?2)) generated by the n?2th stage GOA unit circuit, a charging scan signal (CG(n?2)) generated by the n?2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n?2)) generated by the n?2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).

Abstract: Provided is a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M?2th high frequency clock signals (CK(M), CK(M?2)), a stage transfer signal (ST(n?2)) generated by the n?2th stage GOA unit circuit, a charging scan signal (CG(n?2)) generated by the n?2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n?2)) generated by the n?2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).

Abstract: Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal.

Abstract: Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.

Abstract: A power converter with an isolated topology may include a power transistor, a sense transistor, and a read-out circuit. The sense transistor may be arranged in a current mirror configuration with the power transistor such that the gate terminal of the sense transistor is coupled to the gate terminal of the power transistor and the first drain/source terminal of the sense transistor is coupled to the first drain/source terminal of the power transistor. The read-out circuit may be coupled to the second drain/source terminal of the power transistor and the second drain source/terminal of the sense transistor. The read-out circuit may be arranged to cause a voltage at the second drain/source terminal of the sense transistor to be substantially the same as a voltage at the second drain/source terminal of the power transistor.

Abstract: A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first PMOS transistor. The level shift circuit provides an output signal, wherein the output signal has a first operation voltage and a second operation voltage. When the output signal received by the negative voltage generator is the first operation voltage, the negative voltage generator outputs the first operation voltage. When the output signal received by the negative voltage generator is the second operation voltage, the negative voltage generator generates and outputs a third operation voltage, and the third operation voltage is lower than the second operation voltage. A control terminal of the first PMOS transistor is coupled to an output terminal of the negative voltage generator. An output terminal of the first PMOS transistor provides a driving voltage.

Abstract: A source driver circuit can include: (i) a control transistor having a control terminal and first and second power terminals, where the control transistor is coupled between a power terminal of a main switching transistor and ground; (ii) a power supply capacitor coupled between the control terminal of the main switching transistor and ground, where the power supply capacitor is configured to receive a bias voltage that is substantially constant; (iii) a freewheeling diode having a cathode coupled to a control terminal of the main switching transistor, and an anode coupled to the second power terminal of the main switching transistor; and (iv) the control transistor being controllable to be periodically turned on and off to control the main switching transistor to correspondingly follow on and off states of the control transistor.

Abstract: The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a pair of commutation cells. Each commutation cell includes a power electronic switch and a gate driver connected to a gate of the power electronic switch. A reference of the gate driver of a first commutation cell is connected to a ground of the power converter while a reference of the gate driver of a second commutation cell is connected to a collector of the power electronic switch of the first commutation cell. The gate driver of the second commutation cell has no negative voltage power input, either through using a single voltage power supply or by connecting a negative voltage connection of the dual voltage power supply to ground.

Abstract: The present invention provides a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M?2th high frequency clock signals (CK(M), CK(M?2)), a stage transfer signal (ST(n?2)) generated by the n?2th stage GOA unit circuit, a charging scan signal (CG(n?2)) generated by the n?2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n?2)) generated by the n?2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).

Abstract: The present disclosure relates to a compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver. The compensation circuit includes a circuit path sampling a first portion of a voltage induced across an inductance of the power electronic switch at turn-on. Another circuit path samples a second portion of the voltage induced across the inductance of the power electronic switch at turn-off. The compensation circuit further includes a gate driver reference connection configured to respectively supply the sampled portions of the voltage during turn-on and turn-off of the power electronic switch. A compensation circuit controlling a first power electronic switch in parallel with a second power electronic switch, a commutation cell and a power converter having a pair of parallel legs, in which each power electronic switch is provided with the compensation circuit, are also disclosed.

Abstract: Disclosed herein is a power electronic device assembly for preventing parasitic switching-on of a feeder circuit breaker. The assembly includes a logic circuit, a power switch with an input and a reference leg, and a driver circuit which drives the power switch. The driver circuit includes a drive unit and a short circuit having a safety function. When the input of the power switch is not operated, the power switch is short-circuited by the reference leg so that the potential of the input decreases below a switching-on threshold. An additional wire connection device is disposed between the driver circuit and the power switch and configured such that when no or excessively small amount of supply voltage is applied, the input of the power switch is short-circuited or is coupled to a safety potential at which discharge is secured, whereby discharge of parasitic charge current is secured.

Abstract: A method and system for generating a reference voltage are disclosed. The reference voltage is generated by generating a voltage VRIGHT using a first transistor and generating a voltage VBIAS using a second transistor. The gates of the two transistors are connected to a common node VREF, but the loads of the transistors have different resistances. At least one differential pair is used to detect a difference between voltages VRIGHT and VBIAS. VREF is forced to a value at which the source-drain currents in each of the transistors is equal. The transistors sued are NMOS transistors.

Abstract: A semiconductor device of the present invention includes a transistor having a drain and a source, a voltage being applied between the drain and the source from a high-voltage power supply, a drive device that generates a source voltage and a gate voltage for the transistor from a voltage of a low-voltage power supply lower than that of the high-voltage power supply, and a voltage dividing circuit connected to the low-voltage power supply, wherein when the source voltage is lower than a certain value, an output voltage from the voltage dividing circuit is applied to the source.

Abstract: A GOA circuit based on LTPS semiconductor TFT includes a plurality of GOA units which are cascade connected, in which an Nth GOA unit includes a pull-up control part, a pull-up part, a first pull-down part and a pull-down holding part. The pull-down holding part utilizes a high/low voltage reverse design and includes first, second and third DC constant low voltage levels, which are sequentially abated, and a DC constant high voltage level so that the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit and particularly the bad function due to the electric leakage issue can be solved. Also, the existing issue that the second node voltage level of the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the functioning period can be solved.

Abstract: A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit.

Abstract: A drive device includes an off-side circuit controlling a gate current of a power switching element to perform an off operation. The off-side circuit includes: a main MOS transistor; a sense MOS transistor defining a drain current of the main MOS transistor; and a sense current control circuit controlling a drain current of the sense MOS transistor to be constant. The sense current control circuit includes: a reference power supply; a reference resistor; and an operational amplifier generating an output at the gate of the sense MOS transistor so that a potential between the reference resistor and the sense MOS transistor approaches the reference potential. The sense current control circuit flows a current, determined by a resistance value of the reference resistor and the reference potential, as the drain current of the sense MOS transistor.

Abstract: A dimming control circuit for adjusting brightness of a light-emitting component is provided. The dimming control circuit includes a driving transistor, an amplifier and a control circuit. The driving transistor is coupled to the light-emitting component The amplifier includes a first input terminal and an output terminal. The output terminal is coupled to a gate of the driving transistor. The control circuit is coupled to the amplifier. The control circuit generates a second analog signal to the first input terminal of the amplifier according to a first analog signal. A slew rate of the second analog signal below the slew rate of the first analog signal and the amplifier controls the driving transistor to adjust a driving current flowing through the light-emitting component according to the second analog signal.

Abstract: A power supply and a gate driver includes a power switching element to control current, a control circuit to output a control signal for opening or closing of the power switching element, and a gate drive circuit to open or close the power switching element in accordance with the control signal. The gate drive circuit includes a first inductive circuit connected to a supply voltage source, and a second inductive circuit connected to an input stage of the power switching element, and transfers electrical energy stored in the input stage of the power switching element, using the first and second inductive circuits. Accordingly, electrical energy supplied to the input stage of the power switching element during an ON state of the power switching element is again recovered during an OFF state of the power switching element.

Abstract: A gate driver circuit for prevention of an arm short may include a drive controller configured to a gate drive signal, a drive signal transfer portion configured to amplify the gate drive signal and output the amplified gate drive signal, a variable resistance portion configured to change a time constant of the amplified gate drive signal using an internal resistance and output the amplified gate drive signal having the changed time constant to a gate of a semiconductor device, and a resistance controller configured to compare a first DESAT pin voltage of the drive controller with a first predetermined reference value and control the internal resistance of the variable resistance portion using the comparison result with the first predetermined reference value to perform a first driver circuit protection.

Abstract: The present invention provides an array substrate, a driving method and a display device. The array substrate comprises a plurality of gate lines. A first gate line of the two adjacent gate lines is coupled to a first switch unit and a second gate line is coupled to a second switch unit. The first switch unit and the second switch unit are coupled to a control line, and are coupled to a gate drive output channel. The second switch unit is turned off when the first switch unit is turned on under control of the control line, and the first switch unit is turned off when the second switch is turned on under control of the control line. According to the present invention, it is able to effectively reduce the number of the gate drive ICs and thereby to reduce the cost.

Abstract: In described examples, a first isolation element electrically isolates a first circuit from a second circuit and passes AC signals between the first circuit and the second circuit. A second isolation element electrically isolates the first circuit from the second circuit and passes AC signals between the first circuit and the second circuit. A ground of the second circuit electrically floats relative to a ground of the first circuit, so that a digital signal is able to pass from the second circuit through a third isolation element to the first circuit. A supply voltage generation device converts AC signals from the first isolation element and the second isolation element into at least one DC voltage to power the second circuit.