Abstract: In described examples, a first isolation element electrically isolates a first circuit from a second circuit and passes AC signals between the first circuit and the second circuit. A second isolation element electrically isolates the first circuit from the second circuit and passes AC signals between the first circuit and the second circuit. A ground of the second circuit electrically floats relative to a ground of the first circuit, so that a digital signal is able to pass from the second circuit through a third isolation element to the first circuit. A supply voltage generation device converts AC signals from the first isolation element and the second isolation element into at least one DC voltage to power the second circuit.

Abstract: A switching controller having an over voltage protection circuit is disclosed. The over voltage protection circuit detects whether the output voltage is higher than an over voltage threshold and turns on the rectifier when the output voltage is higher than an over voltage threshold. The over voltage protection circuit detects whether a current flowing through a rectifier is lower than a negative current limit and further turns off the rectifier for a time period when the current flowing through the rectifier is lower than the negative current limit. The off time period varies inversely with the input voltage.

Abstract: A current control circuit includes a first drive switching device, a gate power source, a control switching device, a first resistor, an operational amplifier, and a switching circuit. The operational amplifier includes: an output terminal connected to the control switching device; a non-inverting input terminal; and an inverting input terminal configured to receive a reference potential. The switching circuit is configured to: input a value based on a potential difference between both ends of the first resistor to the non-inverting input terminal when a current flowing through the first drive switching device is equal to or smaller than a threshold level; and input a value based on a potential on a current pathway between the control switching device and the first drive switching device to the non-inverting input terminal when the current flowing through the first drive switching device is greater than the threshold level.

Abstract: A semiconductor device according to an embodiments controls a gate voltage to be applied to a gate electrode of a junction field effect transistor including a source electrode, a drain electrode, and the gate electrode, the transistor having a first threshold voltage at which the transistor is turned on, and a second threshold at which conductivity modulation occurs in the transistor so as to make the gate voltage equal to or higher than the second threshold voltage when a forward current in a direction from the drain electrode toward the source electrode flows, and so as to make the time variation in gate voltage have a point from which the rate of the time variation starts decreasing at a voltage between the second threshold voltage and the first threshold voltage when the forward current to be shut down.

Abstract: Provided is a BrushLess Direct Current (BLDC) motor system including a motor driving circuit configured to control a pulse-width-modulation (PWM) inverter in a first operation mode or a second operation mode according to a control signal, and output a switching signal according to each operation mode, the PWM inverter configured to receive the switching signal to output first three-phase voltages having a first frequency in the first operation mode, and output second three-phase voltages having a second frequency in the second operation mode, a sensorless BLDC motor configured not to operate in the first operation mode by operating based on three-phase voltages having a frequency in a different band from the first frequency, and operate in the second mode by operating based on three-phase voltages having a frequency in an identical band to the second frequency, and a parameter detecting circuit configured to calculate parameter information on the sensorless BLDC motor in the first operation mode by using sens

Abstract: A scan driving circuit includes a pull controlling module for generating scan level signal based on transferring signals from the previous one stage and from the previous two stage, a pull-up module, a pull-down module, a pull-down holding module, a transferring module, a first bootstrap capacitor, a constant low voltage level source, and a second bootstrap capacitor for pulling up the scan level signal through the transferring signal from the previous one stage. The present invention upgrades a reliability of the scan driving circuit.

Abstract: A device for measuring a periodic signal is disclosed. The device includes a light source for generating an optical input signal directed at an object being measured from an electrical input signal generated by a driver device on the basis of a first clock pulse, an optical receiver for detecting and converting the signal received, a central control and measuring device is designed to generate the first clock pulse for the driver device and to receive and process the electrical measuring signal, and a voltage-supply apparatus for supplying the driver device. The central control and measuring device are preferably designed to generate a second clock pulse for the voltage-supply apparatus and to filter the electrical measuring signal on the basis of the first and/or second clock pulse. The frequency of the second clock pulse is an even multiple of the frequency of the first clock pulse.

Abstract: A drive control device for two semiconductor elements having a transistor structure and a diode structure with a common energization electrode includes: a current detection device outputting a current detection signal of the semiconductor elements; and a first control device outputting a gate drive signal from when a first time period has elapsed from a starting time to when a second time period has elapsed from the starting time, at which an off-command signal is input after it is determined that a current flows through the semiconductor elements in a forward direction of the diode structure during a time period for which an on-command signal is input to the semiconductor elements. The first and the second time periods are preliminary set not to generate an arm short-circuit between two semiconductor elements.

Abstract: A voltage converter having a bootstrap refresh control circuit and a method for controlling the voltage converter. The bootstrap refresh control circuit monitors a bootstrap voltage across a bootstrap capacitor and provides a high side driving signal to a high side switch of the voltage converter. The bootstrap refresh control circuit also controls the charging of the bootstrap capacitor through decreasing the output voltage of the voltage converter once the bootstrap voltage is dropped to be smaller than a bootstrap refresh threshold. When the output voltage of the voltage converter is decreased enough, the bootstrap refresh control circuit switches the high side switch and the low side switch on and off to refresh the bootstrap voltage.

Abstract: A drive circuit includes: a constant current circuit configured to supply a constant current to a gate of the voltage-controlled device, and to turn on the voltage-controlled device; a discharge circuit configured to supply a discharge current between the gate and an emitter of the voltage-controlled device, and to turn off the voltage-controlled device; a switch circuit configured to operate one of the constant current circuit or the discharge circuit depending on a drive signal, and to turn on or turn off the voltage-controlled device; a current instruction value generation circuit configured to generate and output at least a current instruction value that sets an output current from the constant current circuit; and a current control circuit configured to control the output current from the constant current circuit based on the current instruction value generated by the current instruction value generation circuit.

Abstract: The present document relates to DC/DC converters with a modular structure for providing different levels of output currents. A power converter configured to convert electrical power at an input voltage into electrical power at an output voltage is described. The power converter comprises inverter stages with half bridges comprising a high side switches and low side switches which are arranged in series between the input voltage and a reference voltage; and with high side drivers for providing drive signals for the high side switches, subject to a high side control signals at a drive voltage level. In addition, the power converter comprises a level shifting unit configured to convert a high side control signal at a logic voltage level into the high side control signal at the drive voltage level for driving the high side switches.

Abstract: Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer.

Abstract: The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400) and a pull-down holding part (500); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third DC constant low voltage levels (VSS1, VSS2, VSS3) which are sequentially abated and a DC constant high voltage level (H), the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the functioning period can be solved to effectively maintain the first node (Q(N)) a

Abstract: The system comprises a Digital Signal Processing module, a Power Supply Unit and an audio amplifier. In the Digital Signal Processing module, the level of the digital audio signal is detected for adjusting the rail voltage in the amplifier. The digital audio signal is delayed by the Digital Signal Processing module prior to transforming and feeding it into the audio amplifier for amplification in order to stabilize the rail voltage after adjustment of the rail voltage to an increased level. Further in order to decrease the power consumption, especially in battery driven amplifiers, an adjustment of the rail voltage to a reduced level is delayed by a second predetermined time length (S_Hold) of 1 to 5 seconds as this reduces the number of adjustments of the rail voltage.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: Aspects of the disclosure provide a circuit for driving a power switch. The circuit includes a first circuit configured to provide a charging current to charge a control terminal of the power switch, a second circuit configured to provide a discharging current to discharge the control terminal of the power switch, and a control circuit configured to provide control signals to the first circuit and the second circuit to activate/deactivate the first circuit and the second circuit. At least one of the charging current and the discharging current ramps from a first level to a second level at a rate.

Abstract: Pulse width modulated controller systems. Implementations may include: a microcontroller coupled with a memory, a switch controller coupled with the microcontroller, and a calibration unit. The calibration unit may include one or more comparators, one or more passive electrical components, and an encoder logic all operatively coupled together and coupled with the microcontroller and with the switch controller where the at least one comparator and the one or more passive electrical components are electrically coupled with a supply voltage to the semiconductor switch and with a load voltage (output voltage) from the semiconductor switch.

Abstract: A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: A scan driving circuit is disclosed and used to execute a driving operation for cascaded scan lines. The scan driving circuit has a pull-down control module, a pull-down module, a pull-up module, a pull-up maintaining module, a bootstrap capacitor, a constant low-level voltage source and a constant high-level voltage source; the scan driving circuit uses a PMOS type transistor to control the pull-down control module, the pull-down module, the pull-up module and the pull-up maintaining module. The scan driving circuit has a simple overall structure and lower energy consumption.

Abstract: Malfunction can be reliably avoided even when a signal that drives a high side power device is not normally transmitted in a level shift circuit. In a drive circuit, a pulse generator circuit generates a set signal and reset signal that causes a high side power device to be turned on or off. The pulse generator circuit provides set and reset signals, via a level shift circuit, to a high side drive circuit. A high side potential (a high side reference potential or a high side power supply potential) is detected by a high side potential detector circuit. A high side potential determination circuit determines a change in potential that impedes the transmission of the set signal or reset signal in the level shift circuit, and causes the pulse generator circuit to regenerate the set signal or reset signal when the timing of the detection coincides with the timing at which the set signal or reset signal is generated.

Abstract: A gate drive circuit includes: a modulation circuit that generates a first modulated signal and a second modulated signal; an isolator including a first electromagnetic resonance coupler that isolatedly transmits the first modulated signal, and a second electromagnetic resonance coupler that isolatedly transmits the second modulated signal; a first rectifier circuit that generates a first signal by rectifying the first modulated signal; a second rectifier circuit that generates a second signal by rectifying at least a part of the second modulated signal; a third rectifier circuit that generates charging voltage by rectifying a second radio-frequency wave; a capacitor that charges a charge in accordance with the charging voltage; and an output circuit which selects whether or not to supply the charge charged in the capacitor to a gate terminal of the semiconductor switch, in accordance with at least one of the first signal and the second signal.

Abstract: A control circuit of a semiconductor switching element includes a gate driving circuit and a negative power source circuit. The gate driving circuit drives the semiconductor switching element disposed on a power supply path of an inductive load. The negative power source circuit is connected between output terminals of the semiconductor switching element. The negative power source circuit includes a series circuit of a capacitor and a diode in a forward direction connected from a negative potential side terminal to a positive potential side terminal of the output terminals. A common connection point of the capacitor and the diode in the negative power source circuit is connected to a negative power source terminal of the gate driving circuit.

Abstract: A method is disclosed for switching a semiconductor switch from a first static switch state to a second static switch state by controlling a control connection of the semiconductor switch. The method includes switching the semiconductor switch in a current-controlled manner starting from the first static switch state in a first switching phase by applying at least one first specified actuating current at the control connection of the semiconductor switch in a controlled manner, and switching the semiconductor switch in a voltage-controlled manner in a second switching phase following the first switching phase by applying at least one first specified actuating voltage to the control connection of the semiconductor switch in a controlled manner until the second static switch state is reached. In this manner, switching losses are reduced.

Abstract: A device for controlling at least one transistor is disclosed. The device includes the transistor, which includes a control electrode and two other electrodes, a main control circuit connected to the control electrode of the transistor and configured to control the state of the transistor in a main operating mode, and an auxiliary control circuit configured to inject, in an auxiliary operating mode. An auxiliary current opposed to the current flows between the main control circuit and the control electrode of the transistor.

Abstract: The present invention provides a liquid crystal display and a shift register thereof. Each shift register unit of the shift register comprises a storage circuit, receiving and temporarily storing a former stage signal, a voltage level control circuit and an inverter circuit, charging and discharging scan lines of a liquid crystal display panel, and a first node exists between the voltage level control circuit and the inverter circuit, and a second node exists between the storage circuit and the voltage level control circuit, and the storage circuit is employed to selectively invert and output received level signals to the second node under control of a first sequence signal, and the voltage level control circuit is employed to provide a low level signal to the first node, and the inverter circuit is employed to selectively invert and output the low level signal provided by the voltage level control circuit under control of a second sequence signal.

Abstract: In accordance with an embodiment, a circuit includes a normally-off transistor, and a normally-on transistor comprising a second load path terminal coupled to a first load path terminal of the normally off transistor, and a control terminal coupled to a second load path terminal of the normally-off transistor. The circuit further includes a driver circuit having an output coupled to a control terminal of the normally off transistor, a first power supply terminal configured to be coupled to a first power supply terminal of a first power supply, and a second power supply terminal configured to be coupled to a second power supply terminal of a second power supply. The second load path terminal of the normally on transistor is further configured to be coupled to a second power supply terminal of the first power supply and to a first power supply terminal of the second power supply.

Abstract: A drive unit includes a charging unit which charges an opening/closing control terminal of a switching element to switch a drive state. The switching element includes a sensing terminal which outputs a minute current having a correlation with current flowing between input and output terminals of the switching element. The sensing terminal and either of the output terminal or a member having a potential equal to that of the output terminal are connected via a sensing resistor. The drive unit further includes an active gate control unit which changes a charge rate based on comparison of sensing voltage, which is a potential difference across the sensing resistor, or a rate of change of the sensing voltage with a specified value. The specified value is set based on individual-difference information of the switching element which indicates a characteristic, which affects the sensing voltage, when the drive state is switched.

Abstract: Disclosed is a half-power buffer/amplifier. The half-power buffer/amplifier includes first and second amplifying blocks respectively corresponding to first and second channels, a first output buffer unit controlled by an output from the first amplifying block, and a second output buffer unit controlled by an output from the second amplifying block. Each of the first and second amplifying blocks includes an input unit configured to amplify a first input signal, thereby outputting first and second currents, and an amplifying unit including a first current mirror, a second current mirror, and a bias unit connected between the first current mirror and the second mirror. Nodes in the first and second amplifying blocks are selectively connected to source/drain terminals of transistors in the first and second amplifying blocks in response to a control signal.

Abstract: A driving apparatus of the present disclosure includes a coil including a second terminal connected to a control terminal of a switching element, a charging switch connected between a first potential line and a first terminal of the coil, a clamp switch connected between the first potential line and the control terminal of the switching element, a charging diode connected between a second potential line and the first terminal of the coil, and a control circuit that outputs a charging control signal for turning on the charging switch and for turning off the charging switch before a potential of the control terminal of the switching element reaches the first potential and a clamp control signal for turning on the clamp switch after the charging switch is turned on.

Abstract: A gate drive circuit in an aspect of the present disclosure includes: a first electromagnetic resonant coupler that isolatedly transmits a transmission signal from the primary side to the secondary side, and also isolatedly transmits a reflected signal from the secondary side to the primary side; a modulator circuit that modulates a radio-frequency wave with an input signal to generate the transmission signal; a demodulator circuit that demodulates the transmission signal to generate an output signal; a variable capacitance diode into which the transmission signal is input from the first electromagnetic resonant coupler, the variable capacitance diode disposed on the secondary side, the variable capacitance diode allowing a capacitance thereof to vary according to a monitor signal; and a reflected signal rectifier circuit that rectifies the reflected signal input to generate a monitor output signal.

Abstract: An ignition exciter system for igniting fuel in a gas turbine engine. The ignition exciter system includes a rechargeable energy source, at least one pulse-forming network coupled to the rechargeable energy source and generating a stored energy waveform from energy in the rechargeable energy source, at least one igniter plug coupled to the at least one pulse-forming network to receive the stored energy waveform and generating a spark in response to the received stored energy waveform.

Abstract: A driver circuit includes normally-on first and second transistors, a first control circuit for controlling the first transistor in response to a first control signal, a second control circuit for controlling the second transistor in response to a second control signal, a capacitor connected between first and second power supply nodes of the first control circuit, a power supply connected between third and fourth power supply nodes of the second control circuit, a switch element connected between first and fourth power supply nodes, and a third control circuit for turning the switch element on when an output voltage becomes about 0V.

Abstract: There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state.

Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Abstract: A gate driver circuit includes several shift register stages. One of shifter register stages includes a pull-up unit, a pull-up control unit, and an output unit. The pull-up unit is configured for generating a driving signal according to a first clock signal and an operating signal. The pull-up control unit is configured for generating a next-stage operating signal to a next-stage shift register stage according to the first clock signal, the operating signal and the driving signal. The output unit is configured for receiving the driving signal and generating a first gate driving signal and a second gate driving signal according to a first controlling signal and a second controlling signal, respectively.

Abstract: A system for transferring information from a first circuit to a second circuit includes first and second isolation elements coupled between the first circuit and the second circuit. A first transient filter is located on the second circuit and coupled to the first isolation element. A second transient filter is located on the second circuit and coupled to the second isolation element. A first ground is located on the first circuit, and a second ground is located on the second circuit. The first ground electrically floats relative to the second ground.

Abstract: A driving apparatus includes a first potential line that applies a first potential, a second potential line that applies a second potential, a coil including a first terminal and a second second terminal that is connected to a control terminal of a switching element, a charging switch connected between the first potential line and the first terminal of the coil, a clamp switch provided between the first potential line and the second terminal of the coil, a reverse-flow blocking diode connected in series with the clamp switch between the first potential line and the second terminal of the coil, and a control circuit that controls the charging switch and the clamp switch.

Abstract: A four pin integrated circuit MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) load switch is disclosed that provides full features including adjustable ramp time/rate, adjustable discharge time/rate, temperature control, over-current control, and short circuit protection. In some embodiments, the adjustable ramp is based on the voltage or current input into the integrated circuit.

Abstract: A gate driver circuit may include a driving signal generating unit generating first and second control signals based on a data signal and a fault state signal and controlling gate detection, a driving inverter operating in response to the first and second control signals to generate a gate signal and providing the gate signal to a power switch element, and a soft turn-off/gate detecting unit operating in response to the second control signal, performing a soft turn-off in the case of a fault, and detecting the gate signal to provide a detected signal.

Abstract: System and method are provided for driving a transistor. The system includes a floating-voltage generator, a first driving circuit, and a second driving circuit. The floating-voltage generator is configured to receive a first bias voltage and generate a floating voltage, the floating-voltage generator being further configured to change the floating voltage if the first bias voltage changes and to maintain the floating voltage to be lower than the first bias voltage by a first predetermined value in magnitude. The first driving circuit is configured to receive an input signal, the first bias voltage and the floating voltage. The second driving circuit is configured to receive the input signal, a second bias voltage and a third bias voltage, the first driving circuit and the second driving circuit being configured to generate an output signal to drive a transistor.

Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

Abstract: A DC-DC Buck circuit has a DC input terminal, a DC output terminal, a ground terminal, an inductor, a capacitor, a sampling resistor, a PWM control chip and a DrMOS chip. The output of the driver pin of the PWM control chip is unrelated to the voltage between the inductor and the sampling resistor. The DC-DC Buck circuit can produce a larger output voltage while also being compatible with a DrMOS chip.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract: Some aspects of the present disclosure provide system and method of operation of a driving circuit for a light emitting element in a Time-of-Flight (ToF) camera. A DC-DC converter is configured to emit a constant current, and is coupled in parallel to a first modulation switch configured to connect the driving circuit to ground. The first modulation switch is further configured to alternate connections between the current source and ground at a frequency in a desired range of operation to produce an AC current. In some embodiments, an RC circuit element is coupled to an output electrode of the light emitting element and configured to apply a reverse bias to decrease turn-off time of the light emitting element. In some embodiments, a second modulation switch is coupled to the output electrode and configured to apply the reverse bias across the light emitting element. Other systems and methods are also disclosed.

Abstract: A device for connecting to a two-wire communications bus, a bus station that, while utilizing the device, is able to send messages, represented on the bus lines as dominant and recessive bus levels, to additional connected bus stations and receive same from them. The device includes (a) an arrangement setting a dominant bus level in the form of a first voltage difference between the two bus lines by driving a first electric current, and the device is suitable for the recessive bus level to set in as the second voltage difference between the two bus lines, at least partially by the flowing of a discharge current via terminating resistors connected to the bus lines; and (b) an arrangement to speed up the setting of at least one of the bus levels by driving at least one additional electric current, at least in response to the presence of a switching condition.

Abstract: A system for optimizing switching dead-time includes a power converter that includes a half-bridge circuit comprising a first switch coupled in series with a second switch, first and second state detection circuits respectively coupled to the first and second switches and configured to respectively detect an activation state of the first and second switches. First and second switch control circuits coupled respectively to the first and second switches are configured to respectively toggle the first and second switches between an activate state and a deactivated state. The first switch control circuit includes a first input configured to receive an activation signal from the second state detection circuit indicative of the activation state of the second switch, and the second switch control circuit includes a first input configured to receive an activation signal from the first state detection circuit indicative of the activation state of the first switch.