Abstract: An apparatus and a method are provided to drive FET with voltage determined by current through the FET and parameters of FET to get maxim efficiency for any specific load current and variable load current; two versions of the invention are provided; one version of the invention is to provide an independent power supply with selected voltage value; the other version of the invention is to provide a controllable variable output voltage power supply to supply variable voltage to driver corresponding to variable load current.

Abstract: A semiconductor device or power electronic device is described. The device includes a pair of pole pieces, each having a profiled surface. A semiconductor body or wafer, preferably of wide bandgap electronic material, is located between the pole pieces and includes contact metallisation regions. The semiconductor body produces an electric field that emerges from an edge region. Passivation means includes a first or radially inner part in contact with the edge region of the semiconductor body and which diffuses the electric field as it emerges from the edge region and a second or radially outer part. The second part of the passivation is in contact with the first part and provides a substantially void-free interface with the profiled surface of each pole piece. The device may be immersed in a dielectric liquid.

Abstract: There are provided a level shifter circuit and a gate driver circuit including the same. The level shifter circuit includes: a plurality of switching devices connected to a predetermined DC power supply through a resistor and operated by different driving signals; a gain conversion unit operated by first signals output from the plurality of switching devices, respectively, and generating second signals having a level within a predetermined range of the first signals; and a noise removal unit connected to at least one output terminal among the plurality of switching devices to prevent malfunctioning of the gain conversion unit, wherein the gain conversion unit inputs the second signals to a high side gate driver circuit through an inverter circuit.

Abstract: Devices and methods are provided in which a driver is supplied via a first current path and a second current path which can comprise a switching element.

Abstract: A voltage generating circuit includes first and second step-up circuits, each having first and second input terminals and an output terminal and configured to increase a voltage level of an input signal supplied through the first input terminal and output the signal with the increased voltage level through the output terminal. The second input terminal of the first step-up circuit is connected to the output terminal of the second step-up circuit and the second input terminal of the second step-up circuit is connected to the output terminal of the first step-up circuit. The voltage generating circuit may also include third and fourth step-up circuits and fifth and sixth step-up circuits having similar configurations.

Abstract: Provided is a semiconductor integrated circuit including an internal voltage generator for generating an internal voltage. A semiconductor integrated circuit includes a dividing unit, a comparing unit, a driving unit, and a voltage level controlling unit. The dividing unit divides an internal voltage in a predetermined division ratio to output a feedback voltage. The comparing unit compares a feedback voltage with a reference voltage. The driving unit drives an internal voltage terminal in response to an output signal of the comparing unit. The voltage level controlling unit controls a voltage level of the output signal of the comparing unit in response to a first control signal that is activated at a predetermined time before an operation time point of an internal circuit using an internal voltage.

Abstract: A MOSFET at an input side controls the operation of a current mirror circuit in accordance with a level change of a PWM signal applied to its gate. When the current mirror circuit operates, a current generated by a current source flows as a mirror current so that a current flows to discharge electricity charged in a capacitance between a gate and a source through a gate of a MOSFET at an output side. When the current mirror circuit stops its operation, a current flowing from the current mirror circuit through the current source is supplied to the gate of the MOSFET at the output side.

Abstract: According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.

Abstract: A gate driving circuit for driving a voltage-driven switching device is provided with a current limiting circuit for limiting a gate current ig that flows into a gate terminal through a gate resistor at turn-on to a current limit value IL which defines an upper limit value. The current limit value IL is set at a value which is larger than a gate current value I2 at turn-on of the switching device during a period when the Miller effect occurs but is smaller than a gate current value I1 at a point in time when a main current begins to flow at turn-on in a case where the gate current ig is not limited by the current limiting circuit. This arrangement makes a variation in a collector current of the switching device moderate at turn-on thereof when the collector current begins to flow, thereby reducing high-frequency noise.

Abstract: A driving circuit for driving a power semiconductor switch wherein at least one semiconductor device being provided which is implemented in such a way that it is operated in breakdown in response to the exceeding of a specific collector-emitter voltage of the power semiconductor switch, an output of the at least one semiconductor device being connected via a conductive interconnect to a terminal between the resistors of the resistor series circuit or to the resistor-series-circuit output which is connected to the signal processing unit, and the breakdown voltage of the at least one semiconductor device being selected in such a way that the potential at the output of the at least one semiconductor device is greater than the potential at the gate of the power semiconductor switch in its ON state. The invention further relates to a method for driving a power semiconductor switch.

Abstract: The present invention relates to a switch controller, a power supply including the same, and a driving method thereof. An AC input of the power supply is connected to a rectification circuit. The power supply includes a power switch to which the AC input passed through the rectification circuit flows during a turn-on period of the power switch and a switch controller detecting a half-on time point that is an intermediate time point of the turn-on period, calculating the AC current using a result of sampling a sense voltage that depends on a current flowing to the power switch during the turn-on period at the half-on time point and the turn-on period, and controlling the input current to have a reference sine wave. The reference sine wave has a sine wave that is full-wave rectified from the AC input.

Abstract: In a driving system for driving a switching element, a controller controls the switching element. A temperature measuring module measures a temperature of the switching element, and output a first signal representing the measured temperature of the switching element as first information. A state determining module determines whether the switching element is in a specified temperature state based on the first signal, and outputs a second signal representing a result of the determination as second information. A communication medium communicably connects between the controller and the state determining module, and the second signal output from the state determining module being transferred to the controller via the communication medium. The controller determines how to drive the switching element based on the second information in the second signal transferred thereto via the communication medium.

Abstract: A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.

Abstract: A low power consumption semiconductor driving circuit is provided which applies positive and negative bias signals to a semiconductor switching element by using a single power source to perform the switching of the semiconductor switching element. The semiconductor driving circuit is a semiconductor driving circuit for driving the semiconductor switching element. The semiconductor driving circuit includes an internal power source circuit for generating a second voltage from a first voltage supplied from an external power source, and a driver for applying the first voltage or the second voltage between the gate and emitter of the semiconductor switching element in accordance with an input signal inputted from outside to switch on and off the semiconductor switching element. The internal power source circuit is configured to operate in accordance with the input signal.

Abstract: A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of a capacitor and the input of an inverter, and a source is connected to a first wiring. The other electrode of the capacitor is connected to a second wiring. In such a memory element, the potential of the second wiring is complementary to the potential of the first wiring when writing data; accordingly, the potential of the drain of the transistor, i.e., the potential of the input of the inverter can be higher than the high potential of the inverter. Thus, shoot-through current of the inverter at this time can be significantly reduced. As a result, power consumption in a standby state can be significantly reduced.

Abstract: In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.

Abstract: This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.

Abstract: In a drive unit for a switching element, a drive circuit changes the switching element between an on-state and an off-state, by controlling a potential difference between a reference terminal, which is one of a pair of ends of a current path of the switching element, and an opening-closing control terminal of the switching element. A determination section determines, if an on-operation command or an off-operation command is inputted as an operation signal for the switching element, whether or not the potential difference has reached a specific value toward which the potential difference shifts, in response to one of the operation commands, with respect to a threshold value by which the switching element is turned on. A forcible processing section removes charge for turning on the switching element from the opening-closing control terminal, if the determination section determines that the potential difference has not reached the specific value.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a driving signal generator comparing first and second internal voltage signals with lower and upper limit reference voltage signals to generate a pull-up driving signal and a pull-down driving signal, a driver generating a first voltage and a second voltage in response to the pull-up driving signal and the pull-down driving signal, a selecting signal generator comparing the first internal voltage signal with the second internal voltage signal to generate a selection signal, and a selection transmitter that transmits any one of the first and second voltages to the first or second internal voltage signal in response to the selection signal.

Abstract: To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.

Abstract: An active clamp current sink is used to voltage protect a low voltage rated, high power current sink that drives illumination current through a string of serially connected LEDs. When the LEDs are turned off as part of a PWM configuration, the forward voltage on the LEDs falls, and the voltage presented to the low voltage rated, high power current sink rises. The active clamp current sink monitors the voltage across the high power current sink and ensures that an adequate current flows through the LEDs. This minimally adequate current maintains a sufficiently large forward voltage through the LEDs, and therefore a sufficiently small voltage is presented to the high power current sink.

Abstract: A communication method includes detecting at a gate drive unit a change of state of a command signal that is received via a command link of the gate drive unit and initiating, responsive to the change of state of the command signal, a blanking period in which the gate drive unit will process as incoming data any further changes of state of the command signal. The method also includes receiving incoming data at the gate drive unit, by processing modulations of the command signal, within the blanking period.

Abstract: In one embodiment, a power switch driving circuit can include: (i) a first circuit configured receiving a control signal, and controlling a first transistor gate, where a first transistor source is coupled to a power supply, and a first transistor drain is coupled to a driving signal configured to control a power switch; (ii) a second circuit configured to receive the control signal, and to control a second transistor gate, where a second transistor source is coupled to ground, and a second transistor drain is coupled to the driving signal; and (iii) a driving enhancement circuit having a third transistor and a first inverter that is configured to invert an output of the first circuit to control a third transistor gate, where a third transistor source is coupled to the driving signal, and a third transistor drain is coupled to the power supply.

Abstract: A transmitter comprises a protection circuit; a first termination resistor having a first end coupled to a first voltage source, and a second end coupled to the protection circuit; a second termination resistor having a first end coupled to the first voltage source, and a second end coupled to the protection circuit, wherein the second end of the first termination resistor and the second end of the second termination resistor form a differential output pair; a current switch coupled to the protection circuit; a current source coupled to the current switch; and a pre-driver circuit coupled to the current switch, for controlling the current switch, making the differential output pair generate an output current. Wherein, the pre-driver circuit receives a second voltage source, and the first voltage source is higher than the second voltage source.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: A control device of a switching circuit of a resonant apparatus is described. The switching circuit comprises at least one half-bridge having a high-side transistor and a low-side transistor connected between an input voltage and a reference voltage; the resonant apparatus comprises a resonant load. The control device is configured to determine the on time period and the off time period of the transistors alternatively and a dead time of both the transistors so that a periodic square-wave voltage is applied to the resonant load. The control device comprises a detector adapted to detect the current sign flowing through the resonant load and a correction circuit configured to extend the current operating time period of said two transistors in response to at least the current sign detected from the detection means.

Abstract: A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract: The present document discloses a driver circuit for the high side switch of a half bridge at ultra-high voltage. The half bridge comprises the high side switch coupled to an input voltage Vin and to a midpoint of a low side switch. The driver circuit comprises a control signal generation unit generating a stream of control pulses and a control logic generating a gate voltage for the high side switch using a supply voltage Vcc based on the control pulses, a supply voltage capacitor generating the supply voltage Vcc, and a decoupling capacitor coupled on a first side to the control signal generation unit and on a second side to the control logic, to the midpoint of the half bridge via a first charging switch, and to the supply voltage capacitor via a second charging switch.

Abstract: To achieve low power consumption of a semiconductor device including a plurality of function blocks capable of being in either an operating state or a not-operating state, by effective use of electric charge discharged from a not-operating function block. In a semiconductor device including a plurality of function blocks, a capacitor is electrically connected to the plurality of function blocks so that electric charge discharged from a not-operating function block is accumulated in the capacitor. Then, the electric charge accumulated in the capacitor is supplied to a function block to be in an operating state, and then power is supplied from a power source to the function block.

Abstract: Various exemplary embodiments relate to gate driver circuitry that compensate for parasitic inductances. Input buffers in the gate driver are grounded to an exposed die pad. Grounding may involve either a downbond or conductive glue.

Abstract: A gate driver (100), a high-side MOSFET switch system (200) and a method (300) of pulse-driven switching a MOSFET employ a Miller capacitance or a Miller capacitance threshold. The gate driver (100) includes a gate discharge portion (110) to provide a first voltage for a first time period to a gate of a MOSFET (102). The first voltage is less than a turn-on threshold voltage of the MOSFET. The gate driver further includes a gate charge portion (120) to provide a second voltage for a second time period to the MOSFET gate. The second voltage is greater than the MOSFET turn-on threshold voltage. The second time period is less than a time period for a gate-source voltage of the MOSFET to exceed the Miller capacitance threshold. The method (300) of pulse-driven switching of a MOSFET includes applying (310) the first voltage for the first time period and applying (320) the second voltage for the second time period.

Abstract: A method for driving a field effect transistor for shaping an electrical signal, representing a sound, to an output signal is disclosed. The method comprises modifying the input signal to an intermediate signal, and output of the intermediate signal to the field effect transistor for shaping the output signal. The method comprises the steps of adjusting the quiescent point of the field effect transistor such that the same is placed in the quadratic region of the transfer characteristics of the field effect transistors, and adjusting the amplitude of the intermediate signal, such that the same causes the potential swing between the gate terminal and the source terminal to at least partly be in the quadratic region of the transfer characteristics of the field effect transistor.

Abstract: The present invention is a method and circuitry for driving a high-threshold MOS device on low input voltages. The invention includes a circuit that operates on a supply voltage that is less than the threshold voltage of the high-threshold MOS device. The circuit includes one or more low threshold MOS inverters and one or more capacitors that operate at low input voltages. The one or more low threshold MOS inverters operate in a manner that the one or more capacitors get charged to a voltage greater than the low input voltage. Thereafter, the charged capacitor drives the high threshold MOS device.

Abstract: A display panel includes a base substrate, a first gate line, a second gate line, first and second gate pads, a data line, a delay compensating line and a first delay compensating transistor. The first gate line extends in a first direction on the base substrate. The second gate line is substantially parallel to the first gate line. The first and second gate pads extend from first terminals of respective first and second gate lines. The data line extends in a second direction which is different from the first direction. The delay compensating line is substantially parallel to the data line. The first delay compensating transistor is electrically connected to the first and second gate lines and to the delay compensating line.

Abstract: A switch apparatus includes a semiconductor power switch connected for delivering current while driven by a gate drive voltage and an adaptive gate drive unit connected to a gate of the power switch. The gate drive unit is configured to select one of a plurality of pre-determined time functions for a gate drive voltage, and to deliver the gate drive voltage to the gate of the power switch according to the selected time function, thereby driving the power switch to deliver current within a pre-determined slew rate envelope.

Abstract: A gate driving circuit includes first to n-th gate clock lines, first to m-th selection lines, a holding control line, a voltage line and a plurality of stages. The first to n-th gate clock lines transfer first to n-th gate clock signals. The first to m-th selection lines transfer first to m-th gate selection signals. The holding control line transfers a holding control signal. The voltage line transfers a gate-off voltage. The stages outputs a plurality of gate signals, each stage outputs a high voltage of a gate clock signal as a gate-on voltage of a gate signal in response to a high voltage of a gate selection signal, and outputs the gate-off voltage in response to a high voltage of the holding control signal.

Abstract: Providing a driver for semiconductor switch element capable of securing a sufficient drive power and reliably turning off the semiconductor switch element. The driver includes a converter section 2 which includes a switching element Q1 and which is configured to output a desired DC voltage by switching the switching element Q1, a control section 1 configured to control the switching operation of the switching element Q1, capacitors C1A, C1B charged by the output of the converter section 2, turn-on circuits 31A, 31B configured to supply gates of a bidirectional switch element 4 using electric charges stored in the capacitors C1A, C1B with drive powers to turn-on the bidirectional switch element 4, and turn-off circuits 32A, 32B configured to discharge the capacitors C1A, C1B to turn-off the bidirectional switch element 4 in response to the halt of the switching operation of the switching element Q1 by the control section 1.

Abstract: A programmable input/output circuit includes a programmable output circuit configured to drive an output signal to an input/output pad at a plurality of voltages, at least one of the plurality of voltages being supplied by an external circuit. The programmable input/output circuit further includes a programmable input configured to detect an input signal from the input/output pad at the plurality of voltages. The voltage levels of the input and output circuits may be independently and dynamically controllable.

Abstract: According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.

Abstract: A gate driver turns on/off a switching element Q1 by applying a control signal from a controller to a gate of the switching element. The switching element has the gate, a drain, and a source and contains a wide-bandgap semiconductor. The gate driver includes a parallel circuit that includes a first capacitor C1 and a first resistor R1 and is connected between the controller and the gate of the switching element and a short-circuit unit S4 that is connected between the gate and source of the switching element and short-circuits the gate and source of the switching element after a delay from an OFF pulse of the control signal.

Abstract: A circuit arrangement includes a half-bridge with a high-side switch and a low-side switch, each switch including a control terminal and a load path. The load paths of the high-side switch and the low-side switch are coupled in series between a terminal for a supply potential and a terminal for a reference potential a high-side driver operable to provide a high-side drive signal received at the control terminal of the high-side switch. The high-side driver includes supply terminals a charge storage device coupled between the supply terminals of the high-side driver. A control circuit includes a charging circuit, a switching element and a drive circuit operable to switch on the switching element dependent on at least one operation parameter of the circuit arrangement.

Abstract: A circuit, which includes a high voltage driver, is disclosed. The high voltage driver includes a P-type field effect transistor (PFET) and a source bias circuit. The source bias circuit receives a low voltage input signal and applies a direct current (DC) bias to the low voltage input signal to provide a DC biased signal. The PFET has a first source, a first gate, and a first drain. The first source receives the DC biased signal. The first gate receives a first low voltage DC supply signal. The first drain provides a high voltage output signal based on the DC biased signal and the first low voltage DC supply signal. In this regard, the high voltage driver receives and translates the low voltage input signal to provide the high voltage output signal.

Abstract: In a power conversion device provided with a power semiconductor device and a semiconductor driver circuit for driving the power semiconductor device, false firing can be prevented, and improvement in reliability can be achieved. The power conversion device is provided with: a first switch element inserted between a power supply voltage and an output node; a second switch element inserted between a ground power supply voltage and the output node; and a gate driver circuit for controlling turning ON/OFF of the second switch element. When the second switch element is controlled to be turned OFF, the gate driver circuit drives a gate-source voltage at, for example, a level of 0 V.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate and a transistor on the substrate. The semiconductor devices may include a first guard ring of first conductivity type in the substrate adjacent the transistor. The semiconductor devices may include a second guard ring of second conductivity type opposite the first conductivity type in the substrate adjacent the first guard ring. Related semiconductor systems are also provided.

Abstract: A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

Abstract: A synchronous driving circuit in the arts may cause a short through pheromone when a duty cycle of a duty cycle control signal is too short. The present invention sets a delay time with a suitable period when the duty cycle of the duty cycle control signal is too short to avoid the short through phenomenon.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.

Abstract: A control circuit is provided including a trigger circuit having a capacitor connected between a pulse generator and a second switching element, and a latch circuit connected via a diode, between a junction of a load with a first switching element and the control terminal of the second switching element, wherein when the pulse generator outputs a drive signal, both of the first switching element and the second switching element are turned on and the second switching element is held in the ON state through the latch circuit by a voltage at the junction. When the drive signal is stopped, both of the first switching element and the second switching element are turned off; meanwhile if the load is short-circuited, the first switching element and the second switching element are turned off through the latch circuit by the voltage at the junction.

Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.