Abstract: A display and a gate driver are disclosed herein, in which the gate driver includes a number of gate driving units, and each of the gate driving units includes a control circuit, a boost circuit, a driver output circuit and a voltage stabilized circuit. The control circuit is electrically connected to a previous gate driving unit and a next gate driving unit. The boost circuit is electrically connected to the control circuit for driving the next gate driving unit. The driver output circuit is electrically connected to the boost circuit and a pixel array for driving at least one scan line in the pixel array. The voltage stabilizing circuit is electrically connected to the boost circuit and the driver output circuit.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage.

Abstract: A half bridge gate driving circuit for providing gate driving circuits in a bi-hecto celcius (200 degrees celcius) operating environment having multiple functions including combinations of multiple level logic inputs, noise immunity, fault protection, overlap protection, pulse modulation, high-frequency modulation with transformer based isolation, high-frequency demodulation back to pulse width modulation, deadtime generator, level shifter for high side transistor, overcurrent protection, and undervoltage lockout.

Abstract: An adaptive gate drive circuit that can generate a gate bias voltage with temperature compensation for a MOSFET is disclosed. The adaptive gate drive circuit may generate the gate bias voltage with variable drive capability to combat higher gate leakage current of the MOSFET at higher temperature. In one design, an apparatus includes a control circuit and a gate drive circuit. The control circuit generates at least one control signal having a variable frequency determined based on a sensed temperature of the MOSFET. For example, a clock divider ratio may be determined based on the sensed temperature of the MOSFET, an input clock signal may be divided based on the clock divider ratio to obtain a variable clock signal, and the control signal(s) may be generated based on the variable clock signal. The gate drive circuit generates a bias voltage for the MOSFET based on the control signal(s).

Abstract: A gate control circuit including: a gate input arranged to receive an input gate feed signal; a gate output arranged to be connected, during normal operation, to at least one switching module for controlling current through a main circuit, the gate output being connected to the gate input; a power supply; and a switch connected between the power supply and the gate output, the switch being arranged to close as a response to a failure. A corresponding power module and method are also presented.

Abstract: Low headroom line driver circuits are disclosed. In several embodiments, the line driver circuits include a first transistor, a second transistor, a third transistor and a fourth transistor, where the first transistor and second transistors; and the third and fourth transistors are matched, first and second matched impedances, first and second driver controls circuit configured to apply control signals to the gates of the first and second transistors; and the third and fourth transistors respectively. In addition, the first and third transistors; and the second and fourth transistors are configured as a pair of stacked transistors connected between the voltage supplies Vdd and Vss, the second and fourth transistors are configured as a pair of stacked transistors connected between the voltage supplies Vdd and Vss, the matched impedances are connected in series between nodes formed by the connection between the first and third transistors; and the second and fourth transistors.

Abstract: Disclosed is an electronic circuit. The electronic circuit includes a transistor having a control terminal to receive a drive signal, and a load path between a first and a second load terminal. A voltage protection circuit is coupled to the transistor, has a control input, is configured to assume one of an activated state and a deactivated state as an operation state dependent on a control signal received at the control input, and is configured to limit a voltage between the load terminals or between one of the load terminals and the control terminal. A control circuit is coupled to the control input of the voltage protection circuit and is configured to deactivate the voltage protection circuit dependent on at least one operation parameter of the transistor and when a voltage across the load path or a load current through the load path is other than zero.

Abstract: A gate drive circuit capable of operating at high speed and with low loss without erroneously operating the switching element is provided with a small number of components and a simple and easy circuit configuration. A primary side of a transformer is connected to an output terminal of a low-side gate drive circuit, and a secondary side of the transformer is connected to a gate input side of a high-side switching element. As a positive gate drive voltage is output from the low-side drive circuit, a negative voltage is applied between the gate and source of a high-side switching element, and a gate voltage is suppressed to be equal to or lower than a threshold value. Therefore, the high-side switching element maintains a turn-off state when the low-side switching element is turned on.

Abstract: Disclosed are a gate driver and a display device including the same. The gate driver comprises a register which stores data, a gate driving circuit which generates driving signals based on the data stored in the register, and one or more output terminals which output the driving signals generated by the gate driving circuit.

Abstract: In a driver, a clamping module executes a clamping task that clamps an on-off control terminal voltage to be equal to or lower than a clamp voltage for a predetermined time during charging of the on-off control terminal of the switching element. The clamp voltage is lower than an upper limit of the voltage at the on-off control terminal of the switching element. A measuring module measures a parameter value correlated with a sense current correlated with a current flowing between input and output terminals of the switching element. A limiting module discharges the on-off control terminal to limit flow of the current between the input and output terminals if the value of the parameter exceeds a threshold. A setting module variably sets a length of the predetermined time as a function of the parameter value during charging of the switching element's on-off control terminal.

Abstract: AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.

Abstract: A system for regulating semiconductor devices may include a current regulator configured to regulate one or more currents provided to an insulated gate bipolar transistor (IGBT). The current regulator may regulate the currents by generating a current profile based at least in part on a collector voltage value associated with the IGBT, a rate of collector voltage change value associated with the IGBT, or any combination thereof The current profile may include one or more current values to be provided to a gate of the IGBT such that the current values are configured to limit the rate of collector voltage change to a first value. The current regulator may then send the one or more current values to a current source configured to supply the gate of the IGBT with one or more currents that correspond to the one or more current values.

Abstract: Provided is a semiconductor integrated circuit including an internal voltage generator for generating an internal voltage. A semiconductor integrated circuit includes a dividing unit, a comparing unit, a driving unit, and a voltage level controlling unit. The dividing unit divides an internal voltage in a predetermined division ratio to output a feedback voltage. The comparing unit compares a feedback voltage with a reference voltage. The driving unit drives an internal voltage terminal in response to an output signal of the comparing unit. The voltage level controlling unit controls a voltage level of the output signal of the comparing unit in response to a first control signal that is activated at a predetermined time before an operation time point of an internal circuit using an internal voltage.

Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.

Abstract: According to an embodiment, a solid-state bidirectional switch includes a first and a second power field-effect transistor electrically connected anti-serial with each other. Each of the first and second power field-effect transistors includes a source region, a drain region, a body region forming a pn-junction with the source region and having an inversion channel region, a gate terminal, a drift region between the body region and the drain region and having an accumulation channel region, and a drift control region adjacent to the accumulation channel region. The accumulation channel region is controllable through the drift control region. The solid-state bidirectional switch further includes a controller connected with the gate terminals of the first and second power field-effect transistors.

Abstract: A current providing circuit, for providing an output current at an output terminal, comprising: a current providing module, coupled to a first predetermined voltage level, for providing the output current according to the first predetermined voltage level and a control voltage transmitted to the current providing module; and a control voltage generating module, for generating the control voltage corresponding to the first predetermined voltage level and a threshold voltage of the current providing module.

Abstract: A semiconductor device which stores data, and in which refresh operation is not needed, is described. The semiconductor device comprises at least a transistor and a capacitor. A first electrode of the capacitor is connected to a reference voltage terminal and a second electrode of the capacitor is connected to one of a source and a drain of the transistor. The semiconductor device is configured to put, when necessary, the other of the source and the drain of the transistor to the same potential as the one of the source and the drain, so that charge accumulated in the capacitor, which is connected to the one of the source and the drain of the transistor, does not leak through the transistor.

Abstract: An output buffer is disclosed. The output buffer includes an input-stage circuit, an output-stage circuit and a compensation circuit. The compensation circuit includes a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The input-stage circuit receives a differential input signal and outputting a response signal. The output-stage circuit receives the response signal and outputting an output signal. The first switch controls a connection between the input-stage circuit and a first terminal of the capacitor. The second switch controls the connection between an output terminal of the compensation circuit and a second terminal of the capacitor. The third switch controls the connection between the input-stage circuit and the second-terminal of the capacitor. The forth switch controls the connection between the output terminal of the compensation circuit and the first terminal of the capacitor.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: An output driver and a data output driving circuit using the output driver includes a pull-up driver including at least three pull-up transistors connected between a high voltage and an output node in a stack structure of three stages or more and a pull-down driver including at least three pull-down transistors connected between a ground node and the output node in a stack structure of three stages or more.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: In various embodiments, a driving circuit for a transistor is provided. The driving circuit may include a transistor including a control terminal; a capacitance; a first switch and a power source, wherein the first switch may be coupled between the power source and a first terminal of the capacitance; a second switch and an inductance which may be coupled in series between the first terminal of the capacitance and the control terminal of the transistor.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: Disclosed herein is a solidstate switch driving circuit for a vehicle. The solidstate switch driving circuit includes an oscillation circuit, a constant voltage circuit, a first Field Effect Transistor (FET), a second FET, a third FET configured, a first time constant circuit, a first time constant circuit, a reverse voltage protection diode, a solidstate power switch, and a second time constant circuit. The first time constant circuit is connected to the drain of the second FET and the drain of the third FET. The reverse voltage protection diode has an N pole and a P pole. The solidstate power switch selectively turns on and off power applied to the load. The second time constant circuit has one side connected to the first time constant circuit and the reverse voltage protection diode, and another side connected to a gate of the solidstate power switch.

Abstract: There is offered a switching device control circuit that can accurately estimate a temperature of a power device to execute thermal shutdown without increasing the number of terminals. The control circuit has an output unit controlling an operating current flowing through an IGBT based on an input signal, a temperature detection unit outputting a detection signal when a temperature of the control circuit rises above a second preset temperature that is set corresponding to a first preset temperature of the IGBT after the IGBT commences its operation, and an output control unit controlling the output unit so as to turn off the IGBT in response to the detection signal.

Abstract: Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.

Abstract: The switching current control circuit includes a switching pulse supply circuit, a comparator circuit, and analog circuit unit, a digital circuit unit, etc. The A/D converter (2) detects a load current in an ON period of a switching pulse as a detected current, and converts it into digital data. The arithmetic control circuit (3) calculates a lower limit of the detected current for providing a timing of switching from OFF to ON of the switching pulse, based on the converted data. Continuation/discontinuous modes are determined whether the lower limit is equal to or greater than 0.

Abstract: In one embodiment, a power switch driving circuit can include: (i) an upper switch having a first power terminal coupled to a voltage source, and a second power terminal coupled to a driving signal; (ii) a lower switch having a first power terminal coupled to the driving signal, and a second power terminal coupled to a first voltage level, where the first voltage level is higher than a first ground potential; (iii) an upper switch driving sub circuit configured to receive a control signal, and to drive the upper switch in response thereto; and (iii) a lower switch driving sub circuit configured to receive the control signal, and to drive the lower switch in response thereto, where the upper and lower switch driving sub circuits are coupled to a second ground potential.

Abstract: An electronic switch may include transfer transistor having a first conduction terminal for receiving an input signal, a second conduction terminal, and a control terminal. The transfer transistor may enable/disable a transfer of the input signal from the first conduction terminal to the second conduction terminal according to a control signal. The control signal may take a first value and a second value different from the first value, a difference between the first value and the second value defining, in absolute value, an operative value of the control signal. The electronic switch may further comprise a driving circuit for receiving the input signal and the control signal, and for providing a driving signal equal to the sum between the input signal and the operative value of the control signal to the control terminal of the transfer transistor.

Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Abstract: Embodiments of the present disclosure can be used to produce smaller, more compact antenna drivers at a reduced cost. Systems and methods for integrating components of an antenna driver with components of a shunt regulator and clamp are provided. By combining these components according to embodiments of the present disclosure, transistor count in an antenna driver can be reduced. This integrated device advantageously allows antenna driver functionality, regulator functionality, and clamp control functionality to be provided at a reduced manufacturing cost and with reduced real estate.

Abstract: A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

Abstract: Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique.

Abstract: An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.

Abstract: An electronic device includes: a base member; a conductive film including a first end portion and a second end portion fixed to the base member, the conductive film being movable in a lateral direction of the base member between the first end portion and the second end portion; a first driving electrode, which is provided in the base member at a position opposed to a first main surface of the conductive film, and to which a first driving voltage is applied; a second driving electrode, which is provided in the base member at a position opposed to a second main surface of the conductive film, and to which a second driving voltage is applied; and a terminal provided in the base member at a position where the terminal enables to come into contact with the second main surface of the conductive film.

Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.

Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the re-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of th

Abstract: Negative voltage generators that do not require level shifters or AC coupling capacitors are disclosed. In an exemplary design, a negative voltage generator includes first, second, third and fourth switches, a capacitor, and a control circuit. The first switch is coupled between an input node and a first node. The second switch is coupled between the first node and circuit ground. The third switch is coupled between a second node and circuit ground. The fourth switch is coupled between the second node and an output node. The input node receives a positive voltage, and the output node provides a negative voltage. The capacitor is coupled between the first and second nodes. The control circuit (e.g., an inverter) generates a control signal having positive and negative voltage levels for the third switch using a negative voltage level at the second node.

Abstract: A control circuit includes a basic input output system (BIOS) chip, an embedded controller (EC), and a regulation unit. The BIOS chip outputs control signals corresponding to various operating frequencies of an electronic element. A digital-to-analog conversion unit of the EC receives the control signals, and outputs different types of analog voltages to the regulation unit. The regulation unit provides a proper voltage to the electronic element in relation to the operating frequency of the electronic element.

Abstract: A method includes obtaining a standard value for a characteristic of a power switch and obtaining a measured value of the characteristic, via a gate drive unit connected to a gate terminal of the power switch. The method also includes determining a health state of the power switch by comparing the measured value to the standard value of the characteristic.

Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.

Abstract: An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.

Abstract: A capacitance measuring circuit comprising an oscillator circuit, where a sensor capacitance forms a link of a plurality of series connected impedances and where a square wave voltage is impressed on the series connected impedances from a separate high speed, a low impedance source and the measurement of the charging current, into the series connected impedances, is performed by a separate high accuracy current sensing device, connected in series between the low impedance square wave source and the plurality of the series connected impedances.

Abstract: A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current.

Abstract: A control apparatus for driving a semiconductor switch of an inverter. A drive circuit generates a driver signal on the basis of a switching signal generated by a control regulation system of the inverter. A driver circuit which is coupled between the drive circuit and a control input of the semiconductor switch is configured to receive the driver signal and to generate, on the basis of the driver signal, a control signal which drives the semiconductor switch. The control signal is fed into the control input of the semiconductor switch. A regulation circuit is coupled to the drive circuit and is configured to detect a voltage signal dependent on the voltage across the semiconductor switch, to generate a regulation signal which is dependent on the voltage signal and is intended to regulate the driver signal, and to feed the regulation signal into the drive circuit.

Abstract: In various embodiments, a driving circuit for a transistor is provided, wherein the transistor may include a transistor having a control terminal, a diode, a capacitance with a first terminal and a second terminal, wherein the first terminal may be coupled to the control terminal and the second terminal may be coupled to a reference potential via the diode, and a resistor, which is coupled in parallel to the capacitance.

Abstract: An apparatus and a method are provided to drive FET with voltage determined by current through the FET and parameters of FET to get maxim efficiency for any specific load current and variable load current; two versions of the invention are provided; one version of the invention is to provide an independent power supply with selected voltage value; the other version of the invention is to provide a controllable variable output voltage power supply to supply variable voltage to driver corresponding to variable load current.

Abstract: A semiconductor device or power electronic device is described. The device includes a pair of pole pieces, each having a profiled surface. A semiconductor body or wafer, preferably of wide bandgap electronic material, is located between the pole pieces and includes contact metallisation regions. The semiconductor body produces an electric field that emerges from an edge region. Passivation means includes a first or radially inner part in contact with the edge region of the semiconductor body and which diffuses the electric field as it emerges from the edge region and a second or radially outer part. The second part of the passivation is in contact with the first part and provides a substantially void-free interface with the profiled surface of each pole piece. The device may be immersed in a dielectric liquid.

Abstract: There are provided a level shifter circuit and a gate driver circuit including the same. The level shifter circuit includes: a plurality of switching devices connected to a predetermined DC power supply through a resistor and operated by different driving signals; a gain conversion unit operated by first signals output from the plurality of switching devices, respectively, and generating second signals having a level within a predetermined range of the first signals; and a noise removal unit connected to at least one output terminal among the plurality of switching devices to prevent malfunctioning of the gain conversion unit, wherein the gain conversion unit inputs the second signals to a high side gate driver circuit through an inverter circuit.