Abstract: A method and circuit for lowering impedance of a transistor bridge having two pairs of cooperating transistors, comprising receiving a pair of DC input signals which enable activation of one of the pairs of transistors, the activation providing a path for the DC input signals through the two activated transistors, the pair of DC input signals having voltages differing from each other by a first amount; and applying a second pair of DC signals each to a different gate of the two activated transistors, the second pair of DC signals having voltages differing from each other by a second amount that is greater than the first amount, wherein as a result of the second amount being greater than the first amount, impedances of the two activated transistors are lower as compared to if the pair of DC input signals were used in substitution for the second pair of signals.

Abstract: A PMOS output stage and an NMOS output stage of which output impedances are controlled in accordance with impedance codes, a gate control part which drives output transistors held by the PMOS output stage and the NMOS output stage, and a slew rate control part which generates bias voltages to control driving ability of the gate control part based on an input current are included, and manufacturing variability of an input current circuit generating an input current is corrected by using the impedance code by the slew rate control part.

Abstract: A semiconductor device includes a driver circuit having an output resistance that is controllable responsive to a resistance control signal and a calibration circuit configured to duplicate a resistance behavior of the driver circuit and to generate the resistance control signal responsive to the duplicated resistance behavior. The driver circuit may include a first variable resistor and may be configured to couple an output node to a power supply node via the first variable resistor responsive to an input signal The calibration circuit may include a second variable resistor that is a duplicate of the first variable resistor. The calibration circuit may further include a current source circuit and may be configured to couple the second variable resistor between the power supply node and the current source circuit and to generate the resistance control signal responsive to a voltage of the second variable resistor.

Abstract: A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.

Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: According to an embodiment, an FET drive circuit includes an FET, a first circuit, a resistor and a third rectifying device. The first circuit includes a first rectifying device, a second rectifying device and a capacitive element sequentially provided in series from a drain to a gate of the FET, the first rectifying device allowing a forward electric current flowing from the drain to the gate, and the second rectifying device having a predetermined breakdown voltage with respect to the electric current from the drain to the gate. The resistor is provided between a power source and a connecting point of the second rectifying device and the capacitive element; and the third rectifying device provided between a source and a gate of the FET.

Abstract: The present invention relates to a bootstrap switch circuit and a driving method thereof. The bootstrap switch circuit includes: an input transistor including a first electrode for receiving an input voltage; an output transistor including a second electrode connected to a second electrode of the input transistor, and a first electrode for outputting an output voltage; a control transistor including a control electrode connected to the second electrode of the input transistor and the second electrode of the output transistor, and a first electrode for receiving a power supply voltage; and a level shifter including a power input terminal connected to the second electrode of the control transistor, an output terminal connected to a control electrode of the input transistor and a control electrode of the output transistor, and an input terminal for receiving a switch control signal.

Abstract: A semiconductor device, includes: a first field effect transistor having one terminal to which a first electrical potential is given; a second field effect transistor having one terminal to which a second electrical potential smaller than the first electrical potential is given; a controller that controls each electrical potential of each control terminal of the first field effect transistor and the second field effect transistor; a capacitor element having one end connected to the control terminal of the first field effect transistor, the capacitor element being charged by the control of the controller; and a load element connected between another terminal of the first field effect transistor and another terminal of the second field effect transistor.

Abstract: Disclosed are a gate driving unit capable of having reduced design area and power consumption by reducing an off-time of a gate signal, and an LCD device having the same. The gate driving unit includes N stage circuit units driven by receiving a start signal and first to fourth clock signals from the outside, wherein each stage circuit unit is configured to output gate signals by at least one of the first to fourth clock signals, and to receive gate signals output from an (N+3)th stage circuit unit to thus use as reset signals.

Abstract: A low voltage AC power controller uses a line coupled capacitor AC to DC converter circuit to obtain energy from AC line power supplied to an AC load and may be used with an external high voltage AC switching device to control power supplied to the AC load. The line coupled capacitor AC to DC converter circuit provides a low power device that senses characteristics of the power supplied to the load and can communicate sensed information and/or receive control information related to the power supplied to load.

Abstract: In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.

Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.

Abstract: The system (21) includes: a power transistor (22), a data medium (60) including data relating to the manufacturing tolerance (Tol) of at least one electric parameter of the transistor (22), an electric circuit (26) for controlling the transistor adapted so as to operate for a reference value of the parameter (VREF), an electric circuit (64) having an inductance of less than 100 nH and such that the assembly (70) formed with the circuit (64) and the transistor (22) has a value for the parameter, for which the deviation in absolute with the reference value is strictly less than the manufacturing tolerance (Tol).

Abstract: A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

Abstract: The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

Abstract: A dual pole dual through switch for switching between at least four states. The switch comprises four transistors such as N-channel Metal Oxide Semiconductor transistors, such that at each state at most one transistor is in “on” state, and the others are in “off” state. Each transistor has its own control circuit, which provides zero or negative voltage to the drain of the transistor, positive voltage to the source of the transistor, and control alternating voltage to the gate of the transistor. The switch can be used on-chip for devices. Such devices may include a base station or a handset of a cordless phone.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: A high voltage waveform is generated that is similar to a low voltage input waveform. The high voltage waveform is a series of pulses that are applied directly to the device. An error signal controls the frequency, magnitude, and duration of the pulses. A feedback signal derived from the high voltage waveform is compared with the input waveform to produce the error signal.

Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

Abstract: A charging current is supplied to the gate (control terminal) of a driven switching device during an on-state command interval, for raising the gate voltage to an on-state value. Otherwise, discharging of the gate capacitance is enabled, for decreasing the gate voltage to an off-state value. A second switching device is connected between the gate and a circuit point held at the off-state voltage value, and is maintained in an on state while the gate discharging is enabled. At a first time point, the gate voltage rises above a threshold value. At a second time point, a voltage detection circuit detects that that the gate voltage has risen above the threshold value, causing the second switching device to be set in the off state. It is ensured that the delay between the first and second time points is shorter than a minimum duration of an on-state command interval.

Abstract: A high-side switch control circuit is provided. The high-side switch control circuit includes an on/off transistor, a bias resistor, a zener diode, a level-shifting transistor, and a current source. The on/off transistor operates as a switch. The bias resistor is coupled to turn off the on/off transistor. The zener diode is coupled to clamp the maximum voltage of the on/off transistor. The level-shifting transistor is coupled to turn on the on/off transistor. The current source is coupled to the level-shifting transistor. The current source limits the maximum current of the level-shifting transistor.

Abstract: A switching circuit includes a switching device including the first and second main electrodes and a control electrode; and a driver including: a first rectifying device having an anode terminal connected to the first main electrode of the switching device; a first driving device having a first main electrode connected to a cathode terminal of the first rectifying device and a second main electrode connected to the control electrode of the switching device; a second driving device having a first main electrode connected to the control electrode of the switching device and a second main electrode connected to the second main electrode of the switching device; and input terminals receiving control signals inputted to a control electrode of the first driving device and a control electrode of the second driving device.

Abstract: A first-path connects an input-terminal and an output-terminal of a high-potential-side switching-element and includes a high-potential-side rectifying-device and a high-potential-side passive-element. A second-path connects the output-terminal of the high-potential-side switching-element and the output-terminal of a low-potential-side switching-element and includes a low-potential-side rectifying-device and a low-potential-side passive-element. A high-potential-side applying-unit applies voltage to a connecting point between the high-potential-side rectifying-device and the high-potential-side passive-element. A high-potential-side determining-unit determines that an overcurrent is flowing between the input-terminal and the output-terminal of the high-potential-side switching-element by using a first-value. A limiting-unit limits a current between the low-potential-side rectifying-device and the output-terminal of the high-potential-side switching-element if the overcurrent is flowing.

Abstract: A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity.

Abstract: A drive unit includes a charging unit which charges an opening/closing control terminal of a switching element to switch a drive state. The switching element includes a sensing terminal which outputs a minute current having a correlation with current flowing between input and output terminals of the switching element. The sensing terminal and either of the output terminal or a member having a potential equal to that of the output terminal are connected via a sensing resistor. The drive unit further includes an active gate control unit which changes a charge rate based on comparison of sensing voltage, which is a potential difference across the sensing resistor, or a rate of change of the sensing voltage with a specified value. The specified value is set based on individual-difference information of the switching element which indicates a characteristic, which affects the sensing voltage, when the drive state is switched.

Abstract: A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.

Abstract: An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level.

Abstract: A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.

Abstract: Four energization switching devices and positive/negative switching devices are controlled to form a path charging a positive capacitor; a path connecting a power supply with the positive capacitor in series and energizing an inductor to charge a control terminal of a target switching device; a path charging the control terminal using electromagnetism in the inductor; a path supplying circulating current to the power supply when potential of the control terminal becomes higher than voltage of the power supply; a path charging a negative capacitor; a path connecting the power supply with the negative capacitor in series and energizing the inductor to discharge the control terminal; a path discharging the control terminal using electromagnetism in the inductor; and a path supplying circulating current to the power supply when potential of the control terminal becomes lower than potential of a negative terminal of the power supply.

Abstract: A gate drive circuit capable of turning on a semiconductor switching element at high speed, which includes: a buffer circuit including a turn-on-drive switching element and a turn-off-drive switching element that are complementarily turned on and off, for driving the semiconductor switching element; a first DC voltage supply including a positive electrode connected to the source or emitter of the turn-on-drive switching element and a negative electrode connected to a reference potential; and a second DC voltage supply including a positive electrode connected to the source or emitter of the turn-off-drive switching element and a negative electrode connected to the reference potential.

Abstract: System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch.

Abstract: A driving circuit that drives a semiconductor device includes first to sixth semiconductor devices. A first state and a second state are provided in one cycle in which a voltage is applied to a control terminal of the semiconductor device. In the first state, the first semiconductor device is closed, the third and fourth semiconductor devices are opened, and when the second semiconductor device is structured to have a semiconductor switch, the semiconductor switch is closed. In the second state, the first semiconductor device is opened, and the third and fourth semiconductor devices are closed.

Abstract: A gate driving circuit includes a gate control circuit and a gate voltage limit circuit. The gate control circuit establishes or breaks electrical continuity of a gate voltage supply path from a power source line to a gate terminal of a transistor in response to an on-command and an off-command. The gate voltage limit circuit limits a gate voltage of the transistor to be less than or equal to a first voltage in response to the on-command at least in a period until a determination of whether an electric current greater than a fault criterion value flows to the transistor ends and then limits the gate voltage to be less than or equal to a second voltage.

Abstract: A high voltage semiconductor element and an operating method thereof are provided. The high voltage semiconductor element comprises a high voltage metal-oxide-semiconductor transistor (HVMOS) and a NPN type electro-static discharge bipolar transistor (ESD BJT). The HVMOS has a drain and a source. The NPN type ESD BJT has a first collector and a first emitter. The first collector is electronically connected to the drain, and the first emitter is electronically connected to the source.

Abstract: A gate drive circuit of the present invention is a gate drive circuit for driving an insulated gate switching element, which comprises a control drive circuit for applying a driving voltage to a control terminal of the switching element at a predetermined timing, and a voltage monitoring circuit for monitoring both a first voltage which is a power supply voltage of the control drive circuit and a second voltage which negatively biases the control terminal of the switching element, and in the gate drive circuit, the control drive circuit cuts off an output when at least one of the first and second voltages monitored by the voltage monitoring circuit becomes lower than a threshold value. It is an object of the present invention to provide an insulated gate switching element which can suppress wrong ON.

Abstract: A drive unit comprises a switching circuit and an abnormal signal generating circuit. The switching circuit is configured to be connected to an external time generating circuit, and is configured to switch a driving condition relating to a driving voltage of a voltage-driven element in a transitional period between a driving state and a non-driving state of the voltage-driven element based on a measurement time which is measured by using of the time generating circuit. The abnormal signal generating circuit is configured to generate an abnormal signal when an accurate measurement of the time using the time generating circuit is not executed.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: A method and system that may include a pair of amplifier transistors and an output coupled to a load device. The precharge buffer may be controlled by an activation signal. The precharge buffer may also include a pair of level shifters. Each level shifter may be provided in association with a respective one of the transistors, and each may provide a respective level shift to an input signal at a common signal source based on a reference voltage. Outputs of the level shifters may be coupled to the respective transistors. The precharge buffer may also include a bypass signal path extending from the common signal source to the load device. A signal path may be controlled by another activation signal, and the precharge buffer and the bypass signal may be enabled during mutually exclusive states of the activation signal.

Abstract: A short-circuit protection circuit (12) configured to protect a switching element from an overcurrent includes: a potential decreasing means for decreasing a potential of a gate terminal when a main circuit current is an overcurrent; a feedback means for performing feedback control on an amount of a decrease in the gate potential caused by the potential decreasing means according to a current amount of the main circuit current; and a phase advancing means for performing phase advance compensation in a feedback loop under the feedback control.

Abstract: A drive circuit for a semiconductor switching element is disclosed. The drive circuit includes a power supply, a capacitor, a connection changeover unit for switching a connection form between the power supply and the capacitor, a resistor connected to a control terminal of the semiconductor switching element, first and second switching elements whose common connection point is connected to the resistor, a positive-side diode whose cathode is connected to the first switching element, a negative-side diode whose anode is connected to the second switching element, and a current conduction control circuit for controlling the connection changeover unit, and the first and second switching elements to form (i) a first path for charging the capacitor, (ii) a second path for charging the control terminal of the semiconductor switching element, and (iii) a third path for discharging the control terminal of the semiconductor switching element.

Abstract: A power supply circuit includes a sequence control circuit configured to generate at least one control signal in response to a main power source, a voltage regulator circuit configured to be coupled to the main power source and to selectively generate at least one power supply voltage for a chipset from the main power source in response to the at least one control signal and a discharge circuit configured to discharge the voltage regulator circuit responsive to the at least one control signal.

Abstract: Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

Abstract: A circuit for controlling the switching operation of a transistor is described. A gate driver circuit is operably connected to a control electrode of the transistor and is configured to charge and discharge the control electrode to switch the transistor on and off, respectively, in accordance with a control signal. The charging and discharging of the control electrode is done such that the corresponding transitions in the load current and the output voltage are smooth with a defined slope. A controllable switch is connected to the control electrode such that, when the switch closes, the control electrode is quickly discharged via the switch thus quickly switching off the transistor. A control logic circuit is configured to close the controllable switch for switching off the transistor when at least one of a number of conditions holds true.

Abstract: The present document relates to the control of an external power transistor. In particular, the present document relates to a method and system for avoiding ringing at the external power transistor subsequent to switching of the external power transistor. A driver circuit to generate a drive signal for switching a driven switch between an off-state and an on-state is described. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the driven switch to switch to the on-state; wherein an output resistance of the driver circuit is adjustable; an oscillation detection unit to detect a degree of oscillation on the drive signal; and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

Abstract: A power module (2) includes a first high-side main-circuit MOSFET (21) and a second low-side main-circuit MOSFET (22) connected in series thereto. The series circuit of the MOSFETs (21, 22) is connected in parallel to a power source (4). A first short-circuit MOSFET (25) is connected between the gate and the source of the first main-circuit MOSFET (21). A second short-circuit MOSFET (26) is connected between the gate and the source of the second main-circuit MOSFET (22).

Abstract: A gate driver of a switching element Q1 includes transistors Q2 and Q3 that are totem-pole-connected to both ends of a DC power source Vcc1, transistors Q4 and Q5 that are totem-pole-connected to both ends of a DC power source Vcc2 and have emitters connected to the gate of the switching element Q1, and a transformer T1 having a primary winding and a secondary winding. The primary winding is connected to a collector of one of the transistors Q1 and Q2, and through a capacitor, emitters of the transistors Q1 and Q2. The second winding is connected to bases of the transistors Q4 and Q5 and the emitters of the transistors Q4 and Q5. A maximum duty cycle of a pulse signal is determined according to a primary winding voltage of the transformer and a forward base-emitter voltage of the transistors Q4 and Q5.

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract: A high efficiency driving circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, a first N-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, a current source, a third N-type metal-oxide-semiconductor transistor, a fourth N-type metal-oxide-semiconductor transistor, a fifth N-type metal-oxide-semiconductor transistor, a first resistor, and a second resistor. The first P-type metal-oxide-semiconductor transistor charges a third terminal of the first P-type metal-oxide-semiconductor transistor according to a first control signal, and the first N-type metal-oxide-semiconductor transistor discharges the third terminal of the first P-type metal-oxide-semiconductor transistor according to a second control signal.

Abstract: A dead time generation circuit includes a high-side control signal generation circuit and a low-side control signal generation circuit which are separate circuits. The high-side control signal generation circuit inverts a level of a high-side control signal from a driving prohibition level to a driving permission level when a time corresponding to a first clock number has elapsed in a state where a control signal keeps a first level after the control signal transitions from a second level to the first level. The low-side control signal generation circuit inverts a level of a low-side control signal from the driving prohibition level to the driving permission level when a time corresponding to a second clock number has elapsed in a state where the control signal keeps the second level after the control signal transitions from the first level to the second level.