Abstract: A voltage mode driver circuit includes a plurality of VMD cells and a calibration component. The plurality of VMD cells are configured to generate a calibrated emphasis level according to a calibration signal. The calibration component is configured to determine a voltage dependence effect. Additionally, the calibration component is configured to generate the calibration signal according to the determined voltage dependence effect.

Abstract: A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET.

Abstract: There are provided a driving circuit, a driving module, a motor driving apparatus capable of adjusting a driving current driving a power semiconductor device, the driving circuit including a driving unit including a plurality of drivers and selecting a corresponding driver among the plurality of drivers according to a selection signal to determine a current level of a driving signal for driving a semiconductor device, a timing controlling unit detecting a phase shift time of the driving signal transferred to the semiconductor device and comparing the detected time with a preset reference time to control the phase shift time of the driving signal, and a driving controlling unit providing the selection signal for selecting a driver to be driven among the plurality of drivers of the driving unit according a control signal from the outside and a timing control signal of the timing controlling unit.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

Abstract: Provided is an integrated circuit (IC) having a stacked structure. The IC includes: a first IC having a power input terminal to which a power supply voltage is applied; and a second IC having a power input terminal connected to a ground terminal of the first IC, having a central node formed as the power input terminal of the second IC and the ground terminal of the first IC are connected to each other and to which a voltage is applied, and having a ground terminal connected to a ground source, wherein the power supply voltage is divided into first and second voltages that are respectively applied to the first and second ICs.

Abstract: A switch driving circuit has: a switch signal generator adapted to generate switch signals to complementarily turn on and off switches connected in parallel between a node to which an input voltage is applied and a node to which a ground voltage is applied; drivers adapted to generate gate signals in response to the switch signals; and a dead time setter adapted to set dead times during which the switches are both kept off. At least one of the drivers includes a slew rate setter adapted to vary the slew rate of the gate signals according to a slew rate setting signal. The dead time setter controls to vary at least one of the dead times according to at least one of the slew rate setting signal and the input voltage.

Abstract: A driver circuit includes a driver output stage and an operational amplifier. The driver output stage has a high-level voltage input and a low-level voltage input, and is operable to generate an output voltage responsive to a gate voltage applied to the driver output stage. The operational amplifier is operable to regulate the gate voltage applied to the driver output stage so that the output voltage corresponds to a control signal input to the operational amplifier. A first supply voltage connected to the high-level voltage input of the driver output stage is higher than a maximum value of the control signal, and a second supply voltage connected to the low-level voltage input of the driver output stage is lower than a minimum value of the control signal.

Abstract: A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.

Abstract: A gate driving circuit includes a gate control circuit and a gate voltage limit circuit. The gate control circuit establishes or breaks electrical continuity of a gate voltage supply path from a power source line to a gate terminal of a transistor in response to an on-command and an off-command. The gate voltage limit circuit limits a gate voltage of the transistor to be less than or equal to a first voltage in response to the on-command at least in a period until a determination of whether an electric current greater than a fault criterion value flows to the transistor ends and then limits the gate voltage to be less than or equal to a second voltage.

Abstract: According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: A semiconductor relay of the invention includes first and second signal terminals, a substrate, a first switch circuit and a control circuit. The substrate includes signal patterns for forming a signal line between the first and second signal terminals. The first switch circuit has a semiconductor switch used to make or break the connection between the first and second signal terminals. The control circuit has a control IC for controlling the first switch circuit. The control IC is mounted on a land of the substrate. The land has a size corresponding to the control IC. A part or all of the land is included in a part of the signal patterns.

Abstract: A driving integrated circuit (IC) is disclosed. The driving IC comprises a signal processing circuit, a receiver and a terminal resistance providing circuit. The receiver is coupled to a first transmission line and a second transmission line and is output to the signal processing circuit after receiving a transmission signal through the first transmission line and the second transmission line. The terminal resistance providing circuit is coupled to the receiver.

Abstract: Driver circuitry and methods are provided for driving a semiconductor device. The driver circuitry includes a buck converter configured to generate a baseline current, and a capacitor coupled between an output of the buck converter and ground, the capacitor configured to store charge during an off-state of the buck converter and to discharge the stored charge as a peak current during an on-state of the buck converter, wherein the baseline current reaches a current limit prior to the capacitor being fully discharged, and an output current at an output of the buck converter is based, at least in part, on the baseline current and the peak current.

Abstract: This application discusses, among other things, apparatus and methods for driving the bulk of a high-voltage transistor using transistors having gates with low-voltage ratings. In an example, a bulk driver can include an output configured to couple to bulk of a high-voltage transistor, a pick circuit configured to couple the output to an input voltage at an input terminal of the high-voltage transistor or an output voltage at the output terminal of the high-voltage transistor when the high-voltage transistor is in a high impedance state, and a bypass circuit configured to couple the output of the bulk driver to the output voltage when the high-voltage transistor is in a low impedance state.

Abstract: A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

Abstract: A driving circuit that drives a semiconductor device includes first to sixth semiconductor devices. A first state and a second state are provided in one cycle in which a voltage is applied to a control terminal of the semiconductor device. In the first state, the first semiconductor device is closed, the third and fourth semiconductor devices are opened, and when the second semiconductor device is structured to have a semiconductor switch, the semiconductor switch is closed. In the second state, the first semiconductor device is opened, and the third and fourth semiconductor devices are closed.

Abstract: A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

Abstract: A gate driving circuit is provided which is capable of alleviating the effect of a switching noise generated when an IGBT is turned on/off or a common mode noise on a gate driving signal. The gate driving circuit, a primary side and a secondary side thereof being insulated from each other by a pulse transformer; the primary side of the pulse transformer being grounded to a first ground potential point; the secondary side of the pulse transformer being grounded to a second ground potential point insulated from the first ground potential point; and a gate driving signal generated in a secondary winding of the pulse transformer being outputted through a receiver having impedance matching resistors on the input side, includes an electrostatic shield plate between a primary winding of the pulse transformer and the secondary winding, the electrostatic shield plate being grounded to the second ground potential point.

Abstract: An integrated circuit device can include a plurality of analog circuit blocks, each comprising an input section configured to receive an analog input signal, and an output section configured to drive a plurality of output signals corresponding to the input signal, each output signal having a different maximum drive strength; and a signal network comprising a plurality of switches, and providing a configurable connection between at least outputs of the analog circuit blocks and a plurality of N connections to the integrated circuit device, including less than N direct signal paths between each analog circuit block and the N connections.

Abstract: A circuit utilizes a MOS device in a triode mode of operation and includes a biasing circuit and a MOS device. The MOS device has a drain, a source, and a gate terminal, and is coupled to the biasing circuit. The source terminal, drain terminal, and gate terminal each has a potential and the drain and the source terminals have a resistance. The biasing circuit couples the drain and source terminals of the MOS device to the gate terminal of the MOS device. The biasing circuit couples a DC potential to the gate terminal to adjust the resistance between the source and drain terminals of the MOS device. The resistance between the source and drain terminals is a non-linear function of voltage potentials at the source and drain terminals. The biasing circuit reduces the non-linearity of the resistance between the drain and source terminals by modulating the potential at the gate terminal by a combination of source and drain terminal potentials.

Abstract: Apparatus, systems, and methods are provided for protecting a switching device using a gate driver device. An exemplary gate driver system includes an interface for coupling to a switching device, a desaturation detection arrangement coupled to the interface to detect a desaturation condition based on an electrical characteristic at the interface, and a deactivation arrangement coupled to the interface to deactivate the switching device in a manner that is influenced by the electrical characteristic at the interface. In one embodiment, the switching device is deactivated by providing a deactivation current to a control terminal of the switching device and adjusting the deactivation current based on an electrical characteristic at the interface.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: Exemplary embodiments are directed to a gate drive circuit and a method for controlling a gate-controlled component. The gate drive circuit includes a PI controller that receives an input reference signal (vref,d/dt) controls a gate voltage of the gate-controlled component. The gate drive circuit also includes a first feedback loop for the PI controller adapted to provide feedback from a time derivative of a collector-to-emitter voltage (vCE) of the controlled component. The first feedback loop has a first gain (kv). A second is provided in the gate drive circuit feedback loop for the PI controller that provides feedback from the time derivative of the collector current (iC) of the controlled component. The second feedback loop has second gain (ki) and includes a clipping circuit that modifies the feedback signal in the second feedback loop during turn-on of the controlled component when the time derivative of the collector current is negative.

Abstract: A bootstrap gate driver including a load indication unit, a bootstrap gate-drive unit and a drive-control unit is provided. The load indication unit is configured to generate a load indication signal in response to a state of a load. The bootstrap gate-drive unit is configured to drive a switch-transistor circuit in response to an inputted pulse-width-modulation (PWM) signal, wherein the switch-transistor circuit has a high-side driving path and a low-side driving path. The drive-control unit is coupled to the load indication unit and the bootstrap gate-drive unit, and configured to enable or disable the high-side driving path in response to the load indication signal. In the invention, the operation of the low-side driving path is not affected by enabling or disabling the high-side driving path.

Abstract: To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

Abstract: Bias voltage generators that can generate variable bias voltages for transistors in mixers and other circuits are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit (IC)) includes at least one transistor and a bias voltage generator. The transistor(s) have a threshold voltage and receive a bias voltage. The bias voltage generator generates the bias voltage based on changes to the threshold voltage of the transistor(s), e.g., due to IC process and/or temperature. In an exemplary design, the bias voltage generator includes a replica transistor that tracks the transistor(s) and an op-amp that provides a gate voltage for the replica transistor. The bias voltage is generated based on the gate voltage. The bias voltage generator may generate the bias voltage (i) to track the threshold voltage of the transistor(s) in a first mode or (ii) based on a fixed voltage in a second mode.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: In a driver, a charging module electrically charges the on-off control terminal of the switching element for turning on the switching element, and a limiting module performs a task of limiting a voltage at the on-off control terminal of the switching element by a predetermined voltage to thereby limit an increase of a current flowing between the input and output terminals of the switching element. A determining module determines whether the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage while the limiting module is performing the limiting task. A correcting module corrects the voltage at the on-off control terminal of the switching element to be close to the predetermined voltage when it is determined that the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage.

Abstract: The purpose of this invention is to increase reliability of a switching element while reducing consumption power. In the vertical blanking period, an end pulse signal (ED) changes from the low level to the high level. The potential of first nodes (N1) in the first stage to (m?1)th stage of cascade-connected m-stage bistable circuits included in a shift register of the scanning signal drive circuit is reliably maintained at the low level, and the potential of second nodes (N2) in the first stage to the (m?1)th stage changes from the high level to the low level. In a bistable circuit in the m-th stage, the potential of the first node (N1) in the m-th stage changes from the high level to the low level, and the potential of the second node (N2) in the m-th stage is maintained at the low level. The supply to a bistable circuit of clock signals (CKA, CKB) is stopped.

Abstract: A drive circuit supplies a charging current via a charging path to drive the control terminal of a voltage-controlled switching device, with a resistor and a switching device being connected in series in the charging path. A control circuit in an integrated circuit of the drive circuit operates an internal switching device such as to selectively enable/interrupt the charging current and to regulate the voltage drop across the resistor to a fixed value. The switching device connected in the charging path can be readily changed from the internal switching device to an external switching device, in accordance with the operating requirements of the driven switching device.

Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Abstract: According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.

Abstract: A differential switch drive circuit includes a current source, a current control circuit including a pair of transistors having a pair of differential input terminals, a pair of differential output terminals for outputting differential output voltages, and a common connection node connected to the current source, and load elements each connected to a corresponding one of the pair of differential output terminals. Currents flowing through the pair of transistors are controlled so that the sum of currents flowing through the load elements during a steady state of the differential output voltages is different from the sum of currents flowing through the load elements during a transient state of the differential output voltages.

Abstract: System and method are provided for driving a transistor. The system includes a floating-voltage generator, a first driving circuit, and a second driving circuit. The floating-voltage generator is configured to receive a first bias voltage and generate a floating voltage, the floating-voltage generator being further configured to change the floating voltage if the first bias voltage changes and to maintain the floating voltage to be lower than the first bias voltage by a first predetermined value in magnitude. The first driving circuit is configured to receive an input signal, the first bias voltage and the floating voltage. The second driving circuit is configured to receive the input signal, a second bias voltage and a third bias voltage, the first driving circuit and the second driving circuit being configured to generate an output signal to drive a transistor.

Abstract: A turn-off feedback unit (23OFF) of a semiconductor device driving unit generates a feedback voltage as part of a voltage of a drive signal for establishing electrical continuity or disconnection in a bus according to a temporal variation of a collector current of a first semiconductor device (11U) when the first semiconductor device (11U) is turned off from on. A turn-on feedback unit (23ON) generates the feedback voltage according to a commutation current flowing through a free wheeling diode (12D) connected to a second semiconductor device (11D) when the first semiconductor device (11U) is turned on from off.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a driving signal generator comparing first and second internal voltage signals with lower and upper limit reference voltage signals to generate a pull-up driving signal and a pull-down driving signal, a driver generating a first voltage and a second voltage in response to the pull-up driving signal and the pull-down driving signal, a selecting signal generator comparing the first internal voltage signal with the second internal voltage signal to generate a selection signal, and a selection transmitter that transmits any one of the first and second voltages to the first or second internal voltage signal in response to the selection signal.

Abstract: A gate driving circuit and method can improve the tradeoff relation between the noise and the loss caused in the turn-OFF switching of semiconductor device. The gate driving circuit includes first and second series circuits. The first series circuit includes first and second MOSFETs connected in series. The gate terminal of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of the second MOSFET. The emitter of the semiconductor device is connected to the negative potential side of the second MOSFET or a DC power source. The second series circuit includes a capacitor and a third MOSFET connected in series. The second series circuit is connected in parallel with the second MOSFET. The semiconductor device is turned OFF by turning ON the second and third MOSFETs and turning OFF the first MOSFET.

Abstract: A control circuit for a switch, configured to measure the drain-to-source current of the switch is described. The control circuit is configured to control an external transistor and comprises a control pin coupled to the gate of an external transistor. The external transistor and a level shifting unit are coupled to the control pin and configured to isolate an AC current from the control pin; at a time instant subsequent to the first pulse duration, the isolated AC component of the voltage potential is indicative of a drain-to-source current through the external transistor.

Abstract: A driving circuit outputs an output voltage as a driving signal to the gate of a semiconductor element based on a control signal given from an input circuit. The output voltage is at “H” (ON level) if it is determined by a power supply voltage VCC, and is at “L” (OFF level) if it is determined by a ground voltage GND. A reference power supply section includes a series connection of resistors. The reference power supply section obtains a voltage determined by dividing a potential difference between the power supply voltage VCC and the ground voltage GND by a predetermined dividing ratio (resistance ratio between the resistors) as a reference voltage. A buffer circuit applies an output voltage as a reference signal determined by the reference voltage to the source of the semiconductor element.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.

Abstract: The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.

Abstract: An electronic circuit includes a first transistor device with a control terminal and a load path. A drive circuit includes an input terminal and an output terminal. The output terminal is coupled to the control terminal of the first transistor device. The drive circuit is operable to drive the first transistor device dependent on an input signal received at the input terminal. A polarity detector is coupled in parallel with the load path of the first transistor device. The polarity detector includes a second transistor device and a current detector. The second transistor device includes a load path connected to the load path of the first transistor device. The current detector includes a sense path in series with the load path of the second transistor device and an output connected to the input terminal of the drive circuit.