Abstract: The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.

Abstract: An electronic circuit includes a first transistor device with a control terminal and a load path. A drive circuit includes an input terminal and an output terminal. The output terminal is coupled to the control terminal of the first transistor device. The drive circuit is operable to drive the first transistor device dependent on an input signal received at the input terminal. A polarity detector is coupled in parallel with the load path of the first transistor device. The polarity detector includes a second transistor device and a current detector. The second transistor device includes a load path connected to the load path of the first transistor device. The current detector includes a sense path in series with the load path of the second transistor device and an output connected to the input terminal of the drive circuit.

Abstract: A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch.

Abstract: A gate driver of a switching element includes a first capacitor having a first end connected to a DC power source, a first switch having a first electrode connected to the first end of the first capacitor and a second electrode connected to a negative electrode of the DC power source, a second switch having a third electrode connected to the second electrode and the negative electrode of the DC power source and a fourth electrode connected to the first capacitor, a second capacitor connected in parallel with the third and fourth electrodes of the second switch and having a first end connected to the DC power source, and a negative voltage controller connecting the gate of the switching element to the second end of the first capacitor and a second end of the second capacitor when the switching element is turned off.

Abstract: An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage that is approximately equal to the first voltage.

Abstract: A gate driving circuit and a display, the gate driving circuit comprises a plurality of shift register connected in cascade. The shift register comprises: a signal outputting circuit (32), a signal inputting circuit (31), an inverting circuit (33) and a logic circuit (33). The signal outputting circuit (32) receives a forward direction clock signal from an external circuit and comprises a clock transistor and a level transistor. The signal outputting circuit outputs the forward direction clock signal when the clock transistor is turned on and outputs a constant-low level signal when the level transistor is turned on. The signal inputting circuit (31) receives an output signal from a previous shift register, and turns on the clock transistor when the received output signal of the previous shift register is valid.

Abstract: A data signal voltage on a signal line is held in a voltage holding capacitor through an n-type MOS transistor switched on by a gate scan voltage, and supplied to an analog amplifier circuit. The analog amplifier circuit is formed of an MOS transistor having a double gate structure, and the operating point thereof is set at an operating range in which dependence of Ids on Vds is substantially nullified. Even when Vds is varied due to a response of liquid crystal, Ids is substantially fixed. Accordingly, the pixel voltage which is substantially proportional to the data signal voltage can be applied to the liquid crystal.

Abstract: A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal.

Abstract: A drive circuit is provided for a target switching element and opens/closes a current path by controlling an absolute value of a potential difference between one end of the current path and an opening/closing control terminal. The drive circuit includes an integrated circuit connected to the control terminal. The integrated circuit includes an absolute value control circuit controlling the absolute value of the potential difference when the switching element is in an off-state, a stabilization circuit stabilizing the potential difference at a value for maintaining the switching element in an off-state when the switching element is in an off-state, a selection circuit selecting one of control of the absolute value of the potential difference by the control circuit and stabilization of the potential difference by the stabilization circuit, and an on-state terminal connected to the control circuit and the control terminal. The on-state terminal is connected to the stabilization circuit.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.

Abstract: A clock control device and method are provided. The clock control device includes a stable time controller which receives an operational condition and generates an expiration counting value based on the operational condition; a stable time counter which receives the expiration counting value and activates a clock gating enable signal after a count value of the stable time counter is equal to the expiration counting value; a clock gating cell which transmits a clock signal after receiving the clock gating enable signal; and an oscillator which generates an oscillator clock signal and transmits the oscillator clock signal to the clock gating cell and the stable time counter.

Abstract: A driver for driving a driving element includes: a signal source, for providing a square signal; a first modulation circuit, for providing on-pulses and off-pulses according to edges of the square signal; a transformer for coupling output signals of the first modulation circuit to a secondary winding of the transformer to form coupled signals; a second modulation circuit for providing first operating pulses according to coupled on-pulses of the coupled signals, and providing second operating pulses according to coupled off-pulses of the coupled signals; a switch device for turning off the switch device according to the first operating pulses and turning on the switch device according to the second operating pulses, and when the switch device is turned off, coupled on-pulses charge an equivalent capacitor of the driving element to a first driving potential to turn on the driving element, and when the switch device is turned off, the equivalent capacitor discharges to a second driving potential to turn off the

Abstract: A switching element control apparatus capable of controlling a switching element that is driven by controlling a voltage on its control terminal properly in response to characteristic information of the switching element. The apparatus includes a constant current circuit that applies a constant current to the control terminal, a voltage-limiting circuit that limits the voltage on the control terminal so as not to exceed a limiting voltage, and a control circuit that controls the constant current circuit to apply the constant current to the control terminal when having received a drive signal for turning on the switching element, and controls the voltage-limiting circuit to limit the voltage on the control terminal for a voltage-limiting time period. The control circuit includes a memory storing the characteristic information and variably sets at least one of the limiting voltage, the voltage-limiting time period, and the constant current in response to the characteristic information.

Abstract: A controller for controlling a power chain in an electronic device can be used in either of two different applications. The first application requires the controller to produce drive signals for driving discrete power MOSFETs within the power chain. The second application requires the controller to produce an output PWM signal to control an integrated circuit having power MOSFETs integrated with MOSFET drivers within the power chain. The controller generally includes a sensor that detects which of the two applications the controller is in. The controller also generally includes outputs that produce, when the controller is in the first application, the drive signals for driving the discrete power MOSFETs. But when the controller is in the second application, one of the outputs is used to produce the output PWM signal for controlling the integrated circuit.

Abstract: An apparatus is provided to drive a voltage controlled switching element having a conduction control terminal. In the apparatus, it is determined whether or not voltage at the conduction control terminal is at a first voltage which is lower than a second voltage and which is equal to or more than a threshold voltage. The second voltage is a voltage provided when the switching element is in a normal on-state thereof. The threshold voltage is voltage at which the switching element is switched on. When it is determined that the voltage at the conduction control terminal is at the first voltage, the switching element is forcibly switched off.

Abstract: A semiconductor integrated circuit and an integrated circuit, each of which includes multiple regions containing at least one switchable region to switch between supplying power and blocking power individually; a power supply controller to control switching supplying power and blocking power in the switchable region that switches supplying power and blocking power individually; a power supply variable impedance circuit to change a power supply impedance of the semiconductor integrated circuit; and a power supply impedance controller to obtain the power supplying state of the region from the power supply controller, to cause the power supply variable impedance circuit to change the power supply impedance, based on a supply state of the power in the switchable region.

Abstract: A semiconductor device driving unit to supply a drive signal to a gate of a semiconductor switching device, the semiconductor device driving unit comprising: a plurality of gate impedance circuits selectably connectable to the gate of the semiconductor switching device; and a selector to select one or more of the gate impedance circuits to connect to the semiconductor switching device. Also provided is a method of supplying a drive signal to a gate of a semiconductor switching device, the method comprising: selecting one or more of a plurality of gate impedance circuits to be connected to the gate of the semiconductor switching device based on one or more operating conditions and stored data relating to the one or more operating conditions; and connecting the selected one or more of the gate impedance circuits to the semiconductor switching device.

Abstract: A switching element driver IC has one or more photocouplers, a driver circuit, a detection circuit and a setting circuit. The photocoupler receives setting data transmitted from a microcomputer, and transmits the received setting data to the setting circuit, wherein an input side as a high voltage side is electrically insulated from an output side as a low voltage side in the photocoupler. The setting circuit transmits the setting data to the driver circuit and the detection circuit. The driver circuit and the detection circuit operate on the basis of the received setting data. The setting data can be provided to the driver circuit and the detection circuit through the photocoupler and the setting circuit. This structure makes it possible to suppress increasing the number of terminals at the high voltage side of the switching element driver IC, and decrease the entire size of the switching element driver IC.

Abstract: A high voltage semiconductor device is provided and includes an n?-type region encompassed by a p? well region and is provided on a p?-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p?-region is provided that passes through the n?-type region to the silicon substrate. The n?-type region is divided, by the p?-region, into a drift n?-type region having the drain n+-region and a floating n?-type region having a floating electric potential.

Abstract: According to one or more embodiments of the present invention, a power semiconductor device comprise a plurality of gate electrodes, first to third electrodes, and first to fifth semiconductor layers The second semiconductor layer is formed on the first semiconductor layer. A plurality of the third semiconductor layers are formed in the second semiconductor layer and arranged in a direction perpendicular to the stacking direction. The fourth semiconductor layer is formed on the second semiconductor layer. The fifth semiconductor layer is formed on the fourth semiconductor layer. The gate electrodes are formed above the second semiconductor layer and each gate electrode is arranged between the adjacent third semiconductor layers. The first electrodes are formed below the gate electrodes. One of the first electrodes is connected to the gate electrode. One of the first electrodes is connected to the third electrode.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

Abstract: In a driver, a discharging module discharges, at a discharging rate, the on-off control terminal of a switching element in response to a drive signal being shifted from an on state to an off state. A changing module determines whether a condition including a level of a sense signal being higher than a threshold level during the on state of the drive signal is met, and changes the discharging rate of the on-off control terminal in response to the drive signal being shifted from the off state to the on state upon determination that the condition is met. A loosening module loosens the condition after a lapse of a period since the shift of the drive signal from the off state to the on state in comparison to the condition immediately after the shift of the drive signal from the off state to the on state.

Abstract: A driver circuit includes first switch, configured to selectively couple a first driving node to a power supply node, and a second switch, configured to selectively couple a second driving node to a ground node. The first driving node is coupled to each transistor in a first set of PMOS transistor(s) and the second driving node is coupled to each transistor in a second set of NMOS transistor(s). The driver circuit is configured to propagate a first drive signal in a first direction along an electrical path for biasing the first and second sets of transistors when the transistors in the first set, before receiving the first drive signal, are in a first state. The driver circuit is configured to propagate a second drive signal in a second direction along the path when the transistors in the first set, before receiving the second drive signal, are in a second state.

Abstract: A controller of a drive unit is configured so as to control a voltage supplied to a gate resistor of a voltage-driven element by using of a voltage of a feedback connector when an electrical connection between the feedback connector and the gate resistor of the voltage-driven element is ensured. Further, the controller of the drive unit is configured so as to control the voltage supplied to the gate resistor of the voltage-driven element by using of a voltage of an output connector when the electrical connection between the feedback connector and the gate resistor of the voltage-driven element is not ensured.

Abstract: A switch driving circuit for driving a full-controlled power switch is disclosed, including a pulse-width modulation unit, a pulse transformer, an anti-interference module, a pulse-width demodulation unit and a driving-power amplifier. The pulse-width modulation unit converts a driving input signal into a positive-negative narrow pulse-width signal. The anti-interference module is coupled to the secondary side and the positive-negative narrow pulse-width signal includes multiple positive pulses and negative pulses. The anti-interference module filters out the ones from the positive pulses and negative pulses of which the pulse amplitude does not reach an effective threshold, and meanwhile the anti-interference module suppress a common-mode noise caused by a high voltage transient variation at a moment when the full-controlled power switch is turned on or off. The pulse-width demodulation unit converts the filtered positive-negative narrow pulse-width signal into a driving output signal.

Abstract: A high-voltage driver integratable with an integrated circuit has a switching transistor, a switching diode, a first resistor, a second resistor, and a control transistor. The anode of the switching diode is connected to the source of the switching transistor. The cathode of the switching diode is connected to the gate of the switching transistor. When the source voltage of the switching transistor is far greater than the cut-in voltage of the switching diode, the switching diode is forward-biased, and the gate-source voltage of the switching transistor is equal to the negative cut-in voltage. Accordingly, high voltage will not be generated across the gate-source junction of the switching transistor, no junction breakdown will occur between the gate and source thereof, and the high-voltage driver can be integrated with an integrated circuit.

Abstract: A power module includes an IGBT; a MOSFET connected in parallel with the IGBT; a lead frame having a first frame portion on which the IGBT is mounted and a second frame portion on which the MOSFET is mounted, and having a step by which the first frame portion is located at a first height and the second frame portion is located at a second height larger than the first height; and an insulation sheet for a heat sink which is disposed on an underside of only the first frame portion of the lead frame.

Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.

Abstract: A display apparatus including a gate driving circuit configured to include a plurality of stages connected to each other one after another. An i-th stage of the stages includes an output transistor and a control part. At least one control transistor included in the control part includes a first control electrode to which a switching control signal is applied, and a second control electrode disposed on a layer different from a layer on which the first control electrode is disposed, and to which a reference voltage is applied.

Abstract: A driver circuit has a detector circuit including a high side detection transistor, a resistor, and a low side detection transistor connected to a high side output transistor and a low side output transistor. A clamping circuit converts a high voltage amplitude change signal generated at a connection point of the high side detection transistor and resistor to a signal clamped to a voltage range applied on the low side. An OR circuit outputs a signal taking the logical sum of an inverted control signal and an output of a low side first stage drive circuit. A level shifter circuit outputs a level-shifted signal of the OR circuit to a high side first stage drive circuit. A second OR circuit outputs a signal wherein the logical sum of an output signal of the clamping circuit and the control signal is inverted to the low side first stage drive circuit.

Abstract: The present document relates to a start-up circuit comprising a power switch wherein a circuit charges a supply voltage capacitor. The capacitor provides a supply voltage to a power switch; the power switch forms a switched power converter with a power converter network. The circuit comprises a source and gate interface for coupling the circuit to the power switch; a capacitor interface couples the circuit to the supply voltage capacitor; a start-up path couples the gate interface to the capacitor interface; wherein the startup path provides a voltage at the gate interface which is at or above a threshold voltage of the power switch; and a charging path couples the source interface to the capacitor interface; wherein the charging path provides a charging current to the capacitor interface, when the power switch is in on-state.

Abstract: A method for the repetitive transmission of a signal representing a binary value via a transformer section of a driver of a power semiconductor. Transmitting for the first value a first pulse packet as a sequence of a positive pulse and a negative pulse or for the second value a second pulse packet as a sequence of a negative pulse and a positive pulse to the input of the transformer. The respective pulse packets are repetitively fed to the transformer, one of the first value and the second value is detected at the output of the transformer from the sequence of the polarity of an output variable within a transmitted pulse packet.

Abstract: Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.

Abstract: An electronic device may include a first transistor having a normally-on characteristic; a second transistor connected to the first transistor and having a normally-off characteristic; a constant voltage application unit configured to apply a constant voltage to a gate of the first transistor; and a switching unit configured to apply a switching signal to the second transistor. The first transistor may be a high electron mobility transistor (HEMT). The second transistor may be a field-effect transistor (FET). The constant voltage application unit may include a diode connected to the gate of the first transistor; and a constant current source connected to the diode.

Abstract: A switch-driving circuit suitable for driving a full-controlled power switch combination is disclosed. The switch-driving circuit includes a first pulse-width modulator, a high-voltage isolation pulse transformer module and a plurality of output modules. The high-voltage isolation pulse transformer module includes a magnetic core connected to multiple output modules in a one-to-many way, or includes multiple magnetic cores connected to multiple output modules in a one-to-one way. Each output module includes a second pulse-width modulator and a driving-power amplifier. The full-controlled power switch combination includes a plurality of full-controlled power switches. The driving-power amplifier is coupled between the second pulse-width modulator and one of the full-controlled power switches.

Abstract: A gate drive circuit includes: an input port for receiving a control signal; an output port; a capacitor connected to the output port; a modulation unit which generates (i) a first modulated signal indicating timing of a first logical value of the control signal and (ii) a second modulated signal indicating timing of at least a second logical value of the control signal; a first electromagnetic resonance coupler which wirelessly transmits the first modulated signal; a second electromagnetic resonance coupler which wirelessly transmits the second modulated signal; a first rectifier circuit which generates a first demodulated signal by demodulating the first modulated signal, and outputs the first demodulated signal to the output port; and a second rectifier circuit which generates a second demodulated signal by demodulating the second modulated signal, and outputs the second demodulated signal to the output port.

Abstract: Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer.

Abstract: Provided is a technique that contributes to the improvement of voltage measurement accuracy and uniform current consumption of a battery in a voltage measurement device. Switch circuits (SWP and SWN) include switch elements (MP1 and MP2 or MN1 and MN2) which are provided between an input terminal and an output terminal, and switch driving units (401 to 409) which are driven between a first power supply voltage (VCC or GND) and a second power supply voltage (GND or VCC), which are different from each other, with an input voltage interposed therebetween.

Abstract: To provide a driving method of a semiconductor device for reducing power consumption. In a method for driving a semiconductor device of one embodiment of the present invention, in a first period, a switch configured to control an electrical connection between a first wiring and a second wiring together with an n-channel transistor and a p-channel transistor is in an off state during a period in which the states of the n-channel transistor and the p-channel transistor gates of which are electrically connected to each other are switched between an on state and an off state. In a second period, the switch is set to be in an off state. The switch has a channel formation region in a semiconductor, band gap of which is higher than silicon and intrinsic carrier density of which is lower than silicon.

Abstract: System and method are provided for driving a transistor. The system includes a floating-voltage generator, a first driving circuit, and a second driving circuit. The floating-voltage generator is configured to receive a first bias voltage and generate a floating voltage, the floating-voltage generator being further configured to change the floating voltage if the first bias voltage changes and to maintain the floating voltage to be lower than the first bias voltage by a first predetermined value in magnitude. The first driving circuit is configured to receive an input signal, the first bias voltage and the floating voltage. The second driving circuit is configured to receive the input signal, a second bias voltage and a third bias voltage, the first driving circuit and the second driving circuit being configured to generate an output signal to drive a transistor.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echoes of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: In a driver apparatus for driving a voltage-controlled switching element, an absolute value of a voltage difference between a voltage at a reference terminal that is one of terminals of a current path of the switching element and a voltage at the switching control terminal of the switching element is clamped at a clamping voltage greater than a threshold voltage. A voltage greater than the threshold voltage applied to the switching control terminal allows the switching element to be turned on. When the current flowing through the switching element becomes equal to or greater than a clamp threshold after the switching element transitions from an off-state to an on-state, a voltage-drop-rate at which the absolute value is decreased to the clamping voltage is decreased.

Abstract: A disclosed apparatus includes a converter for receiving a supply and regulating a load. The converter uses a gate driver that is controlled by a controller via a control loop. The control loop controls the converter in response to a feedback signal. The controller is located on a first integrated circuit and the gate driver is located on as second integrated circuit. A process geometry of the first integrated circuit is finer than a process geometry of the second integrated circuit.