Abstract: A driving circuit of a semiconductor optical amplifier type gate switch constituting a matrix optical switch is provided with an operation amplifier into which a driving signal is input and from which a current corresponding to the driving signal is output, an inductance element provided at an output terminal of the operation amplifier, and a circuit composed of a diode element and a resistor element connected in parallel and provided between the inductance element and the semiconductor optical amplifier.

Abstract: A driving circuit of an electrooptic device comprises: a plurality of scanning lines; a plurality of data lines; first and second capacitor lines; a common electrode; pixels, the pixels each including: a pixel switching element; a pixel capacitor; and a storage capacitor; a scanning-line driving circuit; and a capacitor-line driving circuit that shifts the voltage of a first (or second) capacitor line corresponding one scanning line to a predetermined voltage when said one scanning line is selected, and when a scanning line apart from said one scanning line by predetermined number of lines is selected, changes the predetermined voltage by a predetermined value or holds the predetermined voltage; and when said one scanning line is selected; and a data-line driving circuit.

Abstract: A driving circuit includes a plurality of scanning lines, a plurality of data lines, a plurality of capacitor lines, pixels, a scanning line driving circuit, a capacitor line driving circuit, a first capacitive signal output circuit, and a data line driving circuit. Each of the pixels includes a pixel switching element, a pixel capacitor, and a storage capacitor. The capacitor line driving circuit supplies a first capacitive signal to the capacitor line when the one scanning line is selected, and changes a voltage value of the first capacitive signal when a scanning line, located a predetermined number of scanning lines away from the one scanning line, is selected. The first capacitive signal output circuit adjusts and outputs a voltage of the first capacitive signal when the one scanning line is selected. The data line driving circuit supplies the pixels with data signals of voltages corresponding to gray scale levels.

Abstract: First and second current sources are turned ON/OFF according to display data. A first input transistor has a source connected to a first potential, a drain connected to a second potential via the first current source, and a gate, the drain and the gate being coupled together. A second input transistor has a source connected to the first potential, a drain connected to the second potential via the second current source, and a gate which receives a gate voltage of the first input transistor. A first output transistor has a source connected to the first potential, a drain, and a gate receiving the drain voltage of the second input transistor. A second output transistor has a source connected to the second potential, a drain connected to the drain of the first output transistor, and a gate which receives a control signal corresponding to the display data.

Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.

Abstract: When a step-up ratio control circuit sets a step-up ratio of a charge pump circuit to 1.0 to enable a short mode, a path inside the charge pump circuit is short-circuited and a first transistor is completely turned on. This produces an inrush current derived from a battery voltage of a lithium ion battery flowing into the charge pump circuit. To address this, a constant current circuit is operated so that the first transistor is turned on slowly. Further, the operation of an oscillator and an operational amplifier is suspended when the short mode is enabled.

Abstract: An integrated circuit containing a communication channel is described. This communication channel includes a transmit circuit configured to transmit signals using a voltage-mode driver, a receive circuit, and a capacitive link that couples the transmit circuit to the receive circuit. The communication channel includes a filter with a capacitive-summing junction to equalize signals communicated between the transmit circuit and the receive circuit.

Abstract: A pad driver is presented that in one form is capable of driving a wide range of capacitive loads with constant rise and fall times, over a wide range of temperature and process corners. A desirable form of the pad driver is characterized by the ability to charge and discharge rail-to-rail with a constant charging and discharging rate over the whole charging and discharging cycles. Furthermore, desirably the driver is independent of any load present at the output pad.

Abstract: A buffer circuit includes an input terminal operable to receive an input signal and an output terminal at which an output signal for the buffer circuit is provided. In the buffer circuit, three transistors at most provide signal currents. Two of the three transistors can be matched. Means are provided for feeding back the output signal so that the two matched transistors are balanced in response to a change in the input signal appearing at the input terminal.

Abstract: A data output driver and a semiconductor memory device having the same are disclosed.

Abstract: A driver for a switching device has a plurality of driver circuits for driving the switching device and a control circuit. The control circuit selectively operates the driver circuits in response to a plurality of predetermined drive modes. Alternatively, a driver for a switching device has a driver circuit and a control circuit. The driver circuit is connected to a plurality of power sources. Each of the power sources has a different voltage. The control circuit selects one of the power sources for operating the driver circuit in response to a plurality of predetermined drive modes.

Abstract: A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Abstract: The invention provides a semiconductor device which performs a write operation of a signal current rapidly to a current input type pixel. Before inputting a signal current, a precharge operation is performed by flowing a large current. After that, a signal current is inputted to perform the set operation. A predetermined potential can be obtained rapidly as the precharge operation is performed before the set operation. The predetermined potential is approximately equal to a potential after completing the set operation. Therefore, the set operation can be rapidly performed and a write operation of a signal current can be rapidly performed. By using two transistors, a gate width W can be long or a gate length L can be short in the precharge operation or the gate width W can be short and the gate length L can be long in the set operation.

Abstract: A voltage source converter with a line-side diode rectifier, a load-side inverter with an electronic circuit, a power supply for the electronic circuit, and a slim DC link with a DC link capacitor is described. The slim DC link connects a DC output side of the line-side diode rectifier with a DC input side of the load-side inverter. A buffer capacitor is connected across the power supply, and a decoupling diode and a current limiting circuit are electrically connected in series with the buffer capacitor. The serially connected buffer capacitor, decoupling diode and current limiting circuit are connected in parallel with the DC link capacitor. This arrangement results in a voltage source converter that has an improved service reliability even in unstable power grids, without adding circuit complexity to the line input.

Abstract: A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

Abstract: An apparatus and method of the present invention includes a high frequency exclusive OR (XOR) with a peaked load stage. The peaked load stage coupled to the XOR produces a peaked response at a specified frequency of operation. The high frequency XOR comprises a mixer stage comprising first and second transconductance stages coupled to produce a differential output current. The peaked load stage receives the differential output current from the mixer stage and provides increasing impedance at a specified frequency of operation. The peaked load stage includes a pair of peaked load blocks comprising a saturation region peaked load MOSFET and a resistive load. The gate-to-source capacitance of the peaked load MOSFET is coupled to the resistive load to form a high pass filter that provides additional bias to a gate of the peaked load MOSFET that increases the resistance of the peaked load MOSFET at the specified frequency.

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution include a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each signal line that isolates the signal line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state. This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary lines.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

Abstract: An electronic logic driver circuit, for driving a capacitive load between supply potentials for example for use in driving logic circuit elements on or off a chip, is disclosed. The driver circuit comprises switching devices to switch current either to or from two main voltage supply sources and two coupled inductors that act to store energy derived from the voltage sources. In operation, the coupled inductors form an LC resonator with the load such that energy stored in the inductors can be transferred to or from the load to drive a change in the voltage of the load.

Abstract: A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line, and it delivers a switching signal to an output terminal. A first set of signals delivered to the control terminals of the multiplexer causes the charge reservoir to deliver charge to the output terminal, and a second set of signals delivered to the control terminals causes charging of the charge reservoir. With the charge reservoir, charge from falling signals is conserved and used to help rising signals at the output, reducing the power required to provide an output switching signal.

Abstract: A charge pump including a differential pair of transistors for controlling a current at a charge pump output node and a replica bias generator for selectively driving a first transistor of the differential pair of transistors into a fully-on state and a second transistor of the differential pair of transistors into a weak inversion state.

Abstract: Programmable differential capacitance is implemented in equalization circuits. The programmable differential capacitance improves the common mode rejection ratio of circuits processing differential signals of various frequencies and voltage swings. Multiple capacitance devices provide the programmable capacitance, which provides an equalization circuit with different, selectable (i.e., programmable) values of capacitance for boosting the transition speed and strength of differential signals processed by the equalization circuit.

Abstract: A high voltage AC power supply circuit for a capacitive load CL, such as an electroluminescent lamp, includes a low voltage DC supply, an inductor L and a FET S in series. The FET S can be pulsed so that the inductor L generates a voltage to charge the capacitive load CL via an H-bridge H, which is in parallel with the FET S. A diode D prevents current discharging from the capacitive load CL while the FET S is closed. The total capacitance downstream of the diode D and in parallel with the capacitive load CL is less than the capacitive load CL, so that when the polarity of the H-bridge is reversed, the voltage across the H-bridge collapses to earth and the capacitive load CL is discharged via the low voltage DC supply. The circuits which a employ a large smoothing capacitor in parallel with the H-bridge.

Abstract: An energy recovery apparatus including a sustaining voltage source for applying a sustaining voltage to a first electrode and a second electrode formed on an upper substrate; a equivalent capacitive load formed between the first electrode and the second electrode; and a power source capacitor disposed between the sustaining voltage source and a ground voltage source, for being charged with a voltage charged in the equivalent capacitive load and preventing a voltage drop phenomenon when a voltage of the sustaining voltage source is applied to the equivalent capacitive load.

Abstract: A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the transducer and a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET's threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed. The control circuit reduces switching time and reduces current spikes in the power supplies to the chip.

Abstract: An output buffer includes an output stage that includes a transconductance device configured to drive a capacitive load, and a first capacitor coupled to an input of the transconductance device. A converter converts an input clock signal into a current that is provided to charge the first capacitor during a specified interval. The converter includes a feedback loop to adjust the current so as to produce a specified logic level at the specified interval. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at least one predetermined format. The apparatus includes: (a) at least one input locus coupled with each input channel for receiving the signals; (b) at least one output locus for presenting selected communication signals in a desired format in at least one output channel; and (c) a plurality of treating circuits for treating the signal excursions in a plurality of formats that include the predetermined format and the desired format. Each treating circuit is coupled with at least one respective input locus and at least one respective output locus. The apparatus presents sufficiently low capacitance between input loci and output loci to impart substantially zero time delay to the communication signals.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: Drive circuitry for capacitive displacement transducers includes an oscillator, a precision low noise voltage reference with added noise reduction circuitry, a synchronous demodulator consisting of a single pole double throw analog switch, one or more transducer electrode drive signals generated by one or more additional analog switches, and feedback circuitry to modify the amplitude of the electrode drive signal based on the circuit output signal, to improve the accuracy of the output signal.

Abstract: A power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver includes an upper transistor and a lower transistor provided in a half-bridge configuration. The output node of the gate driver is provided between the upper and lower transistors. A first delay circuit is coupled to a control terminal of the upper transistor to provide a first delay period for a first gate drive signal being applied to the control terminal of the upper transistor. A second delay circuit is coupled to a control terminal of the lower transistor to provide a second delay period for a second gate drive signal being applied to the control terminal the lower transistor. The first delay period is different from the second delay period.

Abstract: Phase locked loop charge pump comprising a drain node (A, B) and at least a cascode transistor (M4, M6) for limiting the variation of the voltage of said drain node, characterized in that an intermediate switch transistor (M3, M5) is placed between the drain node (A, B) and the cascode transistor (M4, M6).

Abstract: The present invention provides an energy recovering driver that includes a pull-up control, a pull-down control and a transmission gate. The pull up control is responsive to a pull-up control signal and a clock signal to turn the transmission gate ON and OFF and predetermined positions of the clock signal. The pull-down control is responsive to a pull-down control signal and the clock signal to turn the transmission gate ON and OFF at other predetermined locations of the clock signal. The transmission gate transmits the clock signal when at an ON condition and does not transmit the clock signal when in an OFF condition.

Abstract: A driver circuit for switching an output voltage (Vout) at an output terminal 3 by using diode bridges 1 and 2 includes a first current mirror circuit 10 for letting flow a first balance current I2e and letting flow a first transition current I2f obtained by adding a first stationary current to a product of the first balance current I2e and a predetermined multiplier when switching from the low level to the high level, and a second current mirror circuit 20 for letting flow a second transition current I2h obtained by adding a second stationary current to a product of the second balance current I2g and a predetermined multiplier when switching from the high level to the low level. As a result, the power dissipation in the stationary state is reduced without lowering the slew rate at the time when switching the output voltage.

Abstract: Programmable differential capacitance is implemented in equalization circuits. The programmable differential capacitance improves the common mode rejection ratio of circuits processing differential signals of various frequencies and voltage swings. Multiple capacitance devices provide the programmable capacitance, which provides an equalization circuit with different, selectable (i.e., programmable) values of capacitance for boosting the transition speed and strength of differential signals processed by the equalization circuit.

Abstract: A current switching circuit has greatly reduced charge injection effects with the introduction of a mirror path to mirror the switch path. The mirror path comprises a complementary switch and a pulling amplifier, e.g., a pull-down amplifier for a source current switching circuit, or a pull-up amplifier for a sink current switch circuit. The pulling amplifier mirrors the status of an output path of a current source, e.g., a transistor current source, such that when the current source is switched ON or OFF, the switching process with respect to the load, e.g., a load capacitor, is smooth and provides a clean current waveform due to greatly reduced charge injection.

Abstract: A buffer circuit includes a resonant circuit. An output of the resonant buffer circuit transitions once for three transitions on an input.

Abstract: The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other.

Abstract: A bi-directional charge driver circuit provides an output voltage that may be increased or decreased according to two control signals. When the output voltage is configured as an adjustable reference voltage, the adjustable reference voltage may be varied in selectable increments to obtain a desired reference voltage. Alternatively, when the bi-directional charge driver circuit is configured as a digital-to-analog converter, the two control signals are given by a logic circuit in response to two digital input signals. The two digital input signals are converted by the bi-directional charge driver circuit to the analog output voltage.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching.

Abstract: An improved relaxation oscillator circuit is provided using conventional CMOS device shunted with a current source (101 and 103) at each load of two cross-coupled gain stages. The improved oscillator uses a clamp voltage reference (134), to control the voltage swing across the charging/discharging capacitor (118). The improvements provide improved speed to power ratio, increased frequency tuning range, and less process and temperature variation effects. A transistor (130) and current source (138) replicate output transistors (110, 114) and current sources (101, 103). An amplifier (132) receives a clamp voltage reference (134) and current from the transistor (130) and current source (138) and functions to provide necessary drive currents to the gates of transistors (110, 114) which drive the outputs (VOR, VOL).

Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

Abstract: An output driver circuit that can be used to determine whether a repeater buffer is the only device driving a bus low. According to the invention, the current through the output driver circuit of the repeater buffer is compared with a reference current. If that current is greater than the reference current, then the output driver circuit (i.e., the repeater buffer) is the only output driving the bus low. On the other hand, if that current is less than the reference current, then the output driver circuit (and thus the repeater buffer) is not the only device driving the bus low. This information can be used in an I2C repeater to determine the proper response of the repeater and prevent a latch condition.

Abstract: A driver circuit includes a follower transistor and a first switch connected serially between an output terminal and a first power supply, a first current source and a second switch connected serially between the output terminal and a second power supply, and a bias control device for supplying the follower transistor with an input bias voltage based upon an input signal voltage. The first switch is turned on at one timing in a data output interval, thereby causing the transistor to perform a follower operation to drive the output terminal voltage to the vicinity of a certain voltage defined in conformity with the input signal voltage, the second switch is turned on at a timing subsequent to the one timing, thereby placing both the first and second switches in the ON state, and the output terminal voltage is driven to the certain voltage, which is defined in conformity with the input signal voltage, from the subsequent timing onward.

Abstract: A field effect transistor used in radio frequency switching applications and having a linear performance characteristic is disclosed. The transistor comprises a plurality of gate lines, a source terminal, a drain terminal, and two feed forward capacitors electrically coupled to the source and drain terminals and the gate line at a plurality of points along the line. An improved transistor preferably includes three or more gate lines to help improve harmonic suppression.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

Abstract: An improved method and apparatus for active line termination is disclosed. An active termination line driver (ATLD) includes a pair of power amplifiers configured to amplify a transmit signal, the amplifiers comprise a first input for receiving the transmit signal, a second input for receiving a feedback signal, and an output configured to provide the amplified transmit signal to the load. The ATLD also includes a resistive network configured to provide the feedback signal from the outputs of the amplifiers to the second inputs power amplifiers. The resistive network is selectively configured to facilitate any one of a plurality of feedback configurations to emulate a back-matching impedance. Other embodiments of the present invention may be construed as methods for power efficiently driving a transmit signal to a load.

Abstract: Provided are a source follower circuit having a current source having its improved current characteristics, laser driving apparatus, semiconductor laser apparatus, current-voltage conversion circuit, and light receiving circuit. Each of the laser driving apparatus, semiconductor laser apparatus, current-voltage conversion circuit, and light receiving circuit comprises the source follower circuit. The source follower circuit 10 comprises a source follower stage 12 and a bias stage 14. The source follower stage has III-V compound semiconductor transistors 16, 18 and 20. The bias stage 14 has a first node 22 for providing a first bias voltage and a second node 24 for providing a second biasing voltage different from the first biasing voltage. The gate of transistor 16 is coupled to input 26 and a source thereof is coupled to output 28. The gate of transistor 18 is connected to the second node 24. The gate of transistor 20 is connected to the first node 24.

Abstract: A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.

Abstract: A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal.