Abstract: A heterodyne dual-slope frequency generation method for the load change of the power supply, which comprises a power transformer, a feedback control circuit, and a dual-slope charge-discharge circuit. The power supply generates different charge current to fit different operating mode through the feedback control circuit, feedback voltage generated into power transformer, and passes through the dual-slope charge-discharge circuit in accordance with the different outer load device and the different outer voltage rising speed. When the outer loading is changed, the feedback control circuit detects error voltage, feeds through power transformer, further changes the supplied current, and finally automatically adjusts the driving current and the output power.

Abstract: The present invention provides a circuit for driving a display panel using a driving capacitor, comprising an analog-to-digital converter receiving an analog input signal to generate a digital signal, a driving capacitor receiving the digital signal to generate a driving signal for the display panel, and a switching circuit in response to a switching signal, selectively coupling the analog-to-digital converter to the driving capacitor for transmission of the digital signal and coupling the driving capacitor to the display panel for transmission of the driving signal. Thus, the circuit area needed for a source driver processing images of large bit number is reduced, which decreases the cost. Further, the power system of the display having a large dynamic range of voltage can be also simplified.

Abstract: A capacitive load driver includes a first switching element whose first end receives positive potential, an EL element arranged between a second end of the first switching element and the ground, a charge collecting capacitor whose first end is connected to a positive electrode terminal of the EL element, a voltage source connected between a second end of the charge collecting capacitor and the ground, and a controller. The controller charges a parasitic capacitance of the EL element and the charge collecting capacitor, and thereafter, applies negative potential from the voltage source to the second end of the charge collecting capacitor. Thereafter, the controller brings the output voltage of the voltage source to ground potential so that the charge collecting capacitor is discharged to charge the EL element. The capacitance of the charge collecting capacitor is set to be sufficiently greater than that of the parasitic capacitance.

Abstract: A method for feeding DC power to an amplifier module for a pulsed load, the method comprising providing current pulses from a DC power supply; charging a capacitor configuration in the amplifier module; providing an output voltage via a voltage regulated power supply; feeding current pulses to the pulsed load from the capacitor configuration, determining an output current (Iout) pulse configuration appearing during feeding the load from the capacitor configuration; providing a pulsed input current (Iin) from the DC power supply based upon the determined output pulsed current; and limiting the maximum current level of the input current pulses to a pre-determined level by a control and pulse shaping circuit to be substantially lower compared to the peak current of the output current pulses.

Abstract: A drive waveform signal is pulse-modulated and a modulated signal is generated, the obtained modulated signal is power-amplified, and then, a drive signal is demodulated using a low pass filter. Thus obtained drive signal is negatively fed back, and thereby, the resonance peak of the low pass filter is suppressed. In this regard, by bringing gain in a wider frequency domain to take a fixed value or more, a drive signal having a voltage exceeding a power supply voltage may be stably generated.

Abstract: A driving circuit of a semiconductor optical amplifier type gate switch constituting a matrix optical switch is provided with an operation amplifier into which a driving signal is input and from which a current corresponding to the driving signal is output, an inductance element provided at an output terminal of the operation amplifier, and a circuit composed of a diode element and a resistor element connected in parallel and provided between the inductance element and the semiconductor optical amplifier.

Abstract: A low drop out voltage regulator (LDO) is capable of operating in one of two different modes based on externally connected components. In one mode, the LDO directly generates a regulated output voltage. In a second mode, the LDO drives an external PNP transistor to generate a regulated output voltage. In both modes, a relatively large bypass capacitor may be connected to the output voltage node to bypass high-frequency loading on the output voltage node. However, the bypass capacitor creates a low frequency pole in the frequency response of the LDO, which can diminish phase margin and reduce overall stability. An on chip compensation network beneficially counteracts the low frequency pole with an appropriately placed zero, thereby resulting in improved phase margin and greater stability.

Abstract: A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.

Abstract: A transmission driver including a main driving stage and a sub-driving stage is provided. The main driving stage has a main current source, and is adapted for receiving a first differential input data stream and outputting a differential output data stream by using the main current source. The sub-driving stage has two sub-current sources, and is adapted for receiving a second differential input data stream and counteracting/reducing the attenuation or distortion of the differential output data stream caused by a long transmission distance by using the sub-current sources. There is a delay of a specific bit length between the first and the second differential input data streams.

Abstract: A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit.

Abstract: As part of a transmitter and receiver system a droop compensator is provided between the channel isolation device and the driver system to compensate for reduced transition densities. The droop compensator is configured to improve power transfer to the channel in response to reductions in transition density without affecting power transfer during periods of high transition density. The droop compensator creates an impedance mismatch between the matching circuit and driver in relation to the line impedance. The droop compensator may comprise passive elements, such as capacitors, inductors, or resistor, or active elements including transistors or power control modules. The droop compensator may be configured to operate with transformer line couplers or capacitor line couplers, and either current drivers or voltage drivers.

Abstract: A capacitive load driving device includes a drive waveform generator that generates a drive waveform signal, a subtractor that outputs a difference signal between the drive waveform signal and a feedback signal, a modulator that pulse-modulates the difference signal to output a modulated signal, a digital power amplifier that amplifies the modulated signal to output an amplified digital signal, a low pass filter that smoothes the amplified digital signal to output a drive signal for a capacitive load, a feedback circuit that outputs the feedback signal obtained from the drive signal, and an adjusting section that adjusts frequency characteristics of the feedback circuit based on capacitance of the capacitive load to be driven.

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A capacitive load driving circuit includes: a drive waveform signal generator that generates a drive waveform signal; a subtractor that outputs a differential signal between the drive waveform signal and a feedback signal; a modulator that pulse-modulates the differential signal and outputs a modulated signal; a digital power amplifier that amplifies the power of the modulated signal and outputs a power-amplified modulated signal; a smoothing filter that smoothes the power-amplified modulated signal, and outputs a drive signal of the capacitive load; a compensator that causes a phase to precede the drive signal; and an attenuator that attenuates signal amplitude in a band at least including a modulation frequency of the modulated signal. A signal output from a connecting point between the inductor and the wire is made to pass through the compensator and the attenuator and is then used as a feedback signal to the subtractor.

Abstract: A capacitive load driving device includes a drive waveform generator adapted to generate a drive waveform signal, a subtraction section adapted to output a differential signal between the drive waveform signal and two feedback signals, a modulator adapted to perform pulse modulation on the differential signal to obtain a modulated signal; a digital power amplifier adapted to power-amplify the modulated signal to obtain an amplified digital signal, a low pass filter including an inductor and a capacitor, and adapted to smooth the amplified digital signal to obtain a drive signal of a capacitive load, a first feedback circuit adapted to feedback the drive signal to the subtraction section as a first feedback signal, and a second feedback circuit adapted to set forward a phase of the drive signal and to feed back the drive signal to the subtraction section as a second feedback signal.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

Abstract: A DC-DC converter in which self turn-on can be prevented and can improve power efficiency. In a non-insulated DC-DC converter, self turn-on is prevented by applying a negative voltage between a gate and a source of a low side MOSFET by the use of a capacitor for generating negative voltage when the low side MOSFET is in an OFF state. Also, when the low side MOSFET is in an ON state due to the capacitor for generating negative voltage, a positive voltage applied between the gate and the source of the low side MOSFET does not drop from a voltage of a gate driving DC power source that is supplied from a gate power input terminal. Therefore, the power efficiency is improved.

Abstract: A source driver, which has a first resistor string, a first digital-to-analog converter, and a channel buffer, is provided. The first resistor string has a plurality of resistors connected in series, wherein each of the resistors of the first resistor string provides a corresponding gamma voltage. The first digital-to-analog converter is coupled to the resistors of the first resistor string. The digital-to-analog converter selectively outputs one of gamma voltages provided by the resistors as a first output voltage according to a data code. The channel buffer is coupled to an output terminal of the first digital-to-analog converter to output a second output voltage by shifting a voltage level of the first output voltage.

Abstract: Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.

Abstract: The invention provides a multichannel drive circuit by which, even when there occurs a variation between channels in circuit characteristics of each channel including current source due to the semiconductor manufacturing process and the like, loads of each channel constituting a load array can be driven under conditions uniform between all the channels. The invention includes; an interchannel common connection line (5) for making conduction between respective current paths of each channel for connecting the respective current sources of each channel constituting a current source array (11) with respective input switches of each channel constituting an input switch array (13); and current blocking means (12) for blocking output current of the current source of that channel of the plurality of channels in which the input switch is in an OFF state from flowing into the interchannel common connection line.

Abstract: A bus modem for building and industrial electrical systems comprises a module (100) which comprises a pair of input pins (1, 2) destined to be connected to the bus and a pair of output pins (9, 10) destined to be connected to the electrical circuit of a device to be connected to the bus. The module (100) further comprises a voltage control circuit (3) able to take voltage from said bus and to control the voltage (VASB) on a capacitor (C1) disposed at the terminals of said output pins (9, 10), and a transmission control circuit (5) able to control an electronic switch (7) which controls a current limiting circuit (8) able to limit the current on the bus, during transmission of signals from the bus to the devices connected to the bus and vice versa.

Abstract: A method, circuit configuration and bridge circuit for charging a capacitance effective on the main current terminals of a semiconductor switch, in particular an intrinsic capacitance, in particular the drain-source capacitance of a MOSFET semiconductor switch or the collector-emitter capacitance of an IGBT semiconductor switch, the precharging, in particular the at least partial charging, of the effective capacitance being forcibly controlled via a charging current path.

Abstract: A capacitive load driver includes a first switching element whose first end receives positive potential, an EL element arranged between a second end of the first switching element and the ground, a charge collecting capacitor whose first end is connected to a positive electrode terminal of the EL element, a voltage source connected between a second end of the charge collecting capacitor and the ground, and a controller. The controller charges a parasitic capacitance of the EL element and the charge collecting capacitor, and thereafter, applies negative potential from the voltage source to the second end of the charge collecting capacitor. Thereafter, the controller brings the output voltage of the voltage source to ground potential so that the charge collecting capacitor is discharged to charge the EL element. The capacitance of the charge collecting capacitor is set to be sufficiently greater than that of the parasitic capacitance.

Abstract: A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance.

Abstract: In one embodiment, a charge pump controller is configured with transistors having at least two different selectable on-resistance values may be used to charge a pump capacitor.

Abstract: Disclosed herein is a shutter drive unit, including: at least one inductor; first and second drive paths; first and second shutter including first and second drive object capacitive loads, respectively; first and second clamping circuits adapted to clamp the first and second drive object capacitive loads either to a power source potential or to a reference potential through the first and second drive paths, respectively; a first switch adapted to switch connection and non-connection between the inductor and the first drive object capacitive load over to each other; a second switch adapted to switch connection and non-connection between the inductor and the second drive object capacitive load over to each other; and a power collecting portion having a function of applying an intermediate voltage between the power source potential and the reference potential to the inductor, and a power collecting function of collecting a power by the inductor.

Abstract: A driving circuit of a semiconductor optical amplifier type gate switch constituting a matrix optical switch is provided with an operation amplifier into which a driving signal is input and from which a current corresponding to the driving signal is output, an inductance element provided at an output terminal of the operation amplifier, and a circuit composed of a diode element and a resistor element connected in parallel and provided between the inductance element and the semiconductor optical amplifier.

Abstract: A non-inverting AC/DC input buffer combines the desirable characteristics of an alternating current (AC) input buffer including low delay, high speed, and high input voltage swing range with the desirable characteristics of a direct current (DC) input buffer including stability, reliability, and ‘automatic’ high and low data setup. The AC/DC buffer includes logic to help prevent the DC input buffer from interfering with the AC input buffer until the DC input buffer has completed its operations on a transitioning input. The DC buffer is configured to enable the AC buffer to process low input voltage swings such as, for example, voltage swings less than the difference in power supply voltages.

Abstract: A voltage driver circuit includes a first transistor. The first transistor includes a control terminal, a first terminal, and a second terminal. The second transistor includes a control terminal, a first terminal, and a second terminal. A first current source configured to provide a first bias current to the control terminal of the first transistor. A second current source configured to provide a second bias current to the control terminal of the second transistor. The first resistance includes a first terminal connected to the control terminal of the first transistor. The second resistance includes a first terminal connected to the control terminal of the second transistor. A capacitance connects the second terminal of the first transistor with the control terminal of the second transistor. A ratio of the first bias current to the second bias current is approximately equal to a ratio of the second resistance to the first resistance.

Abstract: A driving circuit that drives a capacitive load includes a drive signal generator that generates a drive signal driving the capacitive load via a transistor pair in response to an analog signal, and a power-source voltage generator that generates a high-voltage power-source voltage and a low-voltage power-source voltage and that supplies the high-voltage power-source voltage and the low-voltage power-source voltage respectively to collectors of the transistors of the transistor pair via a high-voltage output terminal and a low-voltage output terminal. The power-source voltage generator includes multiple power sources connected in parallel, a backcurrent prevention diode connected between the adjacent power sources, and a switch unit that connects the adjacent power sources in series under the on-off control of a controller each time the drive signal rises above a predetermined threshold value or falls below a predetermined threshold value.

Abstract: A capacitive load driving circuit that drives a capacitive load, includes: a power supply unit that generates different voltages; a plurality of charge storage elements that are charged with the different voltages generated by the power supply unit; and a load driving section that connects a charge storage element arbitrarily selected from the plurality of charge storage elements to the capacitive load to drive the capacitive load, and connects, when at least two of the charge storage elements are selected, the at least two charge storage elements to the capacitive load in a state where the at least two charge storage elements are connected in series.

Abstract: A voltage buffer may include a first signal path extending from an input terminal to an output terminal in which the first signal path further may include a buffer transistor that may have a control terminal, and a first and second current terminals responsive to the control terminal. In the first signal path, the control terminal may be connected to the input terminal, the first current terminal may be connected to the output terminal, and the first signal path may supply a load current to a load device responsive to an input signal at the input terminal. The voltage buffer further may include a second signal path extending from the input terminal to a current source node. The second signal path may include a replica load device. The voltage buffer further may include a current source supplying substantially constant current and coupled to the current source node.

Abstract: The invention reduces power consumption, reduces EMI, and produces a stable sustain discharge. The sustain pulse generating circuit includes a power recovery circuit, clamping circuit, and auxiliary circuit. The power recovery circuit has a recovery inductor for LC resonance and a recovery capacitor for power recovery, recovers power stored in the capacitive load of the display electrode pairs to the recovery capacitor by LC resonance, and reuses the recovered power to drive the display electrode pairs. A clamping circuit clamps the display electrode pairs to the supply potential and the ground potential. An auxiliary circuit has an auxiliary capacitor connected in series with the recovery capacitor, and an auxiliary inductor that is used for LC resonance with the auxiliary capacitor, and increases the current flowing to the recovery inductor at the sustain pulse rise and fall to greater than the current that flows only as a result of the LC resonance of the recovery inductor and the capacitive load.

Abstract: A driving circuit for a capacitive load includes a driving signal generating unit that generates a driving signal for driving the capacitive load by using a pair of driving transistors. A power source voltage generating unit generates high-voltage and low-voltage power source voltages that are higher and lower, respectively, than the voltage of the driving signal and applies the voltages to collectors of the driving transistors. The power source voltage generating unit includes a pair of power source transistors and a capacitor. The low-voltage power source voltage is generated in an output side of the power-source transistor pair as a voltage that is in a voltage region lower than that of the driving signal and follows the driving signal. The high-voltage power source voltage is output from a high-voltage terminal of the capacitor, is in a voltage region higher than that of the driving signal, and follows the driving signal.

Abstract: A driving circuit that drives a capacitive load includes a drive signal generator that generates a drive signal that drives the capacitive load via a transistor pair in response to an analog signal. A power-source voltage generator generates high-voltage and low-voltage power-source voltages and supplies the power-source voltages to collectors of the transistors via a high-voltage output terminal and a low-voltage output terminal. The power-source voltage generator includes multiple power sources connected in parallel and a switch unit that connects the adjacent power sources in series each time the drive signal rises above or falls below a predetermined threshold value. The driving circuit further includes a voltage controlling capacitor connected to the low-voltage output terminal of the power source, and a power recovery unit having a switch unit that recovers a charge accumulated in the voltage controlling capacitor back to the power source via the high-voltage output terminal.

Abstract: A driving circuit of a semiconductor optical amplifier type gate switch constituting a matrix optical switch is provided with an operation amplifier into which a driving signal is input and from which a current corresponding to the driving signal is output, an inductance element provided at an output terminal of the operation amplifier, and a circuit composed of a diode element and a resistor element connected in parallel and provided between the inductance element and the semiconductor optical amplifier.

Abstract: A capacity load drive device 1 includes: a logic portion 11 generating a binary logic signal IN; and a driver portion 13 determining, based on a predetermined mode switching signal MODE, whether to generate a binary drive signal or ternary drive signal from the logic signal IN and applying binary or ternary drive signals X1 to Xm generated according to the determination, to an end of a capacity load (liquid crystal cell).

Abstract: A power switch assembly for a capacitive load 10 which includes a common electrode 14 and first and second discrete electrodes 16, 18, includes a node n1 coupled to a voltage source Vcc for receiving power there from, a first switching device connected between the node n1 and ground, a second switching device connected between the node n1 and ground, and a dividing circuit connected between the node and ground. The dividing circuit includes an output terminal connected to the common electrode 14 of the capacitive load. The first switching device is coupled to the first electrode 16 of the capacitive load configured to control movement of the capacitive load 10 in a first direction. The second switching device is coupled to the second electrode 18 of the capacitive load configured to control movement of the capacitive load 10 in a second direction reverse to the first direction.

Abstract: An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

Abstract: A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.

Abstract: The present invention provides a circuit for driving a display panel using a driving capacitor, comprising an analog-to-digital converter receiving an analog input signal to generate a digital signal, a driving capacitor receiving the digital signal to generate a driving signal for the display panel, and a switching circuit in response to a switching signal, selectively coupling the analog-to-digital converter to the driving capacitor for transmission of the digital signal and coupling the driving capacitor to the display panel for transmission of the driving signal. Thus, the circuit area needed for a source driver processing images of large bit number is reduced, which decreases the cost. Further, the power system of the display having a large dynamic range of voltage can be also simplified.

Abstract: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor.

Abstract: A drive circuit for driving a semiconductor element is equipped with: a first switch connected to a positive side of a DC power supply; a second switch connected to the other terminal of the first switch and to a negative side of the DC power supply; a third switch connected to the positive side of the DC power supply; a fourth switch connected to the other terminal of the third switch; a fifth switch connected to the other terminal of the fourth switch and to the negative side of the DC power supply; and a capacitor connected to the other terminal of the first switch and to the other terminal of the fourth switch. A gate of the semiconductor element is connected to the other terminal of said third switch; and a source of the semiconductor element is connected to the negative side of the DC power supply.

Abstract: The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed.

Abstract: An output stage may include an input terminal receiving an input signal, an output terminal coupled to an external load, and a pre-buffer coupled to the input terminal and including an enable terminal receiving a general enable signal and a first output terminal for supplying a first control signal. The output stage may also include an output buffer including a first final transistor inserted between the supply terminal and the output terminal, and a control terminal coupled to the first output terminal of the pre-buffer for receiving the first control signal, and a first tracking circuit between the supply terminal and the first output terminal of the pre-buffer. The first tracking circuit may include a first capacitor between the supply terminal and a first intermediate node coupled to the first output terminal of the pre-buffer by a switch activated by a first activation signal during a transient of the first final transistor thereby reconstructing a noise of the first reference voltage.

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract: Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Abstract: A digital amplifier system for driving a capacitive load includes a digital amplifier controller responsive to a digital input command for producing a pulse density modulation signal representative of the digital input command; a switching amplifier for amplifying the pulse density modulation signal and an inductive filter for demodulating the amplified pulse density modulation signal to provide a drive current to drive a capacitive load in response to the digital input command.

Abstract: The present invention discloses a capacitive high-side switch driver for a power converter. The capacitive high-side switch driver according to the present invention includes an inverter and two alternately conducting totem-pole buffers with complementary duty cycles. The duty cycles alternate in response to an input signal. The capacitive high-side switch driver further includes a low-side transistor and a high-side transistor. Once the low-side transistor is turned on, a bootstrap capacitor is charged to create a floating voltage via a charge-pump diode to supply power for the high-side switch driver. To supply additional power for the high-side switch driver, differential signals are produced to further charge the bootstrap capacitor via a bridge rectifier. The capacitive high-side switch driver utilizes a programmable load to provide variable impedance. Furthermore, an under-voltage protector supervises the supply voltage to ensure a reliable gate driving voltage.