Abstract: A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods.

Abstract: A capacitive micro-electromechanical switch (MEMS) integrated circuit (IC) comprises a plurality of capacitors, each having a voltage terminal for applying an actuation voltage to the individual capacitor, wherein each capacitor is capable of being individually cycled. The MEMS IC further includes: a high voltage driver having a voltage distribution mechanism that couples to the voltage terminal of each of the plurality of capacitors to enable the high voltage driver to selectively provide a pre-determined voltage input required to actuate and charge a selected one or more of the plurality of capacitors; and control logic communicatively coupled to the high voltage driver and which deterministically applies power cycle times (less than a stiction limit) for an actuation and de-actuation of at least a first capacitor of the plurality of capacitors to substantially reduce an occurrence of stiction within at least the first capacitor during operation of the MEMS device.

Abstract: A voltage mode driver circuit includes a plurality of VMD cells and a calibration component. The plurality of VMD cells are configured to generate a calibrated emphasis level according to a calibration signal. The calibration component is configured to determine a voltage dependence effect. Additionally, the calibration component is configured to generate the calibration signal according to the determined voltage dependence effect.

Abstract: A gate driving circuit includes a gate control circuit and a gate voltage limit circuit. The gate control circuit establishes or breaks electrical continuity of a gate voltage supply path from a power source line to a gate terminal of a transistor in response to an on-command and an off-command. The gate voltage limit circuit limits a gate voltage of the transistor to be less than or equal to a first voltage in response to the on-command at least in a period until a determination of whether an electric current greater than a fault criterion value flows to the transistor ends and then limits the gate voltage to be less than or equal to a second voltage.

Abstract: An integrated circuit device can include a plurality of analog circuit blocks, each comprising an input section configured to receive an analog input signal, and an output section configured to drive a plurality of output signals corresponding to the input signal, each output signal having a different maximum drive strength; and a signal network comprising a plurality of switches, and providing a configurable connection between at least outputs of the analog circuit blocks and a plurality of N connections to the integrated circuit device, including less than N direct signal paths between each analog circuit block and the N connections.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: A bootstrap gate driver including a load indication unit, a bootstrap gate-drive unit and a drive-control unit is provided. The load indication unit is configured to generate a load indication signal in response to a state of a load. The bootstrap gate-drive unit is configured to drive a switch-transistor circuit in response to an inputted pulse-width-modulation (PWM) signal, wherein the switch-transistor circuit has a high-side driving path and a low-side driving path. The drive-control unit is coupled to the load indication unit and the bootstrap gate-drive unit, and configured to enable or disable the high-side driving path in response to the load indication signal. In the invention, the operation of the low-side driving path is not affected by enabling or disabling the high-side driving path.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a driving signal generator comparing first and second internal voltage signals with lower and upper limit reference voltage signals to generate a pull-up driving signal and a pull-down driving signal, a driver generating a first voltage and a second voltage in response to the pull-up driving signal and the pull-down driving signal, a selecting signal generator comparing the first internal voltage signal with the second internal voltage signal to generate a selection signal, and a selection transmitter that transmits any one of the first and second voltages to the first or second internal voltage signal in response to the selection signal.

Abstract: A driving circuit outputs an output voltage as a driving signal to the gate of a semiconductor element based on a control signal given from an input circuit. The output voltage is at “H” (ON level) if it is determined by a power supply voltage VCC, and is at “L” (OFF level) if it is determined by a ground voltage GND. A reference power supply section includes a series connection of resistors. The reference power supply section obtains a voltage determined by dividing a potential difference between the power supply voltage VCC and the ground voltage GND by a predetermined dividing ratio (resistance ratio between the resistors) as a reference voltage. A buffer circuit applies an output voltage as a reference signal determined by the reference voltage to the source of the semiconductor element.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.

Abstract: An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echoes of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: Disclosed herein are a tunable capacitance control circuit and a tunable capacitance control method. The tunable capacitance control method is a tunable capacitance control method by a tunable capacitance control circuit including an MIM capacitor, a plurality of FET switches, and a control unit, wherein the control unit outputs control signals allowing only one of the plurality of (n) FET switches to be switched on and the remaining (n-1) FET switches to be switched off to the plurality of FET switches, thereby obtaining a desired tunable capacitance value.

Abstract: Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.

Abstract: A method for driving a piezoelectric transducer is provided. An input signal is received. At least one of a plurality of modes is selected for a buck-boost stage from a comparison of a desired voltage on a capacitor to a first threshold and a second threshold, where the desired voltage is determined from the input signal. The piezoelectric transducer is then driven substantially within the audio band using the desired voltage on the capacitor using an H-bridge that changes state with each zero-crossing.

Abstract: A measuring device comprises a plurality of variable capacitors as sensor elements. The plurality of variable capacitors are provided with a drive circuit for each pair. The first electrodes of the two variable capacitors in each pair are electrically connected to each other. The drive circuit for each pair includes a bias supply for applying two AC bias voltages relatively 90° out of phase to the second electrodes respectively of the two variable capacitors to produce an output signal at the first electrodes connected to each other, a multiplier for multiplying the output signal by two AC signals relatively 90° out of phase to produce two multiplication signals, and an integrator for integrating the two multiplication signals for each cycle of the corresponding AC bias voltages to acquire two integration signals for the two variable capacitors.

Abstract: As part of a transmitter and receiver system a droop compensator is provided between the channel isolation device and the driver system to compensate for reduced transition densities. The droop compensator is configured to improve power transfer to the channel in response to reductions in transition density without affecting power transfer during periods of high transition density. The droop compensator creates an impedance mismatch between the matching circuit and driver in relation to the line impedance. The droop compensator may comprise passive elements, such as capacitors, inductors, or resistor, or active elements including transistors or power control modules. The droop compensator may be configured to operate with transformer line couplers or capacitor line couplers, and either current drivers or voltage drivers.

Abstract: A circuit arrangement includes a half-bridge with a high-side switch and a low-side switch, each switch including a control terminal and a load path. The load paths of the high-side switch and the low-side switch are coupled in series between a terminal for a supply potential and a terminal for a reference potential a high-side driver operable to provide a high-side drive signal received at the control terminal of the high-side switch. The high-side driver includes supply terminals a charge storage device coupled between the supply terminals of the high-side driver. A control circuit includes a charging circuit, a switching element and a drive circuit operable to switch on the switching element dependent on at least one operation parameter of the circuit arrangement.

Abstract: A switching circuit includes a switching device including the first and second main electrodes and a control electrode; and a driver including: a first rectifying device having an anode terminal connected to the first main electrode of the switching device; a first driving device having a first main electrode connected to a cathode terminal of the first rectifying device and a second main electrode connected to the control electrode of the switching device; a second driving device having a first main electrode connected to the control electrode of the switching device and a second main electrode connected to the second main electrode of the switching device; and input terminals receiving control signals inputted to a control electrode of the first driving device and a control electrode of the second driving device.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A short-circuit protection circuit (12) configured to protect a switching element from an overcurrent includes: a potential decreasing means for decreasing a potential of a gate terminal when a main circuit current is an overcurrent; a feedback means for performing feedback control on an amount of a decrease in the gate potential caused by the potential decreasing means according to a current amount of the main circuit current; and a phase advancing means for performing phase advance compensation in a feedback loop under the feedback control.

Abstract: The present invention discloses a line driver for a communication system with a variable loading. The line driver includes a positive output terminal, a negative output terminal, a plurality of current cells, for generating a plurality of output currents, and a plurality of switches, for controlling a number of connections between the plurality of current cells and the positive output terminal and the negative output terminal according to impedance of the variable loading, to generate a total output current such that a output voltage swing stays within a specific range.

Abstract: Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

Abstract: A timing control circuit for a switching capacitor dynamic switch includes a first time generator and a second time generator. The first generator includes a first capacitor. The first time generator determines a first time by charging to the first capacitor. The second time generator includes a second capacitor. The first time generator is connected to the second time generator. When the first time ends, the second time generator determines a second time by discharging to the second capacitor.

Abstract: A buffer circuit including an input terminal capable of receiving an input signal and an output terminal capable of being connected to a capacitive load, including an output circuit a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, and means for controlling said first and second transistors receiving the input signal The buffer circuit further includes means for comparing the voltage on the output terminal of the circuit with at least one threshold voltage, the comparison means being connected to said control means.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A method of driving a number of series connected active power semiconductor groups, wherein each of the active power semiconductor groups includes one or more gate oxide-isolated active power semiconductor devices. The method includes generating a current pulse, providing the current pulse to a primary portion of a transformer unit and in response thereto causing a number of reflected current pulses to be reflected at a secondary portion of the transformer unit, and transferring and latching each of the reflected current pulses to create a respective latched gate drive signal, and providing each respective latched gate drive signal to an associated one of the active power semiconductor groups for driving the one or more gate oxide-isolated active power semiconductor devices of the associated one of the active power semiconductor groups. Also, a gate drive circuit that implements the method.

Abstract: A transistor driver includes an inductor coupled to a gate terminal of a transistor and a switching circuit coupled to the inductor and configured to charge a capacitance at a gate terminal of the transistor from a source via the inductor responsive to a first state of a control input, to block discharge of the charged capacitance responsive to a voltage at the gate terminal and to return charge from the charged capacitance to the source responsive to transition of the control input to a second state. The switching circuit may include a switch coupled in series with the inductor and the source and configured to conduct responsive to transition of the control input to the first state and a rectifier coupled in series with the inductor and the source and configured to block discharge of the charged capacitance responsive to the voltage at the gate terminal.

Abstract: A driver circuit is provided. The driver circuit includes a first transistor for receiving a preceding gate signal to generate a first control signal, a second transistor for pulling down the first control signal according to a second control signal, a third transistor for outputting a clock signal according to the first control signal, a fourth transistor for pulling down the clock signal according to the second control signal, a fifth transistor connected to a high voltage source for outputting the second control signal, a sixth transistor for pulling down the second control signal according to the first control signal, a seventh transistor for receiving a next gate signal to pull down the first control signal, and a capacity. The preceding gate signal charges the capacitor to generate the first control signal.

Abstract: Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter includes driver circuitry configured to generate an output signal at an output node and an allocation control module coupled to the driver circuitry. The driver circuitry includes a plurality of driver legs configured to generate the output signal based on a plurality of data bits. The allocation control module is configured to allocate a respective subset of the plurality of driver legs to a respective data bit of a plurality of data bits, wherein the each subset generates a component of the output signal that is influenced by its respective data bit.

Abstract: High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal.

Abstract: Each of a plurality of gate driving parts outputs a first potential (2 V) during a period in which the gates of a plurality of thyristors belonging to the corresponding set are driven (S1N=Low) and outputs a second potential (5 V) that is higher than the first potential at a rising part of the anode driving voltage during a period in which the gates of a plurality of thyristors belonging to the corresponding set are not driven (S1N=High). Each of a plurality of gate driving parts outputs a third potential (3 V) that is lower than the second potential at periods other than the rising part of the anode driving voltage during a period in which the gates of a plurality of thyristors belonging to the corresponding set are not driven (S1N=High).

Abstract: A potential generation circuit and a liquid crystal display device are provided that are capable of reducing power consumption with a simple circuit configuration. The potential generation circuit is a potential generation circuit for generating a common potential that is applied to a capacitive load, and includes a differential amplifier that has a positive input receiving a given set potential and a negative input receiving the common potential that is negatively fed back, a current amplifier that amplifies the output of the differential amplifier and outputs the common potential, a charge recovery capacitor that has one of its ends connected to a reference potential, and an anti-parallel diode that is connected between the other end of the charge recovery capacitor and the common potential.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.

Abstract: A load drive circuit with a current bidirectional detecting function includes: a current bidirectional switch connected between a first wire and a second wire and through which a first forward current flows in a direction from the first wire to the second wire and a first backward current flows in a direction from the second wire to the first wire; a forward current detecting switch connected to the first wire and into which a second forward current correlated to the first forward current flowing through the current bidirectional switch flows; a backward current detecting switch connected to the second wire and into which a second backward current correlated to the first backward current flowing through the current bidirectional switch flows.

Abstract: To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI?NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

Abstract: An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Abstract: Improved digital driver with transition time control of an output stage output transistor of the digital driver. A predriver circuit has a resistor that forms an RC time constant with a feedback capacitor of the output transistor. The RC time constant is adjusted to control corner resolution of the output transistor in output switching. The RC time constant can be controlled by a digitally-controlled variable capacitor. Additionally, a delay may be introduced in the turning on of the output transistor as compared with the turn off time to reduce simultaneous conduction or shoot-through current.

Abstract: An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.

Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

Abstract: A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: Operation of a digital power amplifier for power amplification of a modulated signal is stopped in a period in which a voltage value of a drive signal applied to a capacitive load is constant, to thereby suppress power loss. The power amplification is stopped either when half a period of time when the modulated signal in a first voltage state maintains the first voltage state elapses or when half a period of time when the modulated signal in a second voltage state which is lower in voltage than the first voltage state maintains the second voltage state elapses. Accordingly, when electric current does not flow in a inductor of a low pass filter, it is possible to stop the power amplification. Thus, it is possible to prevent generation of voltage fluctuation in the drive signal due to an electromotive force caused by a self-induction phenomenon of the inductor.

Abstract: A heterodyne dual-slope frequency generation method for the load change of the power supply, which comprises a power transformer, a feedback control circuit, and a dual-slope charge-discharge circuit. The power supply generates different charge current to fit different operating mode through the feedback control circuit, feedback voltage generated into power transformer, and passes through the dual-slope charge-discharge circuit in accordance with the different outer load device and the different outer voltage rising speed. When the outer loading is changed, the feedback control circuit detects error voltage, feeds through power transformer, further changes the supplied current, and finally automatically adjusts the driving current and the output power.