Abstract: In an output driver circuit, a replica circuit includes seventh and eighth transistors corresponding to first and second transistors, respectively, ninth and tenth transistors corresponding to third or fifth, and fourth or sixth transistors in a driver circuit, respectively, and a resistor corresponding to a termination resistor. A reference voltage and a voltage of a node between the ninth transistor and the resistor are input to an operational amplifier, and an output signal of the operational amplifier is input to gates of the first and seventh transistors.

Abstract: A driving circuit that drives a capacitive load includes a drive signal generator that generates a drive signal driving the capacitive load via a transistor pair in response to an analog signal, and a power-source voltage generator that generates a high-voltage power-source voltage and a low-voltage power-source voltage and that supplies the high-voltage power-source voltage and the low-voltage power-source voltage respectively to collectors of the transistors of the transistor pair via a high-voltage output terminal and a low-voltage output terminal. The power-source voltage generator includes multiple power sources connected in parallel, a backcurrent prevention diode connected between the adjacent power sources, and a switch unit that connects the adjacent power sources in series under the on-off control of a controller each time the drive signal rises above a predetermined threshold value or falls below a predetermined threshold value.

Abstract: A repeater circuit. The repeater circuit includes a first output stage having two output circuits, a second output stage having two additional output circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, and responsive thereto another corresponding output circuit is configured to be activated. The output circuits drive an output signal on the output node. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the other corresponding output circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuits.

Abstract: A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.

Abstract: An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Abstract: A driver circuit includes a pre-driver and an output driver. The pre-driver is coupled to receive an input signal and to generate first and second pre-driver output signals in response to the input signal. The output driver generates a driver output signal and includes first and second switches, a native mode transistor, and a driver output. The first switch has a first control terminal coupled to receive the first pre-driver output signal. The second switch has a second control terminal coupled to receive the second pre-driver output signal. The native mode transistor is coupled in series between the first switch and the second switch and has a third control terminal coupled to receive the voltage reference signal. The driver output is coupled between the native mode transistor and the second switch to output the driver output signal.

Abstract: An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.

Abstract: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.

Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.

Abstract: The present invention discloses an electric signal outputting apparatus in a serial electric transmission system. The electric signal outputting apparatus includes a switching part for switchably generating high and low output signals in accordance with signal data and transmitting the output signals to a transmission path, an impedance matching part for matching an output impedance to the impedance of the transmission path, and an auxiliary switching part for subsidiarily supplying current to an output node in the transmission path and subsidiarily absorbing current from the output node in the transmission path when the switching part switches the generation between high and low output signals, wherein the auxiliary switching part conducts the supplying and the absorbing for a period shorter than a pulse width of a reference clock of the serial electric transmission system.

Abstract: A driving circuit that drives a capacitive load includes a drive signal generator that generates a drive signal that drives the capacitive load via a transistor pair in response to an analog signal. A power-source voltage generator generates high-voltage and low-voltage power-source voltages and supplies the power-source voltages to collectors of the transistors via a high-voltage output terminal and a low-voltage output terminal. The power-source voltage generator includes multiple power sources connected in parallel and a switch unit that connects the adjacent power sources in series each time the drive signal rises above or falls below a predetermined threshold value. The driving circuit further includes a voltage controlling capacitor connected to the low-voltage output terminal of the power source, and a power recovery unit having a switch unit that recovers a charge accumulated in the voltage controlling capacitor back to the power source via the high-voltage output terminal.

Abstract: A driving circuit for a capacitive load includes a driving signal generating unit that generates a driving signal for driving the capacitive load by using a pair of driving transistors. A power source voltage generating unit generates high-voltage and low-voltage power source voltages that are higher and lower, respectively, than the voltage of the driving signal and applies the voltages to collectors of the driving transistors. The power source voltage generating unit includes a pair of power source transistors and a capacitor. The low-voltage power source voltage is generated in an output side of the power-source transistor pair as a voltage that is in a voltage region lower than that of the driving signal and follows the driving signal. The high-voltage power source voltage is output from a high-voltage terminal of the capacitor, is in a voltage region higher than that of the driving signal, and follows the driving signal.

Abstract: A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.

Abstract: A pre-emphasis circuit to emphasize edges of transmission data is controlled in correspondence with the result of analysis of the transmission data.

Abstract: Provided is a driving circuit which suppresses a surge voltage at the time of switching a power semiconductor element and reduces switching loss. An element (10) such as an IGBT and another element (20) to be paired are connected, the element (10) is driven by a driver (22), and a gate voltage is controlled by a control circuit (24). When the power semiconductor element is turned off, a comparator (26) detects that a voltage (Vak) of the element (20) is a prescribed voltage, the control circuit (24) switches gate resistance from low resistance to high resistance to suppress the surge voltage, and the switching loss is reduced. When the power semiconductor element is turned on, start up of the voltage (Vak) is detected, and the control circuit (24) switches the gate resistance from high resistance to low resistance after a prescribed time to suppress the surge voltage, and the switching loss is reduced.

Abstract: In driving circuits, signal enhancing circuits are used to enhance driving ability of driving signals. Further, source follower transistors may further enhance driving ability of the driving circuits by conducting more current to loading, so that output signals of the driving circuits may transit more rapidly. In other words, the pull high ability of the driving circuits is enhanced.

Abstract: One example of the invention relates to a circuit arrangement for actuating a high-side transistor which includes a control terminal and a load terminal. The circuit arrangement includes a driver circuit that is designed to generate, in response to a control signal, a driver signal for the control terminal of the high-side transistor. A supply circuit is capacitively coupled to a radio-frequency signal source and is designed to provide a supply voltage to the driver circuit, the supply voltage being referenced to a floating reference potential.

Abstract: An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations.

Abstract: A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input signal has a second state, thereby developing a first output control voltage on the first capacitor. A second capacitor of the pre-driver is discharged with the discharging charging current when the differential input signal has the first state, and charged with the charging current when the differential input signal has the second state, thereby developing a second output control voltage on the second capacitor. An output driver circuit generates a differential output signal in response to the first and second output control voltages. The slew rate of the differential output signal is controlled by the charging and discharging currents.

Abstract: The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.

Abstract: A preset circuit of an audio power amplifier includes an inverter and a voltage drop device. The inverter receives an input signal to output an output signal, and includes a first switch and a second switch. The first switch is controlled with the input signal, and has a first terminal coupled to a power voltage and a second terminal for outputting the output signal. The second switch is controlled with the input signal, and has a third terminal for outputting the output signal and a fourth terminal coupled to a low reference voltage. The voltage drop device is coupled between the first terminal of the first switch and the power voltage and configured to lower the power voltage. The output signal is kept at a low level when the voltage drop device and the first switch are de-actuated due to the power voltage having a level below a first threshold.

Abstract: An analog buffer having voltage compensation mechanism is disclosed for use in a source driving circuit of a liquid crystal display. The analog buffer includes a reference voltage generator, a plurality of capacitors, a plurality of switches, and a plurality of transistors. Each of the capacitors is utilized to store the gate-source voltage of the corresponding turn-on transistor for performing gate-source voltage compensation operation based on the reference voltages provided by the reference voltage generator. Each of the switches functions to control gate-source voltage compensation operation and is turned on/off in response to a corresponding control signal. The analog buffer is capable of compensating the gate-source voltages of turn-on transistors for generating an output voltage having an acceptable tiny offset with respect to an input voltage.

Abstract: A buffer circuit is disclosed. In one embodiment, the buffer circuit includes a preconditioning circuit and a driver circuit. The preconditioning circuit generates a pre-charge signal in response to receiving an input signal. After a predetermined duration, or when the pre-charge circuit reaches a threshold output signal level, the input signal is coupled to an input of the driver circuit. The output signal of the driver circuit is combined with the output signal of the preconditioning circuit to form a composite output signal of the buffer circuit. In one embodiment, the pre-charge signal is used to lower the effective VDS across the transistors of the driver circuit to reduce hot-carrier injection, and therefore reduce transistor performance degradation.

Abstract: A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.

Abstract: Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

Abstract: A voltage buffer with current reuse is described. This voltage buffer can advantageously provide a relatively wide voltage differential using a relatively low current. In one embodiment, a slave branch can be used to minimize potential spikes/glitches in the voltage buffer.

Abstract: A gate voltage detecting circuit 201 detects a gate voltage Vgs of a switching device 11, and when the gate voltage is less than a predetermined voltage that is set to be less than a threshold voltage of the switching device 11, outputs an H-level boost instruction signal. A voltage control circuit 103, when the boost instruction signal is at the L level, outputs a predetermined voltage V1 of a control power supply 102 as it is, and when the boost instruction signal is at the H level, outputs a voltage V2 obtained by boosting the predetermined voltage V1. The drive signal output circuit 104 amplifies a voltage of a PWM pulse output from a PWM pulse output circuit 111 to a voltage output from the voltage control circuit 103.

Abstract: A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.

Abstract: A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: A power switch assembly for a capacitive load 10 which includes a common electrode 14 and first and second discrete electrodes 16, 18, includes a node n1 coupled to a voltage source Vcc for receiving power there from, a first switching device connected between the node n1 and ground, a second switching device connected between the node n1 and ground, and a dividing circuit connected between the node and ground. The dividing circuit includes an output terminal connected to the common electrode 14 of the capacitive load. The first switching device is coupled to the first electrode 16 of the capacitive load configured to control movement of the capacitive load 10 in a first direction. The second switching device is coupled to the second electrode 18 of the capacitive load configured to control movement of the capacitive load 10 in a second direction reverse to the first direction.

Abstract: A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

Abstract: A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data.

Abstract: An operational comparator 10 includes a current source circuit, load circuits driven by the current source circuit, and a current mirror circuit. The load circuits are constituted with MOS transistors, predetermined reference voltage is supplied to the gate terminals of MOS transistors, and each of signal voltages constituting the differential output signal of the differential output circuit is supplied to gate of MOS transistors.

Abstract: A buffer for a driving circuit includes a first transistor, a second transistor and a slew rate controlling circuit. The first transistor serves to provide a current to an output terminal. The second transistor serves to sink a current from the output terminal. The slew rate controlling circuit serves to control slew rate of at least one of the first transistor and the second transistor according to the input signal. The managing circuit serves to prevent the first transistor and the second transistor from turning on simultaneously.

Abstract: In a row-electrode drive circuit of a PDP display device, an N-channel MOS low-side transistor of an output section is in an ON state while a light emission of a capacitive load is sustained. Now, if power to a driver section is lost due to, for example, a disconnection of a line from an external power supply to a low-voltage power terminal, this loss of power is detected by a detection section, and a current path via a parasitic diode of a P-channel MOS transistor, which has turned off, in the driver section to the low-voltage power terminal is interrupted. As a result, the N-channel MOS low-side transistor of the output section has the charged electric charge of the capacitive load stored in a parasitic capacity between its drain and gate, so maintains the ON state.

Abstract: On die termination circuit and method for calibrating the same includes a external resistor connected to a first node, a plurality of calibration resistors connected to a second node, the plurality of calibration resistors being turned on/off in response to a calibration code set, a current mirror configured to mirror currents of the first node and the second node and a code generator configured to generate a calibration code set according to the mirrored currents. In accordance with a method for calibrating an on die termination circuit of the present invention, the method includes a step of mirroring a current of a first node connected to an external resistor and a current of a second node connected to a plurality of calibration resistors and a step of generating a calibration code set according to the mirrored currents.

Abstract: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor.

Abstract: The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed.

Abstract: The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit.

Abstract: A voltage buffer with current reuse is described. This voltage buffer can advantageously provide a relatively wide voltage differential using a relatively low current. In one embodiment, a slave branch can be used to minimize potential spikes/glitches in the voltage buffer.

Abstract: A control device including: an input terminal for receiving a logic control signal; an output terminal for delivering an output control signal from the high-voltage MOS transistor; a first NMOS control transistor with low internal impedance, which is connected between ground and the output terminal and the gate of which is connected to the input terminal; and a second PMOS control transistor, which is connected between a supply terminal and the output terminal and the gate of which is connected to the input terminal by a bipolar transistor mounted to a common base, and which is current controlled at the emitter thereof by a capacitive connecting circuit.

Abstract: An Externally Asynchronous-Internally Clocked (EAIC) system that generates an internal clock signal includes a clock signal control block. The clock signal control block includes a pull-up unit that is activated in response to an input signal used to generate an internal clock signal; a pull-down unit that is activated in response to the input signal used to generate an internal clock signal, and a bypass unit that is provided between the pull-up unit and the pull-down unit, and selectively provides a signal path to the pull-down unit if the pull-down unit is activated and a signal path from the pull-up unit if the pull-up unit is activated.

Abstract: A buffering circuit includes: a first transistor having a gate terminal coupled to an input signal for buffering the input signal to generate an output signal under an operating current, a second transistor cascoded with the first transistor for generating the operating current for the first transistor according to a control signal at a gate terminal of the second transistor, and a control circuit having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to a reference source. The control circuit adjusts the control signal according to the input signal and the reference source, wherein when a voltage level of the input signal varies, the control circuit is arranged to adjust a voltage level of the control signal such that the adjusted voltage level of the control signal varies inversely proportional to the varied voltage level of the input signal.

Abstract: A driver circuit of the present invention includes: a pair of switch elements (P1, N1) connected in series between a ground terminal and a stepped-up voltage VCP application terminal to which a stepped-up voltage VCP is applied; and a clamp element ZD1 connected between a node A between the pair of switch elements and an output terminal T2, the driver circuit driving, according to a voltage signal derived from the node A, an N-channel output transistor Q1 connected between the output terminal T2 and a power supply voltage VCC application terminal to which a power supply voltage VCC is applied. Here, a current control section (IL1, IL2) formed of a resistor and a capacitor that are connected in parallel with each other is inserted in at least one of a current path that connects the node A and the stepped-up voltage VCP application terminal and a current path that connects the node A and the ground terminal.

Abstract: A semiconductor integrated circuit includes a high-side transistor, a low-side transistor, a level shift circuit for driving the high-side transistor, and a pre-driver circuit for driving the low-side transistor. A connection point of the high-side transistor and the low-side transistor serves as an output terminal. The level shift circuit has first and second N-type MOS transistors whose gates are driven by the pre-driver circuit. The semiconductor integrated circuit further includes a diode whose anode is connected to the drain of the first or second N-type MOS transistor to which the gate of the high-side transistor is not connected, and whose cathode is connected to the output terminal.

Abstract: Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Abstract: A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb).

Abstract: An output stage may include an input terminal receiving an input signal, an output terminal coupled to an external load, and a pre-buffer coupled to the input terminal and including an enable terminal receiving a general enable signal and a first output terminal for supplying a first control signal. The output stage may also include an output buffer including a first final transistor inserted between the supply terminal and the output terminal, and a control terminal coupled to the first output terminal of the pre-buffer for receiving the first control signal, and a first tracking circuit between the supply terminal and the first output terminal of the pre-buffer. The first tracking circuit may include a first capacitor between the supply terminal and a first intermediate node coupled to the first output terminal of the pre-buffer by a switch activated by a first activation signal during a transient of the first final transistor thereby reconstructing a noise of the first reference voltage.

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d