Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.

Abstract: A high-voltage tolerant output driver for use in a switching regulator is provided herein. The driver allows the switching regulator to regulate supply voltages that exceed device breakdown limits for the process technology from which the high-voltage tolerant output driver is fabricated. Unregulated supply voltages can vary over a wide range. The regulator only needs two intermediate voltages.

Abstract: A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.

Abstract: Drive and startup circuits are described particularly suitable for use with a switched capacitor divider. In one example, a drive circuit has a level shifter coupled to a gate of each switch of a switched capacitor drive circuit to couple alternating current into the respective gate, a positive phase low side driver coupled to each level shifter to drive the gates of the top switch path through the respective level shifters, and a negative phase low side driver coupled to each level shifter to drive gates of the bottom switch path through the respective level shifters. A startup circuit, such as a capacitive soft start circuit may be used to slow the application of the current to each switch.

Abstract: A charge pump includes a current source/sink unit that charges/discharges an output node in response to an UP/DOWN signal generated by a PFD (phase frequency detector). The charge pump also includes a pull-down/pull-up unit configured to discharge/charge a cascode node within the current source/sink unit for a limited time period after the UP/DOWN signal reaches a threshold level during transition of the UP/DOWN signal for turning off the current source/sink unit.

Abstract: An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.

Abstract: In a load-drive controller, a first comparing unit compares a load current supplied from an H bridge circuit and a desired setting current; a PWM control unit generates a control signal to control the load current; a gate driver drives and controls output transistors of the H bridge circuit based on the control signal, and a load current monitoring unit determines which is larger a level shift equivalent value of the setting current or a peak hold equivalent value of the load current, and the PWM control unit controls increase or decrease of the load current based on a comparison result of the first comparing unit and on a determination result of the load current monitoring unit, so that the load current quickly reaches the setting current of a micro step drive during decrease of the setting current.

Abstract: A pre-driver for driving a high-side transistor of a bridge driver is connected to a bridge driver including first and second drive transistors connected in series between a high voltage power supply and ground. A reference circuit generates a reference voltage that varies depending on the output voltage of the bridge driver. In response to the reference voltage, the regulator circuit generates an internal power supply voltage that is substantially higher than the output voltage by a constant value. A buffer circuit generates a drive voltage for driving the first drive transistor based on the internal power supply voltage and the output voltage.

Abstract: In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal.

Abstract: A drive circuit in power electronic systems comprising a half-bridge circuit of two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged in a series circuit. The drive circuit has a BOT level shifter for transmitting an input signal from a drive logic to a BOT driver. The BOT level shifter is formed as an arrangement of an UP and a DOWN level shifter branch and a signal evaluation circuit connected downstream thereof. In the inventive method for transmitting the input signal, the signal evaluation circuit transfers an output signal to the BOT driver at least one of the UP and DOWN level shifter branches outputs a signal to the respectively assigned input of the signal evaluation circuit.

Abstract: A buffer circuit is provided, having an odd number of stages of inverting amplifiers, wherein the stages are capacitive coupled. A negative feedback path feeds back from an output terminal of the final stage of the inverting amplifiers to an input terminal of the initial stage. A reference current source is also provided. A first switch is provided between the adjacent stages of the inverting amplifiers and switched, depending upon a mode of operation. A second switch is provided for selectively driving at least a transistor(s) in the final stage to cause a current mirror circuit with the reference current source depending upon a mode of operation.

Abstract: A driving circuit to drive an output stage comprising a high side NMOS and a low side NMOS is provided. The driving circuit comprises: a diode comprising an anode and a cathode, wherein the anode is electrically connected to a first voltage source and the sources of a first and a second PMOS; a third and a fourth PMOS both comprising a drain, a source and a gate, wherein the sources are respectively connected to the gates of the second and first PMOS, the drains are respectively connected to the drains of the first and second PMOS. A first and a second NMOS both comprise a drain, a source and a gate, wherein the drains are respectively connected to the drain of the fourth and third PMOS, the sources are coupled to a second voltage source, the gates are respectively connected to a first input and a second input.

Abstract: A high side transistor driver includes a sender module that generates a power input signal. A converter module receives the power input signal and generates an output signal that has a higher voltage than the power input signal. A receiver module receives the output signal and the power input signal and transitions a transistor between ON and OFF states based on the output signal and the power input signal.

Abstract: A high speed voltage translator circuit includes a voltage divider coupled between first and second power supplies, a transconductance amplifier coupled between third and fourth power supplies including a non-inverting voltage input coupled to the voltage divider, an inverting voltage input for receiving an input signal, and a current output, and a current comparator coupled between the third and fourth power supplies having an input coupled to the current output of the transconductance amplifier, and an output for providing a translated output voltage. The translated output voltage transitions between the third and fourth power supply voltage levels, the third power supply voltage level being more positive than a first power supply voltage level, and the fourth power supply voltage level being more negative than a second power supply voltage level.

Abstract: In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.

Abstract: A clock buffer has a band-pass frequency characteristic, in which a pass band of the buffer includes a fundamental frequency of a clock and a gain for attenuating signals, that is, a gain of less than 0 dB is provided at frequencies below the pass band.

Abstract: In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.

Abstract: A dual-mode LVDS/CML transmitter allows a single circuit to operate as either an LVDS transmitter or a CML transmitter. The transmitter mode can be switched by activating or deactivating appropriate circuit elements, and changing the voltage or current produced by appropriate sources or sinks. This flexibility allows a single transmitter to operate well in both AC and DC coupling conditions, and facilitates interoperation with a greater variety of receivers.

Abstract: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches are set to a second switch position to operate the repeater circuit in the normal repeater mode.

Abstract: A circuit system and method are provided to modify a hard disk writer/driver pre-amplifier electronic circuit to synchronize current boosting control signals. The circuit system obtains a single boosting control signal from a single source. Component boosting control signals, a positive and a negative boosting control signal are indirectly generated via processing through two independent intermediate circuits. The two boosting control signals are pulse shaped signals via intermediate circuits which generate the corresponding first and second intermediate output signals in a manner that the two intermediate output signals are made compatible with one another and particularly synchronize to be later combined by some manner of combiner circuit without the generation of unwanted components in the output signal.

Abstract: An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.

Abstract: In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Abstract: A method drives a transistor half-bridge. The method includes measuring a delay time between an edge of an input signal and an corresponding edge of a phase signal, and saving the delay time as a saved delay time value. The phase signal is the output of the transistor half-bridge. In the method, the following steps are repeated until the saved delay time value differs from the delay time by more than a given threshold: decrementing the delay-value of a programmable delay circuit and the saved delay time value by a given decrement, the programmable delay circuit coupled to a control terminal of a first transistor of the half-bridge, and measuring the delay time between an edge of the input signal and an corresponding edge of the phase signal.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A method of transmitting data can include pre-emphasizing data for transmission by a transmitter over a transmission line based on an error feedback signal provided to the transmitter from a receiver of the pre-emphasized data.

Abstract: In a high voltage switch circuit for programming memory cells, preset devices for precharging the core circuit are eliminated by statically presetting nodes of the switch core circuit through a pair of drive circuits arranged to pull up or down a pair of cascoded transistors in the core circuit.

Abstract: A novel output buffer circuit including an input circuit, a voltage generating circuit, and an output circuit forms a three-state buffer circuit. The output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. With such a configuration, a simple circuit using no high voltage insulated transistors and level shift circuits can be made, and the simple circuit can output either a low voltage signal or a high voltage signal responsive to a low voltage input signal, reduce the manufacturing cost and the delay of the risetime of the output signal, which are associated with a high voltage insulated transistor. Furthermore, cost can be reduced by miniaturization of the circuit size.

Abstract: An input/output circuit has an output terminal, a first transistor, a second transistor, a pulse generator, and a bias circuit. The first transistor drives the output terminal based on a predetermined signal. The second transistor controls a potential of the gate of the first transistor. The pulse generator outputs a pulse with a predetermined time width when a level of the predetermined signal changes. The bias circuit generates a bias voltage for controlling the second transistor when the pulse is outputted, and impressing the bias voltage to the gate of the second transistor.

Abstract: Embodiments for providing a plurality of bias voltages to input/output circuitry are disclosed.

Abstract: An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.

Abstract: In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type.

Abstract: A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a two wire line by a predetermined amount and amplifying the signal by the same predetermined amount. The front-end amplifier generates the common-mode voltage of the input signal for a reference generator that determines the logic level of the incoming signal and subtracts a bandgap voltage reference from the common-mode voltage. A comparator compares the difference between the output of the front-end amplifier and the resultant signal generated by the reference generator to generate an output signal for the receiver. This CAN receiver architecture is faster than conventional designs and possesses an improved common-mode rejection, while operating over a wide input common mode range.

Abstract: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change.

Abstract: An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.

Abstract: The present invention provides a driving circuit. It includes a plurality of current mirrors to generate a first charge current and a second charge current in response to a reference current. A switch circuit generates a driving signal in response to an input signal. A driving switch is coupled between the first charge current and the switch circuit. Once the driving switch is turned on and the level of the input signal is in high level, the switch circuit generates the driving signal, the level of the driving signal-being in high level, in response to the first charge current and the second charge current. A detection circuit generates a control signal to turn on/off the driving switch. The detection circuit turns off the driving switch to disable the first charge current after a period of delay time when the level of the driving signal is in high level.

Abstract: A low voltage differential signal (LVDS) driver comprising a cascade current source circuit coupled to a positive voltage supply configured to supply a current, a cascade current sink circuit maintained at a ground voltage configured to receive the current; the cascade current source circuit being coupled to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals, the current switching circuit configured to provide a constant differential output voltage while in operation. Other embodiments are also disclosed.

Abstract: An output buffer for providing a buffered current to a circuit load includes a plurality of operative stages, each one for generating a component of the buffered current and an enabling circuit for selectively enabling each operative stage. The output buffer further comprises at least one auxiliary stage and control means for measuring a control current that can be delivered by the at least one auxiliary stage and for activating the enabling means according to the measured control current.

Abstract: An analog buffer used in a source driver is provided. The analog buffer havs an input end, an output end, a transistor, first and second capacitors, first, second, third, fourth and fifth switches. The source and the drain of the transistor is coupled to the output end and receives a first voltage respectively. The first end of the first and the second capacitors are coupled to the gate of the transistor. The second end of the first and the second capacitors are coupled to the first end of the first, second and fourth switches and the first end of the third and fifth switches respectively. The second end of the first switch receives a second voltage. The second end of the second and third switches are coupled to the input end. The second end of the fourth and fifth switches are coupled to the output end.

Abstract: An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line, and a mode register set. The mode register set generates an impedance control signal group, a driving width control signal group and a delay control signal group. The amount of an auxiliary impedance (SIM), and the driving width and driving time point of an auxiliary signal (XSDR) can be controlled using the impedance control signal group, the driving width control signal group and the delay control signal group. Therefore, in accordance with the output driver of the present invention, the amount of output impedance (OIM), a pre-emphasis width and a pre-emphasis time point can be readily controlled, and the efficiency of the transmission of an output signal to a reception system is improved.

Abstract: A driving device of a capacitive load includes a modulator that executes pulse modulation on a drive waveform signal. An inductor performs low-pass filtering on the modulated drive waveform signal and outputs the low-pass filtered signal as a drive signal towards a load capacitor as the capacitive load. A load selection control circuit selects a load capacitor and a dummy load capacitor to be connected to the inductor so that a sum of the capacitances of the selected load capacitor and dummy load capacitor is kept within a predetermined range. A feedback circuit executes a filtering process on the drive signal so that a frequency characteristic of a passing band of the drive signal becomes substantially flat. The resulting signal is provided to the modulator as a feedback signal. The modulator executes the pulse modulation on a difference value between the drive waveform signal and the feedback signal.

Abstract: A buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an input/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: Dual-function drivers capable of outputting LVDS or TMDS differential signals by sharing output terminals under differential modes. In the dual-function driver, an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode.

Abstract: A source follower includes first through third switches, first and second transistors, and a first capacitor. The first switch is used to determine whether or not to couple the source of the first transistor with an input signal. The second switch is used to determine whether or not to couple a gate and a drain of the first transistor with a first voltage. A first end of the first capacitor is coupled with a first control signal, and a second end of the first capacitor is coupled to the drain of the first transistor and a gate of the second transistor. The third switch is used to determine whether to or not couple a drain of the second transistor with the first voltage, and a source of the second transistor serves as an output of the source follower.

Abstract: A mixed-voltage I/O buffer comprises an input circuit, an output circuit, an I/O pad, a pre-driver circuit coupled to the output circuit, two added coupled N-type transistors, and a dynamical gate-controlled circuit coupled to each gate of the two N-type transistors and the pre-driver circuit; one of the N-type transistors is coupled to the input circuit and the output circuit; the other N-type transistor and the dynamic gate-controlled circuit are together coupled to the I/O pad. Thereby, a mixed-voltage I/O buffer which receives 2×VDD-tolerant input signals and overcomes the hot-carrier degradation is realized.

Abstract: The line driver circuit is provided that includes a first pull-up variable resistor connected between a first power supply and the first output terminal, a second pull-up variable resistor connected between the first power supply and the second output terminal, a first pull-down variable resistor connected between a second power supply and the first output terminal, a second pull-down variable resistor connected between the second power supply and the second output terminal, a floating variable resistor connected between the first output terminal and the second output terminal, and coder logic to adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor in response to received data bits.

Abstract: A driver circuit for outputting an output signal corresponding to an input signal given to the driver circuit, includes a voltage generating unit for outputting a basic output voltage corresponding to the input signal, a first buffer circuit for outputting an output voltage corresponding to the basic output voltage outputted by the voltage generating unit, a second buffer circuit, of which power consumption is larger than the first buffer circuit, for generating and outputting a voltage corresponding to the output voltage as the output signal, a simulating circuit including a simulating buffer circuit for generating a simulated voltage corresponding to the basic output voltage outputted by the voltage generating unit, the simulating buffer circuit having substantially the same characteristic as that of the first buffer circuit, and a controlling unit for controlling the basic output voltage outputted by the voltage generating unit based on the simulated voltage.

Abstract: A low differential output voltage circuit having a voltage generator and a differential output unit is provided. The voltage generator includes a first PMOS transistor, a first amplifier circuit, a unit gain stage, a first NMOS transistor, a second NMOS transistor. The differential output unit includes a first controlled current source, a second controlled current source, a common voltage circuit, a first switch, a second switch, a third switch, and a fourth switch. Due to the voltage generator directly provides a common mode voltage to the differential output unit, and the first amplifier circuit and the unit gain stage could overcome a channel modulation effect of MOS transistors and enhance the driving ability of the common mode voltage respectively. Thus, a response time of the invention is decreased, and an output current of the differential output unit is in a proportion to the reference current received by the voltage generator.

Abstract: The present invention provides a buffer circuit meeting both of low power consumption requirement and an improvement in slew rate characteristics which are in a relation of trade off. Voltage difference detection circuits are provided for detecting a voltage difference between the input signal at rising and at trailing and an output signal. Based on the voltage difference, voltage-current conversion circuits increase a bias current to be supplied to an output NMOS transistor m1 and a source terminal of an output PMOS transistor constituting an output circuit. And, the voltage difference detection circuits have offset voltages. Only when the voltage difference changes into a level higher than the offset voltage, that is, when the input signal changes abruptly (rise or down), bias current increases.

Abstract: A high voltage tolerant input buffer capable of operating across wide range of power supply, including low power supply voltages, dynamically controls the gate voltage of an NMOS pass transistor by sensing the incoming high voltage signal at the pad and dynamically controlling the gate bias voltage of NMOS pass transistor.