Abstract: A buffer circuit includes a first power source node receiving a first voltage, a second power source node receiving a second voltage lower than the first voltage, an output node driving the first and second voltage, a first transistor coupled between the first power source node and the output node, the first transistor being controlled by a first voltage swing, a second transistor coupled between the second power source node and the output node, the second transistor being controlled by a second voltage swing smaller than the first voltage swing and a switch circuit coupled between the output node and the second transistor, the switch circuit being controlled by a third voltage swing larger than the second voltage swing.

Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.

Abstract: Embodiments of the invention relate to a method and apparatus to drive non-resistive loads. The non-resistive load driver may include two or more drivers, such as a high-drive circuit and a low-drive circuit, to drive rail-to-rail output voltages and to stabilize the output voltages at a substantially constant level. The high-drive circuit may drive the output voltage of the non-resistive load driver to a threshold level, whereas the low-drive circuit may modify the output voltage of the non-resistive load driver to approximate an input voltage of the non-resistive load driver, and compensate any leakage associated with the non-resistive loads to provide a substantially constant output voltage. The low-drive circuit consumes less current than the high-drive circuit. The non-resistive load driver consumes less power and use less chip space.

Abstract: A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

Abstract: A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal.

Abstract: An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.

Abstract: An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: A charge pump driving circuit for generating a driving pulse signal to drive a charge pump circuit is disclosed. The charge pump driving circuit includes a control signal generator and a driving signal generator. The control signal generator generates a first control signal, a second control signal, and a third control signal, in which the third control signal transits in the first place, the first control signal transits next, and the second control signal transits last. The driving signal generator, controlled by the first control signal, the second control signal and the third control signal, generates the driving pulse signal, in which the driving signal generator has a rare short circuit current flowing from a supply terminal providing a supply voltage to a ground terminal providing a ground voltage.

Abstract: There is provided a circuit whose output is free from high impedance to improve wrong transmission and waveform overshoot, realizing a semiconductor integrated circuit device in which plural channels is integrated with transmitter circuit as unit channel, in the transmitter circuit used in a medical ultrasound system and drives a transducer by voltage pulses having plural positive and negative electric potentials including ground potential. The transmitter circuit includes a conventional pulse generating circuit supplied with positive and negative voltage largest in absolute value, a P-channel analog switching pulse generating circuit supplied with positive voltage being the second largest therein, an N-channel analog switching pulse generating circuit supplied with negative voltage being the second largest, and an N-channel analog switching ground level damping circuit supplied with ground potential. The circuits are connected to output terminal.

Abstract: Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first output in response to an input. The circuit also includes a first current element coupled to the first positive driver to enable generation of a current. Further, the circuit includes a first negative driver coupled to the first current element, and responsive to the input and the current, due to the first current element, to generate a first negative transition, at a second output, at a rate similar to that of the first positive transition.

Abstract: A complementary high voltage switched current source circuit has a complementary current source pair, wherein a first of the current source pair is coupled to a positive voltage rail and a second of the current source pair is coupled to a negative voltage rail. A digital logic-level control interface circuit is coupled to the complementary current source pair and to the positive voltage rail and the negative voltage rail. A pair of high voltage switches is coupled to the complementary current source pair and the digital logic-level control interface circuit and controlled by the digital control interface circuit.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: A method controls a power MOS transistor having a control terminal and a load path, the load path connected in series with a load between voltage supply terminals, wherein a power supply voltage between the voltage supply terminals imposes a load voltage across the load and a load path voltage across the load path of the power MOS transistor. The method includes generating a control current for the control terminal during a switching process when the power MOS transistor changes switching states. The control current is dependent on the power supply voltage and on at least one of the group consisting of the load path voltage and the load voltage.

Abstract: A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level.

Abstract: Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.

Abstract: A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage.

Abstract: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.

Abstract: A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value.

Abstract: An integrated circuit includes an input terminal for applying an input signal, a further input terminal for applying a further input signal having a level differing from the level of the initial input signal, an output terminal for providing an output signal, a switching unit having a controllable switch, which is arranged between the input terminal and the output terminal, and a further switching unit, which is arranged between the further input terminal and the output terminal. The integrated circuit is operated in a first and subsequent second operating state. The controllable switch of the switching unit is controlled to be conductive in the first and second operating state. In the first operating state, the output signal is provided in dependence on the level of the input signal, and in the second operating state in dependence on the level of the second input signal.

Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

Abstract: Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply.

Abstract: A switching power supply device performs a stable operation with fast response for a semiconductor integrated circuit device. A capacitor is provided between the output side of an inductor and a ground potential. A first power MOSFET supplies an electric current from an input voltage to the input side of the inductor. A second power MOSFET turned on when the first power MOSFET is off allows the input side of the inductor to be of a predetermined potential. A first feedback signal corresponding to an output voltage obtained from the output side of the inductor and a second feedback signal corresponding to an electric current flowed to the first power MOSFET are used to form a PWM signal. The first power MOSFET has plural cells of a vertical type MOS-construction.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: A transit state element circuit. The transit state element circuit includes a clock input stage coupled to receive a clock signal, an output stage configured to drive an output signal on an output node and an activation stage coupled to an input node. The activation stage is configured to, responsive to the clock input stage detecting a transition from a first logic level to a second logic level and detecting a logical transition of an input signal on the input node, activate the output stage to drive an output signal on the output node. A storage element is configured to capture a logic value of the input signal when the clock is at the second logic level and to store the logic value, and to provide the output signal on the output node when the clock signal is at the first logic level.

Abstract: A transistor driver includes a sender module configured to generate a power input signal. A converter module includes a transformer including a first side and a second side. The first side of the transformer is configured to receive the power input signal. A rectifier is connected to the second side of the transformer. The converter module is configured to generate an output signal at an output of the rectifier. A first receiver module is connected to each of the second side of the transformer and the output of the rectifier. The first receiver module is configured to transition a first transistor between an ON state and an OFF state based on a first signal received from the second side of the transformer.

Abstract: A technique for simplifying the control of a switch is presented. In one embodiment, a method of controlling a switch as a function of the voltage across the switch is presented. In one embodiment a method of controlling a switch as a function of the slope of the voltage across the switch is present. In one embodiment a switching is switched on for an on time period that is substantially fixed in response to a voltage across the switch while the switch is off. In one embodiment a switch is switched on for an on time period that is substantially fixed in response to the slope of the voltage across the switch while the switch is off.

Abstract: A drive circuit includes a plurality of output drive terminals and a plurality of push-pull circuit stages. Each of the push-pull circuit stages includes a pair of complementary transistors having a common terminal connected to a respective output drive terminal. The drive circuit further includes a plurality of first transistors connected in series with at least one of the pair of complementary transistors of the push-pull circuit stages, respectively, and a common second transistor. The common second transistor is connected with each of the plurality of first transistors to form a current mirror circuit. The drive circuit further includes a mirror current setting circuit for setting a mirror current flowing through the common transistor.

Abstract: A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.

Abstract: A transmission driver including a main driving stage and a sub-driving stage is provided. The main driving stage has a main current source, and is adapted for receiving a first differential input data stream and outputting a differential output data stream by using the main current source. The sub-driving stage has two sub-current sources, and is adapted for receiving a second differential input data stream and counteracting/reducing the attenuation or distortion of the differential output data stream caused by a long transmission distance by using the sub-current sources. There is a delay of a specific bit length between the first and the second differential input data streams.

Abstract: An operational circuit includes: a first stage having a first input terminal for receiving an input signal and a second input terminal for receiving an output signal of the operational circuit, for outputting a first control signal at a first output terminal and a second control signal at a second output terminal according to the input signal and the output signal; a second stage coupled to the first stage, for generating the output signal according to a first driving current controlled by the first control signal and a second driving current controlled by the second control signal; and a protection circuit coupled between the first stage and the second stage, for detecting the first driving current to selectively adjust the first control signal.

Abstract: A semiconductor device with less power consumption and an electronic appliance using the same. The semiconductor device of the invention is supplied with a first potential from a high potential power source and a second potential from a low potential power source. Upon input of a first signal to an input node, an output node outputs a second signal. With the semiconductor device of the invention, a potential difference of the second signal can be controlled to be smaller than a potential difference between the first potential and the second potential, thereby power consumption required for charging/discharging wires can be reduced.

Abstract: A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit.

Abstract: A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to calibrate their output impedances is provided proximate to the output drivers. A state machine is used to query each output model, and to set the proper output enable signals for the enable transistors in the output drivers in each group so as to calibrate their output impedances. By decentralizing the output models, the process used to form the output models will, due to proximity to the output drivers in each group, be indicative of the process used to form the output drivers. Thus, when each group of output drivers is calibrated, the output models used for each will compensate for process variations as may occur across the surface of the integrated circuit.

Abstract: A shift register capable of supplying only a necessary clock signal to a necessary unit register with simple constitution. A semiconductor device is provided with a shift register in which a plurality of stages of unit registers is connected, in which the unit register comprises a flip-flop circuit, a first switch and a second switch, a first clock signal line is electrically connected to the flip-flop circuit through the first switch, a second clock signal line is electrically connected to the flip-flop circuit through the second switch, the first switch is controlled to be on/off by an output signal from the flip-flop circuit, and the second switch is controlled to be on/off by an input signal to the flip-flop circuit.

Abstract: A pseudo differential circuit is a circuit system taking the advantages of both a CMOS circuit and a differential circuit. However, when process variability and the like are taken into account, a cross point of positive and negative outputs is not constant, thereby increasing a variation in duty of an output waveform. A semiconductor circuit according to the present invention includes: a first transistor being of a first conductivity type, coupled between a first power supply and an output terminal, and applied with an input signal; a second transistor being of a second conductivity type and coupled between a second power supply and the output terminal; a third transistor being of the second conductivity type and coupled between the first power supply and the output terminal; and a fourth transistor being of the first conductivity type and coupled between the second power supply and the output terminal.

Abstract: A driver circuit usable for a display panel can generate an output signal in response to an input pulse signal supplied to only one input signal terminal thereof. The driver circuit includes a pulse generating circuit for generating an output signal at the output terminal. The pulse generating circuit has a first and second differential input stage for respectively driving a push-pull construction of output transistors in response to the input pulse signal supplied through the input signal terminal with respect to the push-pull output, whereby to simplify the circuitry, operate at a high slew rate, and decrease electric current consumption.

Abstract: A power semiconductor drive circuit device includes: an electronic control device generating a control input signal; a signal transfer circuit device having a main path and a self-diagnosis functional block; and a power semiconductor driven by the control output signal from the signal transfer circuit device. The self-diagnosis functional block includes: a feedback pulse transmitter circuit; a second signal transfer circuit; and a second receiver circuit. The second receiver circuit compares the control output signal with the control input signal so as to find out whether the control output signal is matched or unmatched with the control input signal, and then outputs a result to a comparison signal output terminal. A signal outputted to the comparison signal output terminal is transferred to the electronic control device.

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract: Provided is a semiconductor integrated circuit including: a differential driver that is disposed between a first power supply and a second power supply and drives differential input signals to generate differential output signals; and a control signal generation circuit that generates a first control signal for controlling a voltage level of each of the differential output signals. When each of a pair of output signals forming the differential output signals is changed from a voltage level corresponding to the first power supply to a voltage level corresponding to the second power supply, an amount of change in the voltage level of the corresponding output signal is controlled based on the first power supply.

Abstract: Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.

Abstract: A driver arrangement comprises a charge pump based oscillator (OSC) having a first charging element (CE1) with a first capacitance (C1) for generating an oscillator signal depending on a first capacitance (C1) and on a first charging current (I1). A controllable current source (CCS) is configured to generated a first and a second charging current (I1, I2) depending on a current control signal, wherein first and second charging currents (I1, I2) have a first predetermined scaling ratio (?). The current control signal is provided by a control unit (CTL). An output circuit (DRV) of the driver arrangement comprises a second charging element (CE2) having a second capacitance (C2). The output circuit (DRV) is configured to generate an output signal depending on a data signal (TXD), on the second charging current (I2) and on the second capacitance (C2). Herein, the second capacitance (C2) has a second predetermined scaling ratio (?) with respect to the first capacitance (C1).

Abstract: An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving transistors with respective body biases of at least two levels.

Abstract: A repeater circuit. The repeater circuit includes two output circuits, two echo circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, which is configured to drive an output signal on an output node. A corresponding echo circuit is configured to be activated and to drive an input node responsive to activation of the corresponding output circuit. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the corresponding echo circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuit.

Abstract: A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage.

Abstract: A source driver, which has a first resistor string, a first digital-to-analog converter, and a channel buffer, is provided. The first resistor string has a plurality of resistors connected in series, wherein each of the resistors of the first resistor string provides a corresponding gamma voltage. The first digital-to-analog converter is coupled to the resistors of the first resistor string. The digital-to-analog converter selectively outputs one of gamma voltages provided by the resistors as a first output voltage according to a data code. The channel buffer is coupled to an output terminal of the first digital-to-analog converter to output a second output voltage by shifting a voltage level of the first output voltage.

Abstract: A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.

Abstract: Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.

Abstract: A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages.

Abstract: The present invention discloses a capacitive high-side switch driver for a power converter. The capacitive high-side switch driver according to the present invention includes an inverter and two alternately conducting totem-pole buffers with complementary duty cycles. The duty cycles alternate in response to an input signal. The capacitive high-side switch driver further includes a low-side transistor and a high-side transistor. Once the low-side transistor is turned on, a bootstrap capacitor is charged to create a floating voltage via a charge-pump diode to supply power for the high-side switch driver. To supply additional power for the high-side switch driver, differential signals are produced to further charge the bootstrap capacitor via a bridge rectifier. The capacitive high-side switch driver utilizes a programmable load to provide variable impedance. Furthermore, an under-voltage protector supervises the supply voltage to ensure a reliable gate driving voltage.