Abstract: Clock driver circuit having upper and lower transistors1 and upper and lower transistors2. Voltage node1 coupled to electrodes of upper transistor1 and upper transistor2. Voltage node2 coupled to electrodes of lower transistor1 and lower transistor2. Coupling transistor1 couples another electrode of upper transistor1 to another electrode of lower transistor2. Coupling transistor2 couples another electrode of upper transistor2 to another electrode of lower transistor1. Two series1 capacitors couple the another electrode of upper transistor1 to the another electrode of lower transistor1. Two series2 capacitors couple the another electrode of upper transistor2 to the another electrode of lower transistor2. Node intermediate the two series2 capacitors provides in-phase clock output. Node intermediate the two series1 capacitors provides anti-phase clock output. In-phase clock input is coupled to control inputs of upper transistor1, coupling transistor1 and lower transistor1.

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract: A novel high speed, >1 GHz or 2 Gbits/s, low voltage differential signal (LVDS) driver is disclosed. The LVDS design achieves low power consumption while providing LVDS compliant impedance termination to power supply and ground. An output stage of the LVDS is implemented using a Nmos and a Pmos follower in a push pull configuration. This new design relies first on a follower type of an output stage, which provides the inherent impedance termination, second on an AC, capacitive, coupling and DC restoration to drive output stage gates, and on a low power dummy bias generator that supplies DC restoration voltages. As the supply voltage is lower the thick oxide devices performance suffer, therefore for this new design is mainly implemented with thin oxide devices.

Abstract: To provide a load drive circuit that has a satisfactory phase characteristic and can be realized as a low-price LSI chip. A series circuit of nonlinear resistive elements (P2 and N3) and switch elements (N2 and P3) is inserted between control input terminals (GP1 and GN1) of output elements (P1 and N1) of a final amplifier (AMP0) and an output terminal (OUT) of the load drive circuit. The nonlinear resistive element has a nonlinear characteristic in which a resistance value decreases as an applied voltage value increases and the resistance value increases as the applied voltage value decreases. The switch elements are switching-controlled to selectively come into an ON state only in a high-electric potential period or a low-electric potential period of an input signal according to whether the output element is arranged on a high-electric potential side or a low-electric potential side in the final amplifier.

Abstract: A high voltage driver circuit for devices such as non-volatile memories, in which a low voltage driver is combined in two different ways with a high voltage driver In one, input-independent embodiment, a low voltage driver (Q7, Q8) is connected directly in parallel with a high voltage driver, thereby providing a high voltage signal path for high voltage operations and a low voltage signal path for low voltage operations. In an alternative, partially input-dependent embodiment, a low voltage driver is connected to the output of a high voltage driver (Q9, Q10), which may comprise a partial level shifter (Q1 B Q6). The output of this low voltage driver (Q9, Q10), which forms the output terminal of the entire stage, has a pull up/pull down transistor (Q11), depending on whether the partial level shifter (Q1 B Q6) is a positive or negative level shifting high voltage driver.

Abstract: A driving device of a capacitive load includes a modulator that executes pulse modulation on a drive waveform signal. An inductor performs low-pass filtering on the modulated drive waveform signal and outputs the low-pass filtered signal as a drive signal towards a load capacitor as the capacitive load. A load selection control circuit selects a load capacitor and a dummy load capacitor to be connected to the inductor so that a sum of the capacitances of the selected load capacitor and dummy load capacitor is kept within a predetermined range. A feedback circuit executes a filtering process on the drive signal so that a frequency characteristic of a passing band of the drive signal becomes substantially flat. The resulting signal is provided to the modulator as a feedback signal. The modulator executes the pulse modulation on a difference value between the drive waveform signal and the feedback signal.

Abstract: A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

Abstract: An output buffer circuit includes a first output transistor having a source terminal connected to a voltage supply and a drain terminal connected to an output node. The first output transistor is capable of coupling the output node to the voltage supply when the input signal is at a high voltage in the input voltage range. The circuit also includes a second output transistor having a drain terminal connected to the output node and a source terminal connected to ground. The second output transistor is capable of coupling the output node to ground when the input signal is at a low voltage in the input voltage range. The circuit further includes a current-limiting circuit coupled to a gate terminal of the first output transistor and capable of limiting a current flowing through the gate terminal when the first output transistor is turned on. The output node outputs an output signal in an output voltage range, wherein a high voltage of the output voltage range exceeds the high voltage of the input voltage range.

Abstract: An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (VOUT). The third transistor (M3) is coupled between the first node (tn) and the output (VOUT). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3).

Abstract: An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.

Abstract: The problem to be solved by of this claimed application is solved by providing an interface circuit and a signal output adjusting method that are capable of adjusting amplitude of a transmission-side signal by taking attenuation of a transmission path into consideration. In a transmission-side circuit part of an interface circuit 100, a repetitive signal 111 having constant amplitude is sent out to a transmission path 123 through an output buffer circuit 117 that is configured of a CML circuit at the time of testing. In a reception-side circuit part 102, a determining circuit 135 compares the amplitude of the input signal 131 with each of a plurality of reference voltages Vref1 to Vrefn in comparators 1321 to 132n to obtain a comparison result. And, a voltage controlling circuit 119 of a transmission-side circuit part 101 makes the setting of the amplitude by appropriately controlling a constant current value of the CML circuit, thereby enabling the low consumption power to be realized.

Abstract: An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit component coupled to the drive component. The latch may further include a reset threshold component coupled to the drive component for inhibiting oscillation of the drive component, and/or a latch component for passing the present state of the input signal to the output signal when configured as the repeater state and for maintaining the previous state of the output signal during transitions of a clock signal when configured as the latch state.

Abstract: A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal.

Abstract: An adaptive output driver has a number of transistors connected in series between a power supply and a ground. An adaptive bias input is coupled to a gate of one of the transistors.

Abstract: Circuits, methods, and apparatus for limiting voltages received by devices in input/output cells to less than the device's breakdown voltage. An exemplary embodiment of the present invention provides an input/output cell having one or more clamp diodes and resistors configured to limit voltages seen by the gates of the devices in the input/output cell. In one embodiment, the clamp diodes are on-chip, while the resistors are off-chip. In a specific embodiment, the clamp diode is connected between an input pad for the input output cell and a supply voltage VCC, while a resistor is off-chip and in series with the input pad. In another specific embodiment, a series of clamp diodes are coupled between ground and an input pad, while a resistor is off-chip and in series with the input pad. In another embodiment, the clamp diode or diodes may be programmably or selectively disconnected. These clamp diodes may be disabled to protect against latch-up.

Abstract: Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment control signal holding circuit and a monitor circuit. The replica resistor control counter counts up and down based on the comparison result by the comparator to output a control signal to the replica resistor. The resistor-under-adjustment control signal holding circuit holds a control signal that is delivered to the terminal resistor.

Abstract: A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of tolerating an overvoltage, sustaining an electrical connection to an elevated voltage level, and producing an output voltage at an indigenous supply level. An initial pullup drive circuit is coupled to the plurality of output drive devices and produces an initial elevated drive voltage to the plurality of output drive devices. A sustain pullup circuit is coupled to the plurality of output drive devices and produces a sustained output voltage at the indigenous supply level.

Abstract: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.

Abstract: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately with a change of the system, which enables the applied range of the products to be extended.

Abstract: A source follower includes first through third switches, first and second transistors, and a first capacitor. The first switch is used to determine whether or not to couple the source of the first transistor with an input signal. The second switch is used to determine whether or not to couple a gate and a drain of the first transistor with a first voltage. A first end of the first capacitor is coupled with a first control signal, and a second end of the first capacitor is coupled to the drain of the first transistor and a gate of the second transistor. The third switch is used to determine whether to or not couple a drain of the second transistor with the first voltage, and a source of the second transistor serves as an output of the source follower.

Abstract: A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.

Abstract: A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.

Abstract: A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.

Abstract: An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Abstract: In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.

Abstract: A low voltage differential signal (LVDS) transmitter with output power control. Internal sensing circuitry monitors output current flow through the termination impedance. When a proper termination impedance is not connected to the output, the resulting improper output current flow (e.g., zero output current when no termination impedance is connected) is detected by the sensing circuitry, which causes the supply current to the output driver circuitry to be reduced. Additionally, further in response to such detection of improper output current flow, the sensing circuitry can cause the output voltage to be limited, e.g., clamped, at a predetermined maximum magnitude.

Abstract: The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signal and the latch output signal, in which the pull-up circuit increases an output voltage of the output driver circuit from a ground level to a first level when the preset enable signal is at a low level and the latch output signal is at the high level.

Abstract: A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device.

Abstract: A semiconductor integrated circuit according to the invention has a plurality of output transistors connected to an output terminal through which output data is outputted, and an impedance control circuit and a slew rate control circuit. The impedance control circuit generates control signals specifying output transistors to be turned on when the output data is output, from among the plurality of output transistors. The slew rate control circuit generates, according to the control signals, drive signals driving the output transistors to be turned on, and variably sets respective delay times of the drive signals according to the control signals.

Abstract: A switching control circuit of synchronous rectification type that is capable of reducing dead time is obtained. Upon detection that an output potential rises above VDD-Va, a first sensor outputs an H signal to a first input terminal of a first NOR circuit, and the first NOR circuit outputs an L signal to a second input terminal of a second NOR circuit, and the second NOR circuit outputs an H signal to a first gate driving circuit. A PMOS is thereby turned on. Upon detection that the output potential falls below GND+Vb, a second sensor outputs an L signal to a first input terminal of a first NAND circuit, and the first NAND circuit outputs an H signal to a second input terminal of a second NAND circuit, and the second NAND circuit outputs an L signal to a second gate driving circuit. An NMOS is thereby turned on.

Abstract: A TOP level switch for use in a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The TOP level shifter transmits an input signal from drive logic to a TOP driver. In this case, the TOP level shifter is designed as an arrangement of an UP and a DOWN level shifter path, as well as a downstream signal evaluation circuit. In the associated method for transmission of this input signal, the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN, or both, level shifter paths emit a signal to the respectively associated input of the signal evaluation circuit.

Abstract: An apparatus including a bias voltage generator and one or more cascode drivers. Each of the one or more cascode drivers may include a plurality of cascode transistors. The bias voltage generator may control the cascode bias voltages provided to the cascode transistors based on a plurality of programmable control bits received by the bias voltage generator. The received plurality of programmable control bits may include a first set of programmable control bits, which may be used to control the magnitude of the cascode bias voltages, and a second set of programmable control bits, which may be used to control the stability of the cascode bias voltages.

Abstract: A CMOS Output Buffer providing controlled output impedance includes three internal sections each of which provides a impedance control for a corresponding region of the output V-I characteristics of deep linear, deep saturation and transition regions. Each internal section includes controlled current sinks/current sources enabled to provide a precise control over the DC impedance of the driver across the PAD voltage range.

Abstract: A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.

Abstract: A high voltage reception terminal is formed in a semiconductor integrated circuit without increasing the number of manufacturing processes and the manufacturing cost. A transfer gate configured from a NMOS, which is the high withstand voltage transistor, and a pull-up resistor are formed. An input terminal of the transfer gate is connected to the high voltage reception terminal and an output terminal of the transfer gate is connected to a CMOS inverter through an input resistor. One end of the pull-up resistor is connected to the output terminal of the transfer gate and the other end of the pull-up resistor receives source voltage VDD (5V). The transfer gate lowers the inputted high voltage VX (VX>VDD) to VDD-Vt1?. The pull-up resistor biases the voltage at the output terminal of the transfer gate to VDD and boosts the voltage at the output terminal that has been lowered by the transfer gate to about VDD.

Abstract: A semiconductor integrated circuit having a plurality of ultrasound pulsers corresponding to a plurality of respective channels, and integrally formed on a small area. The ultrasound pulsers each include a MOSFET gate drive circuit in which an input voltage pulse is converted into a current pulse, and the current pulse is converted again into a voltage pulse on the basis of a high potential side voltage +HV, and a low potential side voltage ?HV, applied to a transducer drive circuit, and in which a voltage level shift in the input voltage pulse is attained, and a voltage pulse swing is generated by the MOSFET gate drive circuit on the basis of the high potential side voltage +HV, and the low potential side voltage ?HV. The MOSFET gate drive circuit is DC-coupled with the transducer drive circuit.

Abstract: There is provided a reduced current input buffer circuit. More specifically, in one embodiment, there is provided an input buffer circuit comprising an input buffer that is adapted to draw an operating current, means for providing a first portion of the operating current to the input buffer, and means for providing a second portion of the operating current to the input buffer if the input buffer is expecting data.

Abstract: An output driver of a semiconductor memory device is capable of controlling falling and rising edges of an output data. The output driver prevents the first output data form being relatively deteriorated compared with other output data in case that the output data are terminated centering around a predetermined voltage level. The output driver includes a pull-up driver for pull-up driving an output terminal in response to a pull-up control signal, a pull-down driver for pull-down driving the output terminal in response to a pull-down control signal, a first acceleration driver for accelerating the pull-up control signal, and a second acceleration driver for accelerating the pull-down control signal, wherein the first and second acceleration drivers are activated when a first data is outputted.

Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.

Abstract: An output driver having an output that is not dependant on the variation of the voltage level of a variable supply voltage. The output driver, having at least two power supply voltages and which is not influenced by the variation of the voltage level of a variable power supply, leads to a constant output slew rate.

Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

Abstract: A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device.

Abstract: A delay circuit includes: a current control circuit which has n (n is 1 or larger natural number) control pins and a first output line, and is capable of controlling current outputted from the first output line in response to n control signals inputted to the corresponding n control pins; a current mirror circuit connected with the first output line to produce current mirror current from the current and output the current mirror current from a second output line; a first active element having a gate pin and an input pin, the gate pin is connected with the second output line, and the input pin is connected with the first voltage line; a second active element having a gate pin and an input pin, the gate pin is connected with the first output line, and the input pin is connected with the second voltage line; and an inverter circuit having third and fourth active elements connected in series between an output pin of the first active element and an output pin of the second active element.

Abstract: There is provided a LVDS driver arranged to receive an input signal which switches between two voltage levels. The driver comprises a pre-emphasis block (405) for generating a pre-emphasis signal having a first voltage level for a time period T1 after each switch of the input signal, and a second voltage level at all other times, a differential pair of outputs for generating a differential output voltage across a load resistor (RI); and a driver circuit (401) comprising two parallel branches, each branch being connected to one output and each branch being arranged to receive the pre-emphasis signal.

Abstract: A line driver circuit for stabilizing a signal that is output through a transmission line, wherein the line driver circuit receives a first signal having a first swing width corresponding to a difference between a first voltage and a second voltage, creates a second signal having a second swing width less than the first swing width, and outputs the second signal through a transmission line. The line driver circuit includes: a pull-up circuit that pulls up the second signal to a high level; a pull-down circuit that is connected to the pull-up circuit and pulls down the second signal to a low level; and an initializing circuit that is connected to a node of the transmission line, outputs a signal having a voltage of the low level or the high level to the node of the transmission line, and initializes the voltage at the node of the transmission line to the low level or the high level.

Abstract: A switched current source has a first voltage source, a second voltage source, and a third voltage source. A first transistor has a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source. A second transistor has drain, gate and source terminals. The drain terminal of the second transistor is coupled to the gate terminal of the first transistor. The source terminal of the second transistor is coupled to the source terminal of the first transistor. The gate terminal of the second transistor is coupled to the first voltage source. A third transistor has drain, gate and source terminals. The drain terminal of the third transistor is coupled to the gate terminal of the first transistor. The source terminal of the third transistor is coupled to the second voltage source. The gate terminal of the third transistor is coupled to the first voltage source.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A driving device and driving method for controlling electric power to a load is provided. The driving device controls switching operations of switching elements by setting a first duration in which electric power is supplied to the load and by setting a second duration in which the load is floated without electric power. The driving device feeds back an output signal outputted from output terminals of the load, receives an input signal, and compares the fed back output signal with the input signal to detect an error. The driving device also generates an error suppression signal to correct the detected error and controls the switching operation of the switching elements based on the error suppression signal.

Abstract: A semiconductor device comprises a driver provided for a semiconductor element having a control electrode to which a drive voltage is applied, the semiconductor element being switched between the conduction state and the non-conduction state based on the drive voltage, the driver operative to apply the drive voltage to the control electrode; a detector operative to supply a voltage detection signal oscillating at a certain frequency to the control electrode to detect a first voltage having a certain relation to a voltage applied to the semiconductor element; and a controller operative to control the detector based on the first voltage detected at the detector.

Abstract: The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry.