Abstract: A half bridge gate driving circuit for providing gate driving circuits in a bi-hecto celcius (200 degrees celcius) operating environment having multiple functions including combinations of multiple level logic inputs, noise immunity, fault protection, overlap protection, pulse modulation, high-frequency modulation with transformer based isolation, high-frequency demodulation back to pulse width modulation, deadtime generator, level shifter for high side transistor, overcurrent protection, and undervoltage lockout.

Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

Abstract: Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.

Abstract: A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type MOS transistors, an output terminal which is a connection node between the P-type MOS transistor and one of the two or more N-type MOS transistors connected to the P-type MOS transistor, and one or more capacitors connected to the output terminal. The drive capability of the P-type MOS transistor is higher than the overall drive capability of the two or more N-type MOS transistors connected together in series. Therefore, a semiconductor integrated circuit is provided in which fluctuations in the delay time of a delay circuit caused by variations in transistor characteristics can be reduced.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence electromagnetic interference in systems in which the transmitter is used.

Abstract: Techniques for overcoming many of the speed limitations of switching a gated device while protecting the device from damage provide a dynamic driving voltage to the gate of the device being switched. This dynamic voltage provides a way to overcome the complex impedances between the drive point and the actual gate allowing faster switching speeds. This dynamic driving voltage is provided by starting with a fixed amount of charge at a higher initial potential. The fixed charge and voltage are chosen so as not to exceed the device's specified maximum gate current or the device's maximum voltage between the gate and the source (punch-through voltage).

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: An inductive load driving device includes a first switching element, a second switching element, a counter current regeneration circuit, and a circuit element protection circuit. The first switching element is coupled between an output terminal of the power circuit and one end of the inductive load. The second switching element is coupled between the other end of the inductive load and a ground terminal. The counter current regeneration circuit is configured to supply to the output terminal of the power circuit, a counter current output from the other end of the inductive load when the first and second switching elements are in off-state. The circuit element protection circuit is configured to turn on the second switching element when a value of the output voltage of the power circuit becomes equal to or more than a threshold value.

Abstract: A device having a voltage mode driver with tunable amplitude and resistance that supports a predetermined output resistance and output amplitude is described herein. The voltage mode driver includes multiple configurable drivers. The voltage mode driver is controlled by a control module. Resistance tuning is controlled by the number of active configurable drivers and amplitude tuning is controlled by setting the high or low drive state of each active configurable driver. The slew rate of the device is controlled by delaying the setting of the high or low drive state of an active configurable driver by a predetermined interval.

Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

Abstract: A power interface circuit of a contact integrated circuit (IC) card reader is provided.

Abstract: The present invention provides a semiconductor integrated circuit capable of achieving high voltage. The proposed semiconductor integrated circuit includes a first node [VOUT] connected to a first potential node [VDD], and a first n-channel transistor [NT1] and a second n-channel transistor [NT2] serially connected between a first node [VOUT] and a second potential node [VSS] of a lower potential than the first potential node. One end of NT1 is connected to the second potential node [VSS], the other end thereof is connected to one end of the second n-channel transistor [NT2], a gate terminal thereof is connected to a second node [VIN], the other end of NT2 is connected to the first node [VOUT], and a gate terminal thereof is connected to a first intermediate range potential [VM1] positioned between the first potential node [VDD] and the second potential node [VSS].

Abstract: A limiter circuit in a voltage controlled oscillator (VCO) includes a first control circuit, a second control circuit and a driving circuit having a pull-up transistor and a pull-down transistor. The first control circuit generates a first driving control signal for controlling the pull-up transistor based on an AC input signal and a first DC bias voltage. The second control circuit generates a second driving control signal for controlling the pull-down transistor based on the AC input signal and a second DC bias voltage. The driving circuit generates an output signal based on the first driving control signal and the second driving control signal. The output signal swings between a first voltage at the pull-up transistor and a second voltage at the pull-down transistor.

Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the re-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of th

Abstract: An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.

Abstract: A semiconductor device includes a first internal terminal, a first transistor, a second transistor, an oscillator including an output terminal to output a clock signal, and a comparator coupled to a first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to a second reference potential, an external terminal being connectable to the first internal terminal, and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal. Each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal. The first transistor and the second transistor exclusively operate according to the clock signal.

Abstract: When a transmission signal is detected as having been changed from a high level to a low level, two transmission lines are connected for only a predetermined time through a diode by a first transistor and a second transistor. The diode is arranged such that its forward direction is from a high-side transmission line to a low-side transmission line. The diode turns on, when a potential of the high-side transmission line becomes higher than that of the low-side transmission line by ringing and a potential difference therebetween exceeds a forward drop voltage of the diode. As a result, a peak wave level of a positive side in the ringing is limited to the forward drop voltage of the diode.

Abstract: A resonant tank circuit has an output port configured to be coupled to a load comprising a current-controlled semiconductor device, such as a diode, thyristor, transistor or the like. A voltage generator circuit is configured to intermittently apply voltages to an input port of the resonant tank circuit in successive intervals having a duration equal to or greater than a resonant period of the resonant tank circuit. Such an arrangement may be used, for example, to drive a static switch.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: A differential output circuit is controlled according to its mode of operation. While in the first mode, the differential output circuit controls a current flow through a variable current source according to an impedance of the variable current source, and while in the second mode, the differential output circuit compares a voltage at a monitored node and a reference voltage and controls the current flow through the variable current source to make the voltage at the monitored node to be equal to the reference voltage.

Abstract: An exemplary method and a control circuit are disclosed for controlling a power semiconductor component by producing a control signal (Ucin) for controlling the component, forming a second control signal (Ucout) in the potential of the controlled component from the control signal (Ucin), measuring a current flowing through the component, and comparing the measured current with a set limit. A fault signal (Ufault) having a logical state is provided on the basis of the comparison between the measured current and the set limit, producing a component control signal (Uave) from the fault signal (Ufault) and the second control signal (Ucout). If a fault is indicated, the component control signal has a value between high and low states, and otherwise the state of the component control signal (Uave) equals the state of the second control signal (Ucout).

Abstract: A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than one which may comprise n?1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n?1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n?1th discharging time period through the respective n?1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

Abstract: Methods, circuits, and systems for termination calibration are provided. Differential input buffer circuitry is used to compare a signal level at an input/output pad and a first reference signal level. Control circuitry is used to control a controllably variable impedance based on the output of the differential input buffer circuitry. Optionally, second differential input buffer circuitry is used to compare the signal level at the input/output pad to a second reference signal level. The control circuitry is used to control the controllably variable impedance based on the output of both the first and the second differential input buffer circuitry.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes core circuits having an operational mode and a power saving mode, and at least a pad module. The pad module includes a pad, a switchable pull-up module configured to pull up a voltage on the pad when the switchable pull-up module is switched on, a switchable pull-down module configured to pull down the voltage on the pad when the switchable pull-down module is switched on, and a control module configured to control the switchable pull-up module and the switchable pull-down module according to a detection of the voltage on the pad when the core circuits enter the power saving mode.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Abstract: A semiconductor device includes first and second power elements and first and second driving circuits. The semiconductor device also includes a resistor having a first end connected to the first power element and a second end connected to the first driving circuit. Furthermore, the semiconductor device includes a switching element connected between the first driving circuit and the first end of the resistor, and turned ON and OFF. When a first input signal is an OFF signal, the first driving circuit causes the first power element to become turned OFF, and when the first input signal is an OFF signal or when a second input signal is an ON signal, the switching element is turned ON.

Abstract: A synchronous driving circuit in the arts may cause a short through pheromone when a duty cycle of a duty cycle control signal is too short. The present invention sets a delay time with a suitable period when the duty cycle of the duty cycle control signal is too short to avoid the short through phenomenon.

Abstract: A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs.

Abstract: An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor.

Abstract: A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).

Abstract: A charging current is supplied to the gate (control terminal) of a driven switching device during an on-state command interval, for raising the gate voltage to an on-state value. Otherwise, discharging of the gate capacitance is enabled, for decreasing the gate voltage to an off-state value. A second switching device is connected between the gate and a circuit point held at the off-state voltage value, and is maintained in an on state while the gate discharging is enabled. At a first time point, the gate voltage rises above a threshold value. At a second time point, a voltage detection circuit detects that that the gate voltage has risen above the threshold value, causing the second switching device to be set in the off state. It is ensured that the delay between the first and second time points is shorter than a minimum duration of an on-state command interval.

Abstract: A high-side switch control circuit is provided. The high-side switch control circuit includes an on/off transistor, a bias resistor, a zener diode, a level-shifting transistor, and a current source. The on/off transistor operates as a switch. The bias resistor is coupled to turn off the on/off transistor. The zener diode is coupled to clamp the maximum voltage of the on/off transistor. The level-shifting transistor is coupled to turn on the on/off transistor. The current source is coupled to the level-shifting transistor. The current source limits the maximum current of the level-shifting transistor.

Abstract: A driver circuit having: a voltage controller (UCD), which delivers a direct voltage (UPD) to a controller output; a direct voltage converter (DC/DC), to which is applied on the primary side the direct voltage (UPD) delivered from the voltage controller, and which converts such into a direct voltage (U?PD) available on the secondary side; and an end stage operated by means of said direct voltage (U?PD), which converts a control signal (sinexc—A) lying on a signal input into a driver signal (iexc) for the measuring transducer. The direct voltage (U?PD) available on the secondary side of the direct voltage converter (DC/DC) has, in such case, a magnitude which is always smaller than a magnitude of the direct voltage (UPD) delivered by the voltage controller, and the driver signal (iexc) has an electrical power (Pexc), which is higher than an electrical power (Psin) of the control signal (sinexc—A).

Abstract: A non-overlap circuit includes a first delay circuit configured to receive a first input signal and output a first control signal to a driver circuit, sensing circuitry configured to sense a current generated in response to the first control signal coupled through bulk semiconductor of a semiconductor substrate and produce a feedback signal response, and a second delay circuit. The second delay circuit configured to receive the feedback signal from the sensing circuitry and a second input signal and output a second control signal to the driver circuit based on the sensed feedback signal and the second input signal.

Abstract: A high voltage drive circuit includes an edge detector for generating an edge detection signal by detecting edges of a first high side input signal and a first low side input signal, the edge detector providing a high side delay signal and a low side delay signal by delaying the first high side input signal and the first low side input signal, a dead time generator for generating a dead time signal indicating a preset dead time in response to the edge detection signal, and a driver comprising a drive signal generator for providing a high side output signal and a low side output signal by inserting the preset dead time based on the dead time signal into the high side delay signal and the low side delay signal.

Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

Abstract: A buffer circuit includes a first node that receives a first voltage, a second node, an output node that receives the first voltage, a first transistor coupled between the first node and the second node, the first transistor having a backgate receiving the first voltage, and a second transistor coupled between the second node and the output node, the second transistor having a backgate receiving a second voltage being higher than the first voltage.

Abstract: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended.

Abstract: Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for, the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal.

Abstract: Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively.

Abstract: An output driver includes a control signal generation unit configured to generate a control signal in response to a driving strength signal and a power supply voltage level, and a driving signal generation unit configured to buffer a pre-driving signal and generate a driving signal for driving an output data, wherein a driving strength of the driving signal is adjusted in response to the control signal.

Abstract: A drive circuit with a circuit for transmitting a signal from a primary side having a first ground to a secondary side having a second ground. The transformer has capacitive coupling between the primary and secondary sides. The transformer has an ON transmission branch and an OFF transmission branch, which each have a first partial branch and a second partial branch. Capacitive coupling between the primary and secondary sides is effected in each partial branch by high-voltage capacitors. In the inventive method, in each transmission branch, the signal generates a current flow through a first HV capacitor of a first partial branch and an inverse current flow through a second HV capacitor of a second partial branch. This respective current flow is detected on the secondary side and is supplied to an evaluation circuit common to the two partial branches and reconstructs the primary-side input signal on the secondary side.

Abstract: A hybrid power device is formed of a normally-on type SiC-JFET and a normally-off type Si-MOSFET, which are connected in cascode with a source of the SiC-JFET and a drain of the Si-MOSFET being connected to each other thereby forming a hybrid power FET. A gate of the SiC-JFET and a source of the Si-MOSFET are connected via a switching speed regulating resistor. A capacitor is connected to the switching speed regulating resistor in parallel to control a switching speed to a first speed in a former part of the switching period of the hybrid power FET and to a second switching speed in a latter part of the switching period. The second switching speed is lower than the first switching speed.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and output a signal at anode. The second inverter receives another input outputs at the same output node. The current source is serially coupled to the output node via a first switch, the first switch receiving an input at the first input.