Abstract: Methods for increasing a signal frequency include generating two or more signals having a fundamental mode and one or more harmonics; phase shifting bifurcated components of the two or more signals in transmission lines; and combining the bifurcated components to create an output signal that cancels a fundamental mode, a second harmonic, and a third harmonic in the signals to produce a frequency-multiplied output signal.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N?2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed, saves area, and reduces energy consumption.

Abstract: A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.

Abstract: In accordance with an embodiment, a frequency doubling circuit includes a differential transistor pair coupled to an input port of the frequency doubling circuit, a first differential cascode stage having an input coupled to an output of the differential transistor pair, a plurality of first impedance elements coupled between the output of the differential transistor pair and the input of the first differential cascode stage, and an output combining network coupled between the first differential cascode stage and an output port of the frequency doubling circuit.

Abstract: A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number “n” multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.

Abstract: A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner.

Abstract: A multiplier circuit and wireless communication apparatus that adjust an output level of a desired multiple wave to a desired range is provided. The multiplier circuit includes a multiple wave output unit configured to receive an input signal of a predetermined frequency, to output a multiple wave that is a predetermined multiple of the input signal, and control harmonic distortion associated with the output of the multiple wave based on a gate-source voltage; and a controller configured to adjust the gate-source voltage.

Abstract: A circuit includes an oscillation generation circuit, a distribution circuit, and a transceiver circuit. The oscillation generation circuit is configured to generate a first oscillation signal having a first frequency. The distribution circuit includes a voltage to current stage, a transmission portion and a current to voltage stage. The voltage to current stage is configured to receive the first oscillation signal, and convert the first oscillation signal into a current form. The transmission portion is configured to transmit the first oscillation signal in the current form. The current to voltage stage is configured to receive the first oscillation signal in the current form and generate a second oscillation signal having a sub-harmonic frequency of the first frequency, such as half of the first frequency. The transceiver circuit is configured to operate in a frequency band responsive to the second oscillation signal.

Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.

Abstract: Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.

Abstract: A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%.

Abstract: A multiplier-divider circuit for signal process according to the present invention comprises a digital-to-analog converter, a first counter, a second counter, an oscillation circuit, and a control-logic apparatus. The digital-to-analog converter generates an output signal of the multiplier-divider circuit in accordance with the value of an input signal and a first signal. The first counter generates the first signal in response to a clock signal and the duty cycle of the input signal. The second counter generates a second signal in response to the clock signal and the period of the input signal. The oscillation circuit generates the clock signal in accordance with a third signal. The control-logic apparatus generates the third signal in response to the second signal and a constant. The first signal is correlated to the duty cycle of the input signal. The second signal is correlated to the period of the input signal.

Abstract: A frequency multiplier for generating an output signal having a frequency N times the input signal, with N equal to or greater than 3, the frequency multiplier including a phase splitter circuit responsive to the input signal for generating N signals with phase differences, and a mixer circuit responsive to the N signals of the phasor circuit for providing an output signal having a frequency N times the input signal.

Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.

Abstract: The present invention provides a frequency multiplier apparatus. The frequency multiplier apparatus includes an injection-locked frequency multiplier and a frequency-to-control signal converter. The injection-locked frequency multiplier outputs an output signal having a first frequency in response to an input signal having a first basic frequency. The frequency-to-control signal converter provides a first control signal to the injection-locked frequency multiplier in response to the input signal. The injection-locked frequency multiplier adjusts the first frequency to a second frequency in response to a change of the first control signal when the first basic frequency is changed to a second basic frequency.

Abstract: A multiplier circuit including; a 90 degrees coupler that divides an input signal into a first input signal and a second input signal of which phase difference of a base wave is 90 degrees; a first transistor that receives the first input signal and outputs a first output signal including at least a doubled wave and a tripled wave of the first input signal; a second transistor that receives the second input signal and outputs a second output signal including at least a doubled wave and a tripled wave of the second input signal; and a combiner that restrains leakage of the first output signal or the second output signal from one of the first transistor and the second transistor to the other, combines the first output signal and the second output signal, and outputs an output signal of the tripled wave.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.

Abstract: A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal.

Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

Abstract: There is provided a mixing circuit in which a rise of the consumption current can be suppressed while decreasing a non-linear component. The mixing circuit includes: an input unit 803 including a grounded-gate MOS transistor M1 with a source into which an input signal is input, and a grounded-source MOS transistor M2 with a gate into which the input signal is input; a frequency converter 802 for converting frequencies of a first current signal output from the grounded-gate MOS transistor M1 and a second current signal output from the grounded-source MOS transistor M2, and for generating a third current signal and a fourth current signal; a load MOS transistor M7, with a gate and a drain connected, for receiving a third current signal; and a load MOS transistor M8, with a gate and a drain connected, for receiving a fourth current signal.

Abstract: A controller for an SMPS is disclosed. The controller applies a frequency jitter to the SMPS to reduce Electromagnetic Interference (EMI) and/or audible noise. A second input variable is multiplied by a correlated jitter signal, in order to compensate the output power for the frequency jitter. A corresponding method is also disclosed. Since the jitter compensation occurs within the controller, the method is particularly suitable for controllers operating under different control modes for different output powers (or other output criteria). The multiplicative compensation is applicable across a wide range of converter types.

Abstract: A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%.

Abstract: According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of the plurality of stages. The controller simultaneously receives comparison results of the plurality of phase comparators, determines the number of stages that generate the clock of which a phase is synchronized with a phase of the reference clock from among the delay elements of the plurality of stages, and selects the number of output stages from among the delay elements of the plurality of stages based on the determined number of stages so that a delay clock having a demanded delay amount with respect to the reference clock is output.

Abstract: A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

Abstract: Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.

Abstract: Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

Abstract: The invention discloses a mixer circuit (10, 20, 30, 410, 60) comprising a first mixer component (11, 21) with a first (13, 23) and a second (12, 22) input port for a first and a second input signal respectively and an output port (14, 24) for outputting a mixed signal. According to the invention, the mixer circuit (10, 20, 30, 410, 60) also comprises a transformer (15) which connects the first (13, 23) and second (12, 22) input ports of the mixer component (11, 21) inductively via an inverting coupling. In one embodiment, the mixer circuit (30, 410, 60) also comprises inputs for DC-bias of one (13) of the input ports and of the output port (14), as well as an impedance (31) as a filter at the output port.

Abstract: An input unit receives input of a clock signal having a voltage that varies continuously. A supply unit supplies a constant reference voltage. A selector outputs a clock signal having voltage that is changed alternately each time the voltage of the clock signal input from the input unit shifts across the reference voltage supplied from the supply unit. A calculating circuit outputs the exclusive-OR of the clock signal input from the input unit and a clock signal output from the selector.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.

Abstract: A signal generator for coupling to a concealed conductor including a first oscillator configured to generate a first waveform having a first frequency, a first terminal coupled to the first oscillator through a first band pass filter configured to pass signals of the first frequency, a second oscillator configured to generate a second waveform having a second frequency, and a second terminal coupled to the second oscillator through a second band pass filter configured to pass signals of the second frequency.

Abstract: A programmable waveform generator, comprising: a controllable waveform generator configured to generate an initial bandwidth signal having an initial frequency bandwidth; a tone generator configured to generate a plurality of tone signals, each tone signal having a different frequency; a first bandwidth-multiplying circuit, including a first mixer having a first input port configured to receive the low-bandwidth signal; a first switch configured to choose one of the plurality of tone signals or a phase shifted version of one of the plurality of tone signals and output the chosen signal as a first chosen tone; a controller configured to control the operation of the bandwidth multiplying block, wherein the first mixer is further configured to receive the first chosen tone at a second input port, wherein the first mixer is further configured to mix the initial bandwidth signal and the first chosen tone to generate a first bandwidth signal at an output port, the first bandwidth signal having a first frequency ban

Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: A frequency multiplier oscillation circuit (and a method of multiplying a fundamental wave) includes an oscillation unit, a multiplication unit, and a fundamental wave component removal unit. The oscillation unit outputs a fundamental wave. The multiplication unit multiplies the fundamental wave to output the multiplied wave. The fundamental wave component removal unit cancels a fundamental wave component included in the multiplied wave based on the fundamental wave that is output from the oscillation unit to output the multiplied wave to an output terminal.

Abstract: A signal generating circuit (or a generator) of an embodiment includes an oscillator to produce an oscillation signal controlled in oscillating frequency by an analog control signal. The circuit includes: a digital phase detector detecting phase information of the oscillation signal and outputting digital phase information; a first differentiator differentiating the digital phase information and outputting digital frequency information; a comparator comparing a frequency setting code setting the oscillating frequency with the digital frequency information and outputting digital frequency error information; and a low-pass filter removing a high-frequency component of the digital frequency error information.

Abstract: A frequency multiplier circuit, comprising a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, the first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in the current conduction paths of the first differential pair of amplifier elements produces a voltage difference across the first and second nodes at a frequency which contains a harmonic of the input frequency, and a second stage including a second differential pair of amplifier elements coupled at the harmonic of the input frequency with the first and second nodes to amplify differentially the voltage difference and produce an output signal at the harmonic of the input frequency.

Abstract: A circuit includes an oscillation generation circuit, a distribution circuit, and a transceiver circuit. The oscillation generation circuit is configured to generate a first oscillation signal having a first frequency. The distribution circuit includes a voltage to current stage, a transmission portion and a current to voltage stage. The voltage to current stage is configured to receive the first oscillation signal, and convert the first oscillation signal into a current form. The transmission portion is configured to transmit the first oscillation signal in the current form. The current to voltage stage is configured to receive the first oscillation signal in the current form and generate a second oscillation signal having a sub-harmonic frequency of the first frequency, such as half of the first frequency. The transceiver circuit is configured to operate in a frequency band responsive to the second oscillation signal.

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, including one or more of the following: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals by operating on the frequency reference clock signal, the plurality of frequencies signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator and selecting ones of said plurality of frequency signals and transmitting said selected ones of said plurality of frequency signals; and a plurality of differential units, each for receiving one of said selected ones of said plurality of frequency signals, each for applying a differential signal to said selected ones of said plurality of frequency signals, and each for adding time stamps to the selected ones of said plurality of frequency signals and outputting respective time sta

Abstract: Frequency multipliers having corresponding methods and multifunction radios comprise: N multipliers, wherein N is an integer greater than one; wherein the multipliers are connected in series such that each of the multipliers, except for a first one of the multipliers, is configured to mix a periodic input signal with an output of another respective one of the multipliers; wherein the first one of the multipliers is configured to mix the periodic input signal with the periodic input signal.

Abstract: A programmable waveform generator, comprising: a controllable waveform generator configured to generate an initial bandwidth signal having an initial frequency bandwidth; a tone generator configured to generate a plurality of tone signals, each tone signal having a different frequency; a first bandwidth-multiplying circuit, including a first mixer having a first input port configured to receive the low-bandwidth signal; a first switch configured to choose one of the plurality of tone signals or a phase shifted version of one of the plurality of tone signals and output the chosen signal as a first chosen tone; a controller configured to control the operation of the bandwidth multiplying block, wherein the first mixer is further configured to receive the first chosen tone at a second input port, wherein the first mixer is further configured to mix the initial bandwidth signal and the first chosen tone to generate a first bandwidth signal at an output port, the first bandwidth signal having a first frequency ban

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Abstract: A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

Abstract: A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.

Abstract: The present invention provides a method for identifying a specific number of communicating points having relatively smallest accumulated path values from a plurality of transmitting points for a receiving point in a communication system. The method includes steps of: (a) defining a first coordination of each of the plurality of transmitting points and the receiving point on a complex plane; (b) transferring the first coordination of the receiving point to a second coordination thereof, in which the second coordination of the receiving point is near an origin of the complex plane; and (c) identifying the specific number of transmitting points having relatively smallest accumulated path values based on the second coordination of the receiving point.

Abstract: An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay introduced by the N delay elements is M/2. The integrated circuit also includes a plurality of inverters, each coupled to an output of one of the N delay elements, where the plurality is less than N. The integrated circuit also includes a phase detector coupled to the input node and an inverted Nth phase-shifted signal. The integrated circuit also includes a charge pump coupled to the phase detector and the delay elements.