Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices. The clock multiplier circuit includes ring oscillator which oscillates at a higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain a count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to the input signal (1, 2) by a quarter of the latter's cycle period is generated and the output signal (11) is then generated as the difference between the rectified input signal (1, 2) and the rectified delayed signal (3, 4). The input signal (1, 2) and the delayed signal (3, 4) are advantageously rectified by using differential signals each comprising a positive component signal (1, 3) and a negative component signal (2, 4). A respective one of two transistors connected in parallel is driven by a positive component signal (1, 3) and a negative component signal (2, 4) in such a way that a positive half-wave causes the relevant transistor (5-8) to conduct and the relevant transistor (5-8) blocks in a negative half-wave.

Abstract: A clock multiplier capable of modulating the duty cycle of the output clock comprises a first clock multiplication circuit, an inverter, a first low pass filter, a second low pass filter and an amplifier, the first multiplication clock being operative to multiply the frequency of an input clock, the inverter being operative to invert the input clock, the first low pass filter receiving the output clock of the inverter for being charged or discharged, the second low pass filter receiving the output clock of the first clock multiplication circuit for being charged or discharged, the amplifier being operative to compare the output voltages of the first low pass filter and the second low pass filter to perform a feedback control, so as to modulate the duty cycle of the output clock of the first multiplication clock to approach 50%.

Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.

Abstract: An apparatus for generating quadrature phase signals in a half-rate data recovery circuit, which is adapted to generate a first and a second clock signals having the same frequency and being 90 degrees out of phase with each other. The apparatus for generating quadrature phase signals mainly comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates, based on a region control signal, a pair of phase region boundaries for the first clock signal as well as a pair of phase region boundaries for the second clock signal by using a plurality of reference clock signals. The first and second phase interpolators perform, based on a position control signal, weighted average processes for the two pairs of phase region boundaries, respectively, to thereby obtain the first and the second clock signals.

Abstract: Provided is a frequency multiplier including a delay circuit, an XOR gate, and a control circuit and a method of operating such a frequency multiplier to adjust the duty cycle of a clock signal. During operation of the frequency multiplier the delay circuit receives a first clock signal and generates a delayed clock signal. The XOR gate receives the first clock signal and the delayed clock signal, performs an XOR operation on the received signals and outputs a second clock signal that has a frequency that is a multiple of the first clock signal. The control circuit monitors the phase difference between the first clock signal and the delayed clock signal and outputs a control signal corresponding to the detected phase difference to the delay circuit to adjust the time delay applied to the first clock signal by the delay circuit.

Abstract: The present invention relates to an interface mechanism and particularly to an interface mechanism for interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency. The interface mechanism comprises a first input for receiving a relative real-time clock value from the real-time clock, and a second input for receiving an update value from the data processing circuit specifying a desired value for the real-time clock. Update logic is also provided for producing an absolute real-time clock value, the update logic being arranged in response to receipt of the update value to generate an offset value derived from the relative real-time clock value and the update value, the offset value then being applied to the relative real-time clock value to produce an updated absolute real-time clock value. The updated absolute real-time clock value is then output from the interface mechanism.

Abstract: A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.

Abstract: Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant when the clock signal is in its low level. The other integrator circuit charges and discharges its capacitor in the opposite manner to the one integrator circuit as to the level of the clock signal. An output circuit compares the output voltages of both integrator circuits with a reference voltage and raises the level of its output signal when either one of the output voltages drops below the reference voltage. The duty ratio of the circuitry is therefore little susceptible to the frequency of the input signal and power supply voltage.

Abstract: A rewritable memory (120) stores a plurality of regulation amounts (increase amounts and decrease amounts) related to values of signals (240b and 240c) (to give information about a difference amount between an oscillation frequency of a ring oscillator (110) and a desired frequency). A control circuit (131) selects one of the regulation amounts from the memory (120) corresponding to the values of the signals (240b and 240c) and increases or decreases a value of a counter (132) by the regulation amount thus selected. The oscillation frequency is regulated by the value of the counter (132).

Abstract: Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter.

Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: A clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: Radio system including mixer device and switching circuit and method having switching signal feedback control for enhanced dynamic range and performance. Radio apparatus including: local oscillator input port for receiving periodic sinusoidal local oscillator signal; drive circuit for generating a substantially square-wave two-voltage level switching signal including: phase splitter circuit, voltage potential isolation circuit, and square wave signal generation circuit; FET mixing device; input/output signal separation circuit; analog-to-digital converter; and feedback control circuit. Radio tuner apparatus including low-band signal processing circuit; high-band signal processing circuit including first mixer circuit operating as an up-frequency converter, amplifier circuit, second mixer circuit operating as a down-frequency converter, and feedback control circuit for adjusting a duty cycle of a mixer switching device; signal combining circuit and output processing circuit.

Abstract: An edge multiplier circuit comprises a chain of N phase-looped delay cells (130, 131, 132, 133, 134). An order of cells to be delayed is determined by action loops. A first action loop (116, . . . , 128) is utilized for values of j varying from 1 to N, each corresponding to a total delay equal to j times an elementary delay (Te) of a cell. The delay is applied to the chain of N delay cells. An action of the first loop comprises a second action loop (118, . . . , 127) for values of i varying from 1 to N, each corresponding to a rank of a cell in said chain. An action of the second loop calculates a delay error (a (j, i)) output from the cell of rank i relative to an ideal delay that distributes the total delay of the chain equally to each cell.

Abstract: A digital frequency doubler circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.

Abstract: A ferromagnetic film, which has an inherent resonant frequency, is disposed in a cavity resonator. An electromagnetic wave, which has an input frequency equal to the resonant frequency of the ferromagnetic film, is introduced to the ferromagnetic film from an orifice of the cavity resonator to generate a ferromagnetic resonance in the ferromagnetic film, and thus, multiply the input frequency of the electromagnetic wave.

Abstract: A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.

Abstract: Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively.

Abstract: A frequency multiplication circuit is disclosed. The circuit includes a ring oscillator formed of an even number of phase shifting stages. Each phase shifting stage provides a high frequency output comprised of harmonics of the oscillation frequency of the oscillator. An input signal having a first frequency is injected into a feedback node of the oscillator, thereby injection locking the oscillator to the input signal such that the oscillation frequency of the oscillator is equal to the first frequency. An output signal is extracted from two of the phase shifting stages. One of the harmonic frequencies may be isolated in the output signal, thereby providing a clean output at a multiple of the input frequency. When the circuit is operated at high frequencies, the output signal consists substantially of the second harmonic frequency and the circuit operates as a frequency doubler.

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Abstract: A numerically controlled oscillator that generates an accurate digital representation of a repeating waveform such as a sinusoidal wave. Based on the desired output frequency, multiple samples are calculated from multiple cycles of the repeating waveform. As samples are taken, they are stored in a memory location until a sufficient number of samples are accumulated. After the samples are accumulated, they are output in a specified order, which generates an accurate digital representation of a sinusoidal wave at the desired output frequency.

Abstract: An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier.

Abstract: A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired non-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL).

Abstract: A branching section provides a fundamental input wave signal SI of a frequency f to the gate of a FET 15A having a grounded source and the source of a FET 15B having an AC grounded gate, and a signal joining section synthesizes the output signals of the FETs 15A and 15B. An open stub 24 as an amplitude attenuating element is connected to a transmission line 19B of the signal joining section. The length of the open stub 24 is not an integral multiple of &lgr;/4, where &lgr; denotes the wavelength of the fundamental signal SI, and adjusted in simulation such that an amplitude difference between second harmonics included in the drain voltage signals SD1 and SD2 of the respective FETs 15A and 15B is reduced to almost zero. Although the open stub 24 itself is a phase compensating element, since the transfer characteristic of the FET 15B changes by connecting the open stub 24 to the transmission line 19B, the open stub 24 works as an amplitude attenuating element.

Abstract: It is intended to provide a compact circuit configuration used for a frequency multiplier device, suitable to selectively output among a plurality of multiplied frequencies, with less power consumption. The frequency multiplier device uses an input frequency signal f and an output multiplied signal nf to form original signals a and c, as well as phase shifted signals b and d that are phase shifted to ±&pgr;/2 from the original signals a and c, the signals are mixed in a mixer circuits 16 and 17 and summed in a summing amplifier 18 to generate an output frequency signal fOUT. The phase inverter circuit (differential amplifier circuit) 14 and selector circuit (SEL1) 33) controls the phase inversion of one of signals to selectively output one of mixed frequencies (n±1)f as the output frequency signal fOUT.

Abstract: A frequency doubler circuit implemented in an integrated circuit and having improved doubling performance is provided. The frequency doubler circuit including a phase shifter, a first buffer, a second buffer, a detect-control unit, a third buffer, a fourth buffer, a multiplier and an output buffer. The phase shifter outputs, in response to an input signal having a predetermined frequency, a first signal which is in phase with the input signal and a second signal which is out-of-phase from the input signal. The first buffer filters and buffers the first signal, and the second buffer filters and buffers the second signal. The detect-control unit detects a phase difference between the first and second signals in response to the first signal, the second signal, the output signal of the first buffer and the output signal of the second buffer, and outputs first and second control signals.

Abstract: A frequency multiplier circuit comprises: a source oscillator configured to generate a source oscillator signal using a crystal oscillator; and n frequency multiplier circuits (n is an integer which is 2 or more), each of which includes a 90° phase shifter circuit configured to shift the phase of an input signal by 90°, and a mixer configured to generate a doubled signal of the input signal on the basis of the input signal and an output signal of the 90° phase shifter circuit, wherein the n frequency multiplier circuits are cascade-connected, the source oscillation signal being inputted to a first stage frequency multiplier circuit of the n frequency multiplier circuits, and a final stage frequency multiplier circuit of the n frequency multiplier circuits outputting a signal having a frequency 2n times as high as the frequency of the source oscillation signal.

Abstract: It is intended to provide a compact circuit configuration used for a frequency multiplier device, suitable to selectively output among a plurality of multiplied frequencies, with less power consumption. The frequency multiplier device uses an input frequency signal f and an output multiplied signal nf to form original signals a and c, as well as phase shifted signals b and d that are phase shifted to ±&pgr;/2 from the original signals a and c, the signals are mixed in a mixer circuits 16 and 17 and summed in a summing amplifier 18 to generate an output frequency signal fOUT. The phase inverter circuit (differential amplifier circuit) 14 and selector circuit (SEL1) 33) controls the phase inversion of one of signals to selectively output one of mixed frequencies (n±1) f as the output frequency signal fOUT.

Abstract: A combination delay circuit for use in a frequency multiplier comprises a first delay circuit including a plurality of delay lines each having eight segments each effecting a unit delay time td, a latch array having 8 latch elements, one element disposed for each delay line, each receiving an output from a corresponding one of delay segments, and second through eighth delay circuits each having a single delay element effecting the unit delay time. The corresponding between the latch elements and the second through eighth delay circuits is such that delay times in the outputs of the third, fifth, seventh delay circuits are ¼, ½ and ¾, respectively, of the delay times in the output of the eighth delay circuit. The frequency multiplier having the combinational delay circuit multiplies the reference frequency by double, quadruple, and octuple.

Abstract: The edge multiplier circuit comprises a chain of N phase-looped delay cells (130, 131, 132, 133, 134).

Abstract: A cost-effective push-pull arrangement for distributing the power output of the signal from the mixing/local oscillator, so that the transistors are able to be modulated with the same power and with 180° phase shift, and so that, in spite of manufacturing tolerances of the transistor parameters, the signal is effectively decoupled from the other signal gates of the circuit.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired non-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL).

Abstract: A purpose of the present invention is to provide an economical frequency multiplier with a simple structure, wherein a frequency of an input signal can be multiplied with high accuracy and the frequency multiplier is widely applicable to a device in which a high accurate high frequency is required. The frequency multiplier comprises at least a differential signal generating circuit 11 for receiving a sinusoidal wave input signal and generating two signals of which a frequency is as same as that of the input signal and a phase different is 180° and a multiplier circuit 12 for multiplying two signals from the differential signal generating circuit 11 and generating a signal of which a frequency component is double of an original frequency of the input signal so as to obtain an output signal of which a frequency is multiplied in response to the input signal.

Abstract: An electronic circuit generates additional clock edges from a reference clock signal utilizing switch-capacitor techniques. The electronic circuit includes a first capacitance circuit and a second capacitance circuit separated by a switch. During a first time period, the switch is open and the first capacitance circuit is charged. During a second time period, the switch is closed and at least a portion of the charge stored in the first capacitance circuit is transferred to the second capacitance circuit. The amount of charge transferred depends upon the relative sizes of the capacitance circuits. During another time period, the second capacitance circuit is discharged until its associated potential reaches a threshold level corresponding to a threshold set by a level detector. Upon reaching the threshold level, the level detector outputs a logic signal. A high frequency clock signal is produced by combining the logic signal with the reference clock signal.

Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: This invention provides a multistage frequency multiplier having a plurality of frequency doublers. Each doubler incorporates a three-terminal transistor device and is connected to an adjacent doubler via an interstage network. The network comprises a transmission line having its electrical parameters selected to achieve conjugate impedance matching at the intermediate harmonic frequency generated by the corresponding doubler. This network also includes a quarter-wavelength open-ended stub for suppressing a main input frequency component received by the corresponding frequency doubler. A shunt resistor on the transistor gate is preferably used to stabilize the network. This interstage network simplifies overall circuit topology to reduce total circuit size, and provides increased drive power levels to permit broader bandwidth and stabilize required output level from a local oscillator.

Abstract: A mixer includes a first terminal and a second terminal forming a first input port for receiving a first signal having a first frequency; a second input port for receiving a second signal having a second frequency; a mixer output port for a resulting signal; a first group of valves having their control inputs coupled to the first terminal for receiving the first signal; a second group of valves having their control inputs coupled to the second terminal for receiving the first signal; and a third group of two valves having their control inputs coupled for receiving the second signal. The valves co-operate such that in operation the mixer produces the resulting signal responsive to the first and second signals. The mixer also includes at least one passive low pass filter having an inductor, the low pass filter being connected to the control input of a valve in the first and second groups.

Abstract: A low-noise sampling PLL for high-resolution radar systems wherein the reference frequencies are taken from a line spectrum (SPK), which has been generated from the mixture of a low quartz oscillator frequency (F1) with a high quartz oscillator frequency (F2), with the quartz oscillator frequencies (F1, F2) being synchronized. The invention is employed in connection with sampling PLLs for high-resolution radar systems with a controllable frequency oscillator, whose output signal is partially coupled out into a feedback branch and compared with reference frequencies in a phase comparator.

Abstract: A clock control circuit which includes a frequency multiplying interpolator for generating and outputting multiphase clocks by frequency multiplying an input clock; a switch for outputting two of the multiphase clocks input thereto from the frequency multiplying interpolator; a fine adjusting interpolator, to which the two outputs from the switch are applied, for outputting a signal obtained by internally dividing the phase difference between the two outputs; and a control circuit for controlling the switching of the switch and varying the internal-division ratio of the fine adjusting interpolator.

Abstract: An apparatus for generating a supply signal at a predetermined frequency comprises a digital synthesizer connected with an oscillator and a processor; and a temperature sensor connected with the processor. The oscillator provides a periodic excitation signal to the synthesizer, which responds by recurrently accumulating bits in quantum bit step amounts to a maximum bit capacity and returning to a starting bit count in a bit accumulating period. The synthesizer generates the supply signal based upon the bit accumulating period. The processor provides a control signal to the synthesizer to control the quantum bit step amount. The temperature sensor and the processor cooperatively employ a predetermined temperature parameter-correction factor relationship to adjust the control signal to set the quantum bit step amount to establish the bit accumulating period appropriately for the predetermined frequency.

Abstract: A phase shifter network receives at an input node an input clock signal which does not contain higher order harmonics and generates first and second phase-shifted clock signals which are 90° apart and which have the same frequency as the input clock signal. First and second voltage comparators receive the first and second phase-shifted clock signals, respectively, and generates first and second squared clock signals, respectively, which are 90° apart and which have the same frequency as the input clock signal. A combiner combines the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.

Abstract: One end of a first transmission line is connected to the collector of an HBT with the base connected to an output terminal of an input-side matching circuit and with the emitter grounded, and one end of an end-open stub for blocking the passage of the doubled wave is connected to the other end of the first transmission line. One end of a second transmission line is connected to the other end of the first transmission line, and one end of an end-open stub for blocking the passage of the fundamental wave is connected to the other end of the second transmission line. An input terminal of an output-side matching circuit is connected to the other end of the second transmission line.