Abstract: A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

Abstract: A digital waveform oscillator generates digitized waveforms without distortion using a lookup table. The frequencies which may be generated using direct lookup tables at their fundamental table frequencies are increased according to this invention by including multiple cycles of the waveform within a single table. The selection of a table length L and a number of cycles N to be stored in a lookup table is done in a manner to optimize corresponding values of the frequencies to be generated and the sample rate.

Abstract: An outgoing harmonic level evaluator which evaluates the amount of outgoing harmonics by computing correction to the amount of harmonics measured at a receiving point without the need for summing the measurement values of generated harmonics in load bus lines.

Abstract: A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

Abstract: A method and system of frequency multiplying a signal having amplitude modulation using a frequency multiplier operated at a bias voltage that is less than its saturation mode voltage is described. Prior to amplification, the amplitude modulated signal is pre-distorted to compensate for distortion caused by the frequency multiplier. A first pre-distortion phase converts the amplitude modulated signal into a corresponding square root signal to compensate for a first distortion type. A second pre-distortion phase pre-distorts the square root signal to compensate for the distortion caused by biasing the frequency multiplier at a voltage less than the saturation voltage of the multiplier. As a result, a signal that is amplitude modulated can be multiplied by a frequency multiplier.

Abstract: A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal F.sub.clk so that the output frequency F.sub.o of the waveform is:F.sub.o =(F.sub.n /2.sup.N).times.(M.times.F.sub.clk)where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word, M is the multiplication factor and M*F.sub.clk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.

Abstract: A multiplier containing first and second quadritail cells. The first quadritail cell has a first pair of first and second transistors, a second pair of third and fourth transistors, and a first constant current source for driving the first and second pairs. The second quadritail cell has a third pair of fifth and sixth transistors, a fourth pair of seventh and eighth transistors, and a second constant current source for driving the third and fourth pairs. A first input voltage is applied between input ends of the first and fourth transistors and is applied between input ends of the fifth and eighth transistors. A second input voltage is applied between input ends coupled together of the second and third transistors and the input ends coupled together of the sixth and seventh transistors.

Abstract: An optical unit for multiplying the frequency of a clock signal includes at least two series-arranged ring lasers. Each ring laser has a different resonance frequency f.sub.i. The unit has an input for receiving a signal, for example, a low-frequency electric signal for modulating one of the ring lasers. The repetition frequency of at least one of the ring lasers is variable by adapting the optical path length of the resonator.

Abstract: Mixer structures are described which include a current mirror for insertion of trickle currents to an input differential amplifier and an output interface for coupling an output differential amplifier to an output port. The current mirror trickle currents improve the mixer's conversion gain and third-order intercept point and the current mirror introduces them without introducing spurious signals. The output interface couples mixer currents to the output port while isolating the output port from power-supply spurious signals.

Abstract: A Gilbert Multiplier Cell includes an emitter-coupled transistor pair and a pair of cross-coupled emitter-coupled transistor pairs. A filter couples the emitter-coupled transistor pair to the pair of the cross-coupled emitter-coupled transistor pairs. The filter may include a pair of inductors or resistors, a respective one of which serially couples a respective one of the emitter-coupled transistor pair to a respective one of the pair of cross-coupled emitter-coupled transistor pairs, and a capacitor connected between the pair of inductors or resistors. A local oscillator is coupled to the pair of cross-coupled emitter-coupled transistor pairs and a data input is coupled to the emitter-coupled transistor pair. By low pass filtering the output of the emitter-coupled transistor pair that is applied to the pair of cross-coupled emitter-coupled transistor pairs, low noise floor Gilbert Multiplier Cells and quadraphase modulators may be provided.

Abstract: The frequency multiplier 10 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: A transformer-coupled mixer circuit including dc voltage supply; and four transistors, arranged as a first transistor pair and a second transistor pair. Each transistor pair has a first transistor and a second transistor and each transistor has a base, a collector and an emitter. The emitter of the first transistor in each transistor pair is connected to the collector of the second transistor in that transistor pair, and the emitter of the second transistor in each transistor pair is connected to a current sink. The circuit also comprises a transformer, having a set of primary windings and first and second sets of secondary windings, the first set of secondary windings being connected in series with the emitter of the first transistor in the first transistor pair and the second set of secondary windings being connected in series with the emitter of the first transistor in the second transistor pair.

Abstract: A frequency multiplier circuit receives an input signal and generates an output signal. The input waveform (110) has a frequency F.sub.1. The output waveform (112) has a frequency nF.sub.1 wherein n is an even integer. The frequency multiplier circuit comprises first and second transistors T.sub.1 and T.sub.2, each transistor having a base, emitter, and collector. The emitters of each transistor are coupled together and are connected to an output load (108). The collectors of each transistor are coupled together and are connected to a voltage potential (109). The base of each transistor receives an input waveform, wherein a first input waveform (110) at the first transistor base is 180.degree. out of phase with a second input waveform (111) at the second transistor base.

Abstract: A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

Abstract: FET mixers requiring relatively low local oscillator power levels and having excellent isolation of the local oscillator signal relative to the radio and intermediate frequency signal. The mixer comprises a first and second FET transistor (Q1, Q2) having their gates and sources connected together such that the first and second FET transistors are in series; a local oscillator input circuit; a coupling network comprising a transmission line balun; a diplexer circuit; and a bias circuit. In one aspect, the transmission line balun divides the voltage of an incident traveling wave equally between the first and second transmission line components, and sums the currents of traveling waves generated by the transmission line components to generate an exitant traveling wave signal. The RF signal is completely reflected by each the FET transistors with no phase shift when they are nonconducting (OFF), and completely reflected by each of the FET transistors with a 180.degree.

Abstract: A programmable digital frequency multiplier includes either a delay locked loop with an input clock or a ring oscillator which generates multiple phase delayed clock signals having a common frequency equal to that of the input clock and a corresponding number of equidistant phases. In the delay locked loop, a phase comparator compares the phase of the input clock as received by the first inverter circuit with the phase of the output of the last inverter circuit and generates an error signal which is used as a circuit bias control signal for each of the inverter circuits, thereby controlling the phase delay through each inverter circuit. The multiple inverter circuit output signals are individually gated in separate NOR gates with a corresponding number of frequency programming bits.

Abstract: A four terminal multiplication circuit capable of mixing up to three input signals. The circuit includes a MOS transistor having gate, source, drain and back-gate terminals. When the circuit is used as an RF mixer or downconverter, an RF signal is provided to the gate terminal and a local oscillator signal is provided to the back-gate terminal. A DC voltage is applied to the source terminal for biasing the transistor and the mixed/downconverted output (IF) signal is obtained from the drain terminal. A single balanced and a double balanced mixer circuit are also disclosed. In the single balanced circuit, two MOS transistors are used; the RF signal is applied to the gate terminals with the positive phase LO component applied to one back-gate terminal and the negative phase local oscillator (LO) component applied to the other back-gate terminal for producing a positive phase and a negative phase IF signal.

Abstract: A direct digital-to-analog microwave frequency signal synthesizer device which employs both wideband and narrowband direct digital frequency synthesizer (DDFS) circuitry to improve frequency and phase agility, reduce spurious performance, and minimize direct analog circuitry. A clock output having an extremely precise and highly stabilized frequency is fed to the wideband DDFS circuit and to the narrowband DDFS circuit. One or the other is selectively enabled by control logic circuitry. When the former is enabled, precision, high frequency resolution, low spurious, fast frequency switching is achieved at the microwave output. When the latter is enabled, precision, high frequency and phase resolution, low spurious, is achieved, providing frequency chirp, and frequency phase control at the microwave output. The output of the wideband DDFS circuit is processed to reduce the spurious response and up-converted, while the output of the narrow band DDFS circuit is directly up-converted.

Abstract: A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency.

Abstract: The clock generator generates an output clock signal of known frequency from an internally generated high frequency signal of unknown frequency and from a low frequency input signal of known frequency. To this end, the clock multiplier first determines the frequency of the internal clock signal from a comparison with the input clock signal. In one arrangement, the frequency of the internal signal is determined by counting a number of clock transitions occurring during the internal signal within one period of the input clock signal. Once the frequency of the internal signal has been determined, the clock multiplier generates an output clock signal based upon the internal clock signal but adjusted in accordance with the newly determined frequency of the internal clock signal. In one arrangement, the clock multiplier employs a programmable divider.

Abstract: A small and inexpensive mixer that does not require a choke inductor and a large-capacitance capacitor. The mixer has a FET. The FET's source is grounded via a capacitor and is also connected to a power-supply terminal. The FET's gate is coupled to a bias voltage and also connected to a gate input terminal via a capacitor. The FET's drain is connected to an output terminal via a capacitor. A modulating signal is input into the power-supply terminal, and a local signal is input into the gate input terminal, so that a modulated signal is output from the output terminal.

Abstract: A frequency multiplier circuit that needs no coupling capacitors and no input bias circuits for a next-stage circuit, which includes a phase-shifted signal generator, first and second differential amplifiers, and a multiplier. The phase-shifted signal generator receives an initial input signal and generates first and second output signals whose phases are shifted by 90.degree. with each other. The first differential amplifier amplifies the first output signal to output a first positive-phase output signal and a first negative-phase output signal. The second differential amplifier amplifies the second output signal to output a second positive-phase output signal and a second negative-phase output signal. The multiplier multiplies the first and second positive-phase output signals to output a third positive-phase output signal as a positive-phase output of the frequency multiplier circuit.

Abstract: A frequency hopping synthesizer is constructed from two FET-based multiplier circuits each responsive to a carrier input signal and a modulation signal to produce respective output signals which are in-phase combined to provide a frequency-shifted signal. The multiplier circuits each comprise two dual-gate field effect transistor (FET) amplifiers which are electrically balanced to suppress unmodulated carrier components so that only the modulated carrier signal appears. The respective carrier input signals and modulation signals are in quadrature phase relationship. A direct digital synthesizer controllably generates signal components which serve as the modulation signals for the multiplier circuits.

Abstract: A four-quadrant multiplier, which is composed of CMOS transistors and suited to applications of low-voltage operation.

Abstract: A differential mixer (DM) used in a telecommunication radio transmitter able to operate with a 3 Volt supply includes a silicon bipolar cross-connected pair of differential amplifiers (A; B) for receiving a first input voltage (LO) at a high frequency, a pair of current sources (I1; I2), and a voltage-to-current MOS converter (VIC) for receiving a second input voltage (VIN) at a lower frequency. The converter is adapted to convert the low frequency voltage to a differential current (INN) and is coupled to the junction points of the amplifiers and the current sources. The converter further includes a regulated differential cascode circuit (P1; P2) to which the low frequency input voltage (VIN) is applied via resistors (RI1; RI2) and which is coupled to the supply terminals (VCC; GND) of the mixer via two pairs of constant current sources (PB1, PB2; NB1, NB2) respectively.

Abstract: A four-quadrant three-input multiplier is disclosed. The three-input multiplier, which finds the product of a first input signal, a second input signal, and a third input signal, includes four differential transconductance amplifiers and two loads. Transistors in the differential pair of each differential transconductance amplifier are operated in the subthreshold region. Four linear-combination signals are individually fed into one input terminal of the four differential transconductance amplifiers. A linear-combination circuit configuration is also disclosed and can be used to generate the required linear-combination signals.

Abstract: A multiplier in which simplification of a circuit configuration and reduction of a current consumption can be realized. There are provided with first, second, third and fourth pairs of transistors whose capacities are the same with each other and these four pairs are driven by a constant current source, respectively. A sum of first and second input voltage is applied in positive phase to an input end of the first pair and the sum is applied in opposite phase to the other input end thereof. A difference of the first and second input voltages is applied in positive phase to an input end of the second pair and the difference is applied in opposite phase to the other input end thereof. Input ends of the third pair and those of the fourth pair are coupled together to be applied with a direct current voltage.

Abstract: A harmonic tone generator produces a harmonics signal even for input audio signals of a small amplitude. Conversion of a digitized audio signal in accordance with a predetermined non-linear function is performed also for an audio signal of a small amplitude. According to the second aspect of the invention, a level difference between the digital audio signal level in the present sampling time and the audio signal level in the preceding sampling time is detected and the detected level difference is converted to an output value in accordance with a predetermined non-linear function by a non-linear converting circuit. The converted output value is accumulated. According to the third aspect of the invention, the detected level difference is converted to a function conversion output in accordance with a predetermined function by a non-linear converting circuit. A gain of an amplifier to amplify the audio signal in the present sampling time is changed in accordance with the function conversion output.

Abstract: A control circuit for a clock includes a clock multiplier having an input for receiving a clock signal, an amplifier and an output. The clock multiplier multiplies the clock signal and produces an amplified, multiplied clock signal at the output. The amplifier has a reference voltage control input for setting a value of a reference voltage in the amplifier. A peak detection circuit is provided for detecting an amplitude value of the clock signal at the input of the clock multiplier. A comparator is provided for comparing the amplitude value detected at the peak detection circuit with a further reference voltage previously set less than an amplitude value of the clock signal. A switching is coupled to the output of the comparator and to the reference voltage control input of the amplifier in the clock multiplier for switching the further reference voltage according to the output of the comparator.

Abstract: A four-quadrant multiplier using BiCMOS circuits can be applied in high-frequency analog circuits. The four-quadrant multiplier includes two transform circuits to generate two intermediate signals proportional to the first and second input signals, respectively; four square circuits to provide a squaring relationship between current and voltage in the four square circuits; and two resistors serving as a load for the currents of the four square means and for outputting the resultant voltage to an output port.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: A tree mixer includes a first differential pair of transistors which divide current from a first current source between the transistors in dependence upon a first differential input signal supplied to first input terminals. Two second differential pairs of transistors have controlled paths which conduct current, divided between the transistors of the differential pair in dependence upon a second differential input signal supplied to second input terminals, dependent upon current passed by a respective transistor of the first pair of transistors, to produce a product signal at output terminals. One or more second current sources provide for the total current passed by the first pair of transistors to be greater than the total current passed by the two second pairs of transistors, for improved linearity without increasing noise. A quadrature phase modulator can include two such mixers with common output circuitry.

Abstract: A frequency multiplier circuit comprising a first delay circuit for delaying sequentially a reference clock signal, a frequency doubler for delaying the reference clock signal and combining logically the delayed reference clock signal and the reference clock signal, a second delay circuit for delaying sequentially an output signal from the frequency doubler, a signal detector for logically combining the output signal from the frequency doubler and a plurality of output signals from the second delay circuit to detect a desired duty factor of signal, a decoder for decoding a plurality of output signals from the first delay circuit and a plurality of output signals from the signal detector to output a signal delayed by n times half a period of the reference clock signal, and a frequency generator for logically combining an output signal from the decoder and the reference clock signal to generate a multiple frequency of that of the reference clock signal.

Abstract: A signal source provides an output signal which can sweep over a broad frequency range in a well-controlled manner. The signal source includes a voltage controlled oscillator (VCO) producing the output signal and a waveform synthesizer producing a reference signal. The VCO output signal is phase locked to the reference signal. To make the VCO signal continuously sweep over a broad frequency range, the reference signal sweeps repeatedly over a narrow frequency range. During each sweep of the reference signal, the VCO frequency tracks an integer harmonic of the reference signal frequency. The frequency and phase of the reference signal for each successive sweep are abruptly reset at the beginning of each sweep selected such that the VCO signal frequency locks to another integer harmonic of the reference signal frequency and does not change.

Abstract: A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.

Abstract: Apparatus and a method for generating all of the assignable carrier frequencies in the FM broadcast band and for frequency modulating the generated carriers includes a generator of a train of pulses having a crystal-controlled repetition frequency and a specific pulse shape which together produce a spectrum of odd harmonics of the pulse repetition frequency whose separation in frequency is identical to that of the assignable carrier frequencies. This pulse train is then mixed with a 98.0 MHz sine wave to translate the spectrum to the FM band. Simultaneous modulation of all the carriers is achieved by frequency modulating the 98.0 MHz sine wave, whereby the same modulation is imparted simultaneously to all of the carriers.

Abstract: A clock system and method for reducing the measured level of electromagnetic emissions, measured by a measuring device employing a C.I.S.P.R. quasi-peak detector from an electronic device having unintentional electromagnetic emissions at frequencies derived from a system clock is achieved by varying the frequency of the system clock in a range between first and second predetermined frequencies to spread the emission energy over the frequency range and reduce measured emission levels.

Abstract: A multi-channel carrier wave generator includes a signal source capable of generating a carrier wave having a frequency, a first input-match diode circuit receiving the carrier wave to correspondingly generate a plurality of harmonic waves, a first multi-way power divider electrically connected to the first input-match diode circuit to equally divide the harmonic waves, and a first multi-way filter electrically connected to the first multiple power divider to filter through the harmonic waves. Such a multi-channel carrier wave generator has the advantages of having a simple fabrication procedure, a low cost, and a low phase noise, and capable of providing a stable carrier wave and a good filtering result and of using a lower order bandpass filter.

Abstract: A frequency multiplier and mixer circuit comprises a frequency multiplier circuit composed of a first differential amplifier, which includes a first differential circuit formed of source-coupled first and second FETs having their sources connected in common to a first constant current source and a second differential circuit formed of source-coupled third and fourth FETs having their sources connected in common to a second constant current source. The first and second differential circuits constitute two identical unbalanced source-coupled pairs having the same gate width/length ratio K, input terminals of the pairs being connected in cross-coupled fashion, the output terminals of the pairs being connected in parallel. Gates of the first and third FETs are connected in common to one terminal of a first pair of input terminals for receiving a signal to be frequency-multiplied, and gates of the second and fourth FETs are connected in common to the other terminal of the first pair of input terminals.

Abstract: An input signal specified by an input frequency is divided by an out-of-phase type input hybrid coupler, into two divided signals with regard to the power of the input signal, where the divided signals have different phases. The input frequency of each of the divided signals is multiplied by a frequency multiplier connected with the input hybrid coupler, producing frequency multiplied signals each specified by the multiplied frequency. The frequency multiplied signals are composed by an out-of-phase type output hybrid coupler with regard to power, producing an output signal specified by the multiplied frequency. A phase shifter is provided between the input and the output hybrid coupler for varying the phase difference between the frequency multiplied signals, so that the frequency multiplied signals are composed in in-phase.

Abstract: A circuit for generating a pair of quadrature output signals from a pair of quadrature input signals in which the frequency of the output signals is double that of the input. The circuit consists of two dual phase shifters, two symmetrical multipliers and a phase controller. The circuit is fabricated by conventional integrated circuit processing technology. A method of generating frequency doubled quadrature output signals is disclosed.

Abstract: A ring laser gyro scale factor enhancement circuit connected between at least one power supply voltage level and a reference potential for conditioning at least a first and second input signal from a ring laser gyro assembly, the first and second input signals being essentially sinusoidal and having a common first input signal frequency, the second input signal having a predetermined first phase relationship with the first input signal for a first ring laser gyro rotational sense and a second predetermined phase relationship with the first input signal for a second ring laser gyro rotational sense.