Abstract: A phase interpolator that receives input clock phase and selection inputs that are distinct from the input clock phases. The phase interpolator generates an output clock phase based on the selection inputs. The phase interpolator includes selector devices which receive the input clock phases and receive the selection inputs, and includes cross-coupled switches which are connected to the selector devices and receive input clock phases therefrom. The selector devices select which input clock phases to provide to the cross-coupled switches based upon the selection inputs. The cross-coupled switches generate the output clock phase based upon the input clock phases which are received from the selector devices.

Abstract: A branching section provides a fundamental input wave signal SI of a frequency f to the gate of a FET 15A having a grounded source and the source of a FET 15B having an AC grounded gate, and a signal joining section synthesizes the output signals of the FETs 15A and 15B. An open stub 24 as an amplitude attenuating element is connected to a transmission line 19B of the signal joining section. The length of the open stub 24 is not an integral multiply of &lgr;/4, where &lgr; denotes the wavelength of the fundamental signal SI, and adjusted in simulation such that an amplitude difference between second harmonics included in the drain voltage signals SD1 and SD2 of the respective FETs 15A and 15B is reduced to almost zero. Although the open stub 24 itself is a phase compensating element, since the transfer characteristic of the FET 15B changes by connecting the open stub 24 to the transmission line 19B, the open stub 24 works as an amplitude attenuating element.

Abstract: A frequency doubler circuit with a 50% duty cycle output includes a two-input XOR or XNOR logic gate having a first input coupled to a digital input signal having a first frequency, and a second input coupled to a replica of the input signal delayed by a quarter of the time period of the input signal. The frequency doubler circuit includes at least two capacitors in series, a constant current generator for charging the capacitors during one of the two half periods of the input signal, and first and second switches controlled in phase opposition by the input signal and by an inverted signal thereof for charging and discharging the capacitors during each period of the input signal. A voltage divider halves the voltage present on the capacitors so that a comparator senses the halved voltage on one of the two capacitors. The comparator provides an output signal to the second input of the logic gate.

Abstract: A frequency multiplier circuit outputs a desired frequency, wherein a frequency of a reference clock is divided by 4 by a frequency divider, the frequency of a unit clock is divided by 2 by another frequency divider and the output of these dividers are provided to an AND gate. A variable frequency divider divides the frequency of an output from the AND gate by n. An up-counter counts the number of pulses of the output from the variable frequency divider. Another variable frequency divider divides the frequency of the unit clock by the number of pulses to output a signal having a frequency of the reference clock multiplied by n.

Abstract: This electronic device comprises a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of these periodic signals. This multiplier circuit (14) is formed on the basis of an <<EXCLUSIVE-OR>> gate (20), which receives said periodic signals, and a frequency divider circuit (22) connected between the output and an input of said gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which permits to perform a modulation of the type known by the name of “zero demodulation”.

Abstract: A clock signal generating circuit and its clock frequency adjusting method, in which a clock signal of a desired frequency can be generated even if an oscillating circuit of relatively low frequency precision is used. Each of frequency division data is sequentially dnd repetitively read out from a memory in which a plurality of frequency division data has been stored, and a signal whose logic level is inverted each time the read-out frequency division data and the number of pulses of a constant frequency signal generated by an oscillating circuit coincide is generated as a clock signal. An adjustment is performed so as to decrease a value of at least one of the frequency division data stored in the memory when the frequency of the constant frequency signal is lower than the desired request frequency and to increase the value of at least one of the frequency division data stored in the memory when the frequency of the constant frequency signal is higher than the desired request frequency.

Abstract: A switched frequency multiplier receives pulses of pump energy as an input signal. The input signal is transferred to within a housing having a first cavity tuned to the frequency of the pump signal and a second cavity which is tuned to a harmonic of the input signal and is enclosed within the first cavity. An outlet port couples the second tuned cavity to a waveguide which includes a Q-switch that can be turned on and off. The interior of the housing has a planar grid of layers which includes a layer of nonlinear material and a frequency selective layer. The frequency selective layer is transparent to the input signal but reflective to the harmonic output signal thereby trapping energy in the second cavity. The multiplier operates by receiving a pump pulse and storing the energy while the Q-switch is closed. When the Q-switch is opened near the end of the pump pulse, the stored energy is suddenly released to produce a relatively high energy harmonic pulse having a shorter duration than the pump pulse.

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Abstract: A nonlinear transmission-line waveform generator for generating a comb of frequencies and relatively short duration pulses, for example, in the range of picoseconds and tens of picoseconds, that are adapted to being utilized with ultra wideband radios in order to improve the bandwidth of such radios by an order of magnitude, for example, up to tens and even hundreds of GHz. In particular, the nonlinear transmission line waveform generator in accordance with the present invention consists of a microstrip or coplanar waveguide line. In accordance with an important aspect of the invention, the &Dgr;C/&Dgr;V characteristic of the nonlinear transmission line is matched to the frequency and amplitude of the input sinusoid. By matching the &Dgr;C/&Dgr;V characteristics of the nonlinear transmission line to the input sinusoid, the output of the nonlinear transmission line produces a comb of frequencies that are multiples of the input sinusoid frequency, making it suitable as a harmonic generator.

Abstract: One end of a first transmission line is connected to the collector of an HBT with the base connected to an output terminal of an input-side matching circuit and with the emitter grounded, and one end of an end-open stub for blocking the passage of the doubled wave is connected to the other end of the first transmission line. One end of a second transmission line is connected to the other end of the first transmission line, and one end of an end-open stub for blocking the passage of the fundamental wave is connected to the other end of the second transmission line. An input terminal of an output-side matching circuit is connected to the other end of the second transmission line.

Abstract: A clock multiplier circuit comprises: a counter for counting the number of pulses of a predetermined output clock signal; an expected value generating circuit for generating an expected value for the number of pulses of the predetermined output clock signal per a first period which is sufficiently longer than one period of the predetermined output clock signal; a comparator circuit for comparing the counted value of the counter with the expected value per the first period to output a comparative information on the comparative result; a delay control circuit for generating a delay control signal indicative of change of the frequency of the predetermined output signal in accordance with the comparative information; and an output clock signal generating circuit for generating the predetermined output clock signal while changing the frequency in accordance with the delay control signal.

Abstract: A circuit for doubling the frequency of an input signal. The circuit includes a full-wave rectifier that rectifies the input signal to generate an output signal with double the frequency of the input signal. The output signal is compared to a predetermined voltage. Based on this comparison, a control signal is fed back to the full-wave rectifier and the output of the rectifier is adjusted to a predetermined level. In this manner the frequency of the input signal is doubled, and the output power is maintained constant, independent of the input power level.

Abstract: In a frequency-voltage conversion circuit, integrating circuitry gives a predetermined slope for rising or falling of a rectangular pulse signal. First comparing circuitry compares an output value of the integrating circuitry with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. Storing circuitry stores and retains the threshold value. Smoothing circuitry smoothes the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. Second comparing circuitry compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing circuitry on the basis of the comparison result.

Abstract: In a frequency multiplier which generates a multiple output of a reference signal, a reference signal and its inverted signal are propagated through a pair of delay circuits each including a given number of delay cells connected in cascade. The delay cells delay a signal by time t when a control signal is at a high level and delay a signal by time 2t when a control signal is at a low level. The outputs of the delay circuits are added together by an adder circuit to generate a multiple output without using a low-pass filter but by non-feedback control.

Abstract: An improved clock generator performs clock multiplication using selectable generation of clock edges. A clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock—these edges are selectably combined to produce an output clock with the desired multiplication and duty cycle. The sequence of non-overlapping pulses is synchronized to the period of the input reference clock, i.e., to the first harmonic of the reference clock. A pulse generator network includes N pulse generators PG1-PGN, with the output of each pulse generator being coupled to the input of the next pulse generator. When triggered, each pulse generator generates a pulse P with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal.

Abstract: A generator of high frequency signals comprises a delay element and a switching element, whereby the delay element causes a delay of &pgr;/4 radians, and the switching element is switching to produce an output at the fundamental frequency, but with enriched even harmonic content. A filter selects the desired harmonic, and passes this on as an output. Additionally, a maximizing circuit may vary the phase of the delay element to maximize the output level of the generator.

Abstract: A semiconductor circuit includes at least first and second field effect transistors. A source electrode of the first field effect transistor is connected to a drain electrode of the second field effect transistor via a first AC current blocking element and is also grounded via a bypass capacitor. A drain electrode of the first field effect transistor is connected to a power supply. A source-drain voltage of the first field effect transistor is equal to or higher than a pinch-off voltage of the first field effect transistor. A source-drain voltage of the second field effect transistor is equal to or higher than a pinch-off voltage of the second field effect transistor.

Abstract: A frequency doubler includes a first Gilbert cell, a second Gilbert cell coupled to the first Gilbert cell, a frequency generator configured to apply a first sinusoidal wave to the first Gilbert cell, and a phase shifter applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell. A method of doubling frequency without using a feedback loop includes providing a first Gilbert cell, providing a second Gilbert cell coupled to the first Gilbert cell, applying a first sinusoidal wave to the first Gilbert cell, and applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell.

Abstract: One end of a first transmission line is connected to the collector of an HBT with the base connected to an output terminal of an input-side matching circuit and with the emitter grounded, and one end of an end-open stub for blocking the passage of the doubled wave is connected to the other end of the first transmission line. One end of a second transmission line is connected to the other end of the first transmission line, and one end of an end-open stub for blocking the passage of the fundamental wave is connected to the other end of the second transmission line. An input terminal of an output-side matching circuit is connected to the other end of the second transmission line.

Abstract: An N times frequency multiplication circuit uses duty cycle control buffers in combination with edge detectors to provide both multiplication and 50% duty cycle adjustment. Parallel branches of duty cycle control buffers are preset for respective duty cycles of 1/N, 2/N,...,N−1/N. The buffers each receive a common edge detected input signal and simultaneously output their respective duty cycle adjusted clock signals. A rising and falling edge detector generates a pulse train at double the frequency of the 1/N buffer output, while falling edge detectors generate time spaced pulse trains from the outputs of their respective 2/N,...,N−1/N buffers. These pulse trains are combined in an OR gate to provide an output pulse train at a frequency N times the input clock frequency fin. A final stage duty cycle control buffer adjusts the N times fin output signal to a 50% duty cycle.

Abstract: Clock generating circuitry comprises a first frequency multiplier for multiplying the frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for furnishing the frequency-multiplied clock, a frequency divider for dividing the frequency of the frequency-multiplied clock furnished by the first frequency multiplier by 227, and for furnishing the frequency-divided clock, and a second frequency multiplier for multiplying the frequency of the frequency-divided clock from the frequency divider by 128, and for furnishing the frequency-multiplied clock. The reference clock can have a frequency of about 4.43 MHz.

Abstract: A clock frequency multiplying apparatus is disclosed. The apparatus includes a clock generator for generating a clock signal, a data input buffer for serially receiving a data, address, instruction, etc. when a transmission clock signal generated by the clock generator is inputted, a data shift register for grouping the data received through the data input buffer into a data packet and, in parallel, transferring the same to a memory, and a clock frequency multiplier for multiplying a transmission clock frequency generated by the clock generator and inputting the same into the data shift register for implementing a fast data transfer by multiplying a clock frequency by dividing the clock signal in an internal circuit of the DRAM into a critical path and a non-critical path by using a transmission clock signal for the critical path and the multiplied clock signal for the non-critical path and enhancing an internal data transfer ratio.

Abstract: The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: A frequency multiplier circuit needs to have a voltage controlled oscillator circuit having a wide oscillation frequency range, or delay cells each having a delay value which can be controlled over a wide range. Depending on the frequency multiplication factor, however, a frequency multiplied clock signal susceptible to influence of noise is generated. In the disclosed frequency multiplier circuit, there are provided a phase comparison input selection circuit for conducting a selection out of output signals of delay cells forming a voltage controlled delay circuit according to a frequency multiplication factor setting signal and an input frequency range setting signal and outputting the selected signal to a phase comparator, and a selected waveform generation circuit for generating a frequency multiplied clock signal CKOUT from the output signals of the delay cells according to the frequency multiplication factor setting signal and the input frequency range setting signal.

Abstract: A mixing method and mixer structure provide a circuit topology suitable for use in radio receivers, transmitters, tuners, instrumentation systems, telemetry systems, and other systems and devices performing frequency conversion in either homodyne or heterodyne implementations. The inventive mixer may be used for wireless communication devices including radios, cellular telephones, and telemetry systems whether land, sea, airborne, or space based, and whether fixed or mobile. The mixer provides superior intermodulation and harmonic distortion suppression and features excellent conversion loss, noise figure, port match, and port isolation as a result of its circuit topology. The mixer device circuit combines the advantages of series mixing FETs, a triple balanced design using a balanced passive reflection transformer, a precise local oscillator phase splitter, and square wave gate drive having high slew rate signal characteristics to achieve high levels of performance.

Abstract: A frequency translation circuit (10) translates an incoming reference signal (RF.sub.IN) to a lower frequency using a compound mixer circuit (42). The compound mixer circuit (42) has a first mixer circuit (14A) that receives both the incoming reference signal (RF.sub.IN) and a signal generated by a first counter (28A). A second mixer circuit (14X) of the compound mixer circuit (42) receives a signal generated by a second counter (28X) and further translates the signal received from the first mixer circuit (14A) to a lower frequency. Both the first mixer circuit (14A) and the second mixer circuit (14X) generate output signals having a carrier frequency that is lower in frequency by the difference of the two input signals.

Abstract: A frequency divider circuit operable at high frequencies for producing an output signal having a frequency value equal to substantially half the frequency value of a clock signal from which the circuit operates. The circuit includes a first transistor branch, an inventor and a second transistor branch. The first transistor branch is connected to an input of the inventor and the second transistor branch is connected to an output of the inventor. The first transistor branch receives a plurality of input signals including the clock signal, a compliment of the clock signal, and the circuit output signal and produces an input signal which is provided to the inventor. The second transistor branch receives a plurality of inputs including the compliment of the clock signal, the clock signal and the inventor output signal, and produces the circuit output signal. The circuit is configured such that the next inventor state is always available for conveyance to the output signal upon a change in the clock signal.

Abstract: A wide bandwidth frequency multiplier (48) multiplies a first frequency of an input signal (52) to generate an output signal (54) having a second frequency. The multiplier (48) includes first stage doubler (56). The doubler (56) includes a lumped element power splitter (62), a push-push amplifier (80), and a combining junction (96). The power splitter (62) splits the input signal (52) into first and second signals (70, 72) that are balanced in phase. A series resistive element (86) maintains amplitude balance between the first and second signals (70, 72). First and second feedback circuits (166, 184) are integrated with first and second transistors (164, 182) so that the push-push amplifier (80) operates over wide bandwidth. In addition, the multiplier (48) includes a second stage doubler (58) configured similar to the first stage doubler (56) for producing an output signal (54) that is quadruple the frequency of input signal (52).

Abstract: A frequency multiplication circuit generates an output clock signal having a frequency obtained by multiplying an external clock signal inputted from outside by a predetermined number.

Abstract: The invention relates to a wave form shaping circuit, etc. which outputs signals after shaping the input signal to a duty 50% wave form regardless of whether or not input signals are of duty 50%, wherein a duty determination circuit is provided, which determines and instructs the timing position of duty 50% of clock signals to be outputted, upon receiving a timing signal prepared by a timing generation circuit 2.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A frequency multiplier comprises a phase shifter having a differentiator and an integrator each including a series circuit of a resistor and a capacitor, a frequency converter for performing a frequency conversion on the basis of the output signal from the phase shifter and a drive circuit for current-driving the phase shifter in accordance with an input voltage signal.

Abstract: A clock signal control circuit includes a divider dividing an external clock signal into multiple phase clock signals, timing difference dividers connected to the divider for dividing a difference in phase of pulses between the multiple phase clock signals having different phases from each other to generate different phase clock signals, a single multiplexer connected to the timing difference dividers for multiplexing the different phase clock signals to generate multiplexed clock signals, and a synthesizer connected to the multiplexers for synthesizing the multiplexed clock signals into a single multiplied clock signal.

Abstract: The frequency doubling circuit according to the present invention includes first and second pulse generating circuits generating first and second pulse trains based on a periodic input signal. The second pulse train is out of phase with the first pulse train, and a combining circuit combines the first and second pulse trains to generate a periodic output signal having twice the frequency of the periodic input signal. Both the first and second pulse generating circuits include first and second charge storage devices, with the second charge storage device having half the storage capacity of the first charge storage device.

Abstract: A frequency multiplier circuit device having a delay circuit including a plurality of delay elements, and a selector circuit for selecting the number of delay elements for every output stage of the delay circuit. A reference input signal and an output from the selector circuit for determining the period of the reference input signal are input to a phase comparator. The selector circuit is controlled on the basis of an output from the phase comparator to select the number of delay elements of the delay circuit, so as to generate a signal for multiplying a frequency by N, so that the signal is supplied to an exclusive NOR circuit to output a signal having a frequency an N-number of times that of the reference input signal.

Abstract: The invention in one embodiment is a semiconductor device including a logic unit capable of receiving a first clock signal having a first frequency and generating from the first clock signal a second clock signal having a second frequency higher than the first frequency.

Abstract: A negatively delayed signal generating circuit for compensating a duty rate of an input signal, wherein the negatively delayed signal has a larger frequency than that of the input signal and a stable duty rate regardless of the duty rate of the input signal, thereby being stably applicable to a memory device requiring a high speed operation.

Abstract: A digital frequency multiplier is provided that continues to adjust its multiplied frequency after the desired multiplied frequency is reached, that can be tested during operation and that is easily scalable. The digital frequency multiplier comprises a frequency detector, a frequency adjuster and a ring oscillator (RO). The frequency detector is configured for receiving a reference frequency and an RO output frequency, and for continuously monitoring a difference between the reference frequency and the RO output frequency. Based on the continuously monitored difference, the frequency detector continuously outputs an adjusting signal to the frequency adjuster. In response thereto, the frequency adjuster outputs selection data to the RO that adjusts the oscillation frequency of the RO, and thus the multiplied frequency of the digital frequency multiplier. Testable and growable logic circuitry are provided within the RO that allow the digital frequency multiplier to be tested during operation and easily scaled.

Abstract: A frequency multiplier is constructed to input an input signal to a transistor through an input matching circuit and to output a multiplied output signal from the transistor through a reflecting type fundamental wave signal band suppressing circuit and an output matching circuit. A transmission line produces a standing wave and is disposed between the output terminal of the transistor and the input terminal of the reflecting type fundamental wave signal band suppressing circuit. Because the voltage acting on the output terminal of the transistor consequently increases, the transistor operates at a point at which the nonlinearity of its input-output characteristic is greater and the output power of the multiplied output signal increases.

Abstract: A clock signal control circuit includes a divider for dividing an external clock signal into multiple phase clock signals, timing difference dividers connected to the divider for dividing a difference in input timing of pulse edge between the multiple phase clock signals having different phases from each other to generate different phase clock signals, multiplexers connected to the timing difference dividers for multiplexing the different phase multiplied clock signals to generate multiplexed clock signals, and a synthesizer connected to the multiplexers for synthesizing the multiplexed clock signals into a single multiplied clock signal.

Abstract: A three-input multiplier core circuit for multiplying first, second, and third initial input voltages V.sub.x, V.sub.y, and V.sub.z is provided, which is operable at a low supply voltage such as approximately 1 V is provided. This circuit includes an octtail cell having first to eighth bipolar transistors whose emitters are coupled together to be connected to a common constant current source/sink. Collectors of the first to fourth transistors are coupled together to form one of a pair of output terminals, and collectors of the fifth to eighth transistors are coupled together to form the other of the pair thereof. An output including the multiplication result is differentially derived from the pair of output terminals. Bases of the first to eighth transistors are respectively applied with voltages V.sub.1 to V.sub.8, where V.sub.1 =aV.sub.x +bV.sub.y +cV.sub.z, V.sub.2 =aV.sub.x +(b-1)V.sub.y +(c-1)V.sub.z, V.sub.3 =(a-1)V.sub.x +bV.sub.y +(c-1)V.sub.z, V.sub.4 =(a-1)V.sub.x +(b-1)V.sub.y +cV.sub.z, V.sub.

Abstract: A frequency multiplier integrated circuit (IC) has a frequency multiplier 1, an initialization signal generator 2, data sampling generator 3, and a clock generator 4. The frequency multiplier 1 has a timer 17 for calculating a first time between changes of state of an input signal, a time calculator 18 for a second time that a should occur between changes of state in the output signal, and an output signal generator 19 for generating the output signal. The initialization signal generator generates two initialization signals 12 and 13, one being the complement of the other, with a duration greater than 20 msec after an input initialization signal is received.

Abstract: This invention describes a circuit and method for creating a double clock frequency. The circuit uses a sequence of delay elements to delay the primary clock. A delay detector determines when a delayed clock is out of phase with the primary clock. A delay is selected that is one half the delay producing the out of phase delayed clock. The selected delay is used to combine with the primary clock to produce a double clock frequency. Control signals for selecting the "half" delayed clock are latched to prevent clock jitter and spurious signal from producing error signals in the double frequency clock. Different duty cycles can be established by varying the selected delay.

Abstract: In a frequency multiplier circuit, a first delaying section delays a reference signal and generates an output signal when the reference signal has been delayed by a predetermined delay time. A second delaying section generates n (n is an integer more than 0) delayed signals from the reference signal. The first delayed signal of the n delayed signals has a first delay time with respect to the reference signal, and an m-th delayed signal (m is a positive integer and m.ltoreq.n) of the n delayed signal has an m-th delay time with respect to the reference signal. The first through n-th delay times are integer multiples of the first delay time and the predetermined delay time is equal to (n+1) times the first delay time. The second delaying section has a plurality of different input locations for receiving the reference signal and one of the input locations is set to receive the reference signal in accordance with a setting signal from the first delaying section.

Abstract: A frequency multiplying circuit includes a plurality of frequency multipliers in a series array. The multiplying ratio of the initial stage frequency multiplier is the greatest compared with the remaining frequency multiplier or multipliers. Further, at least one of the frequency multipliers uses a voltage controlled delay circuit.

Abstract: A frequency multiplier for controlling a pulse width maintains a desired pulse width irrespective of a semiconductor fabrication process variation. The multiplier includes a delay unit for delaying an input signal and an exclusive OR-gate for exclusively ORing the delayed signal from the delay unit and the input signal. The multiplier further includes inverters that sequentially invert the signal from the exclusive OR-gate and a low-pass filter that filters the signal from the exclusive OR-gate. A high electric potential comparator and low electric potential comparator are for comparing the signal from the low-pass filter with first and second voltage limits to output first and second switch control signals to the delay unit, respectively.

Abstract: A two-quadrant multiplier for multiplying first and second signals, which can realize wide input voltage ranges at a low supply voltage such as 3 or 3.3 V, has a multitail cell. This multitail cell contains a pair of first and second transistors having differential input ends and differential output ends, a third transistor having an input end, and a constant current source for driving the pair and the third transistor. The first signal is applied across the differential input ends of the pair, and the second signal is applied in a single polarity (e.g., either a positive or negative polarity) to the input end of the third transistor. An output signal of the multiplier is a multiplication result of the first and second signals which is differentially derived from the differential output ends of the pair. At least one additional transistor may be provided, an input end of which is coupled with the input ends of the third transistor to be applied with the second signal.

Abstract: A clock multiplier controls the frequency of an output clock signal according to the frequency of an input clock signal by means of two feedback loops. The first feedback loop, active during a fixed number of initial cycles of the input clock signal, counts cycles of the output clock signal during each cycle of the input clock signal, and controls the output clock frequency according to the resulting count values. The second feedback loop, used after the fixed number of initial cycles, divides the frequency of the output clock signal, and controls the output clock frequency according to the phase difference between the resulting divided signal and the input clock signal.

Abstract: A current-mode four-quadrant analog multiplier is provided, which is constructed based on CMOS (complementary metal-oxide semiconductor) technology, capable of generating an output current signal which is proportional in magnitude to the product of two input current signals. This current-mode analog multiplier is designed based on the translinear circuit principle. The current-mode analog multiplier has high precision, wide current dynamic range, and is insensitive to temperature and process, suitable for use in VLSI implementation of many analog circuits and systems, such as fuzzy logic controllers and analog neural networks.

Abstract: A frequency gain display apparatus for an L/C band frequency up unit which is capable of generating a pulse for adjusting the gain of an L/C band frequency up unit used in a satellite system and a pulse for selecting a band width of a SAW (surface acoustic wave) filter and is capable of displaying a gain step of the same.