Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Abstract: A method for optimizing power of a ranging sequence includes counting at least one cycle of a first clock during a Crystal Oscillator (XO)-mode to generate a first cycle count. A second clock is activated at an end of the XO-mode. The first cycle count is converted into a fractional correction value by multiplying the first cycle count by a ratio of a second period of the second clock divided by a first period of the first clock. A first alignment of the first clock to the second clock is determined at a beginning of the XO-mode. A second alignment of the first clock to the second clock is determined at the end of the XO-mode. An adjusted cycle count is determined by summating the fractional correction value with a summation of the first alignment and the second alignment divided by the first period.

Abstract: A method and device for transmitting data reliably to at least one item of equipment is provided, wherein: from its initial clock H1, an item of equipment generates at least one first clock H1U from a rising edge of the initial clock H1 with a frequency F1U and a second clock H1D from a falling edge of the initial clock H1, with a frequency F1D, the item of equipment: reads the received data using at least one first rising edge of H1U and one falling edge consecutive to the first rising edge of H1U, then reads the received data using a first rising edge of H1D and a falling edge consecutive to the first rising edge of H1D, the four clock edges used being consecutive by 2F1, decodes at least the four messages using an error-correcting code, when at least one decoded message is correct, it uses the information contained in this message to drive a device linked to said item of equipment.

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys, and thereby is immune to traditional database hacking attacks.

Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys, and thereby is immune to traditional database hacking attacks.

Abstract: A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at a first input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connected in parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage.

Abstract: According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

Abstract: A processing circuit of a reset signal is provided. The processing circuit receives the reset signal via a reset end. The processing circuit includes a multiplexer, an inverter and a switching unit. The multiplexer has an output end, a first input end and a second input end. The multiplexer is utilized for connecting the output end to the first input end or the second input end according to a selection signal. The inverter is coupled to the second input end of the multiplexer. The switching unit is coupled to the reset end for receiving the reset signal and connecting the reset end to the first input end of the multiplexer or the inverter according to the selection signal.

Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys, and thereby is immune to traditional database hacking attacks.

Abstract: A device is disclosed that includes a delay circuit, a detection circuit, and a bias circuit. The delay circuit is configured to generate an oscillating signal in response to a reference signal, a first bias voltage, and a second bias voltage. The detection circuit is configured to compare the oscillating signal with the reference signal, to generate a detect signal. The bias circuit is configured to adjust the first bias voltage and the second bias voltage according to the detect signal and a reference voltage.

Abstract: Systems and methods for phase detection are disclosed. Phase alignment between first and second clock signals is detected using a comparison of outputs from a collapsible pipeline and a non-collapsible pipeline.

Abstract: For an error resilient pipeline, a Dynamically Adaptable Resilient Pipeline (DARP) controller determines a minimum error pipeline stage of a processor instruction pipeline with a minimum number of errors. In addition, the DARP controller determines a maximum error pipeline stage of the instruction pipeline with a maximum number of errors. The DARP controller increases a clock frequency for the instruction pipeline if the minimum number of errors of the minimum error pipeline stage is zero and the maximum number of errors of the maximum error pipeline stage does not exceed an error threshold. In addition, the DARP controller decreases the clock frequency if the minimum number of errors exceeds an error constant.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Abstract: Systems and methods for phase detection are disclosed. A collapsible three-stage pipeline includes a first register in a first stage having a first clock signal having first clock edges, a second register in a second stage that receives a first signal from the first stage, and having a second clock signal having second clock edges, and a third register in a third stage that receives a second signal from the second stage, and having a third clock signal having third clock edges, wherein each second clock edge has a corresponding first clock edge and a corresponding third clock edge. The circuitry may further include a two-stage pipeline including fourth and fifth stages, a counter that provides an input signal into the collapsible three-stage pipeline and the two-stage pipeline, and a comparator that compares a first output of the collapsible three-stage pipeline and a second output of the two-stage pipeline.

Abstract: A charge module is configured to pre-charge a control node to a pre-charged voltage, such that in a case a control module outputs a control voltage, a drive module is activated according to a gate voltage summed by the control voltage and the pre-charged voltage. The charge module includes a first switch, a charge switch, and a second switch. The first switch is configured to provide a first voltage to an operation node. The charge switch is configured to be switched on corresponding to the first voltage of the operation node, so as to charge the control node. The second switch is configured to provide a second voltage to the operation node according to the gate voltage.

Abstract: A frequency error calculator circuit calculates the frequency error in a basic clock based on the basic clock and on a reference clock having a frequency higher than the basic clock. An operation clock generator circuit outputs an operation clock whose error has been corrected based on the frequency error calculated by the frequency error calculator circuit. An ON/OFF control circuit outputs an ON/OFF control signal that specifies the calculation timing that the frequency error calculator circuit calculates the frequency error of the basic clock based on the frequency error calculated by the frequency error calculator circuit.

Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abstract: A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.

Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

Abstract: A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies. Accordingly, the on-chip reference clocks are generated to provide the required reference clocks to each of the PMAs.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.

Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

Abstract: A transmission system which couples a plurality of transmission devices to a control device includes a first transmission device which is one of the plurality of transmission devices; a first calculation circuit which calculates a first difference value indicating a frequency difference value between a common clock supplied from the control device and a first clock as a clock used in the first transmission device; and a transmitter which reports the first difference value to a second transmission device other than the first transmission device, wherein the second transmission device comprises: a second calculation circuit which calculates a second difference value indicating a frequency difference value between the common clock and a second clock used in the second transmission device, and a frequency controller which controls an oscillator generating the second clock so that the second difference value approaches the first difference value reported from the first transmission device.

Abstract: A data transfer system includes a transmission circuit, which operates by a first clock signal, and a receiving circuit, which operates by a second clock signal different from the first clock signal. The transmission circuit includes an output circuit that outputs a poll signal, of which a level is logically inverted in accordance with a transmission timing of transmission data from the transmission circuit to the receiving circuit. A first signal generating circuit receives the transmission data at a plurality of timings and generates plural sets of reception data corresponding to the plurality of timings. A second signal generating circuit receives the poll signal at the plurality of timings and generates synchronous poll signals corresponding to the plurality of timings. A data selecting circuit compares levels of the synchronous poll signals with each other and selects one of the sets of reception data based on the comparison result.

Abstract: A semiconductor device includes a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal, a phase inversion control unit configured to generate a phase inversion control signal, and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases.

Abstract: The PLL includes a voltage-controlled oscillator (VCO), a frequency down conversion circuit, a phase-frequency detector (PFD), and an adjusting circuit. The VCO is configured to generate an output dock signal. The frequency down conversion circuit is configured to receive the output dock signal and an auxiliary clock signal, and to mix the output clock signal and the auxiliary clock signal to generate a feedback clock signal. By detecting the strength of the feedback clock signal, it provides an auxiliary signal to adjust the frequency of the output clock signal. The PFD is configured to compare the frequencies and the phases of the feedback clock signal and a reference clock signal to generate an adjusting signal. The adjusting circuit is configured to receive the adjusting signal, and to adjust the frequency of the output clock signal generated by the VCO according to the adjusting signal.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.

Abstract: A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection signal, and determine a logic level of a reverse control signal in response to the first phase detection signal, a second phase detection block configured to compare a phase of a clock acquired by delaying the system clock by a correction time, generate a second phase detection signal, and determine a logic level of a clock select signal in response to the first and second phase detection signals, and a clock select block configured to select and output the data clock or a clock acquired by delaying the data clock.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

Abstract: Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit includes a multiplexer and a logic module coupled to the multiplexer. The multiplexer is configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. The logic module includes at least one of an XNOR and an XOR module and is configured to provide an output signal that is responsive to performing at least one of an XNOR and an XOR operation of the output of the multiplexer and an enable signal that enables or disables the clock gate circuit to generate the clock signal.

Abstract: It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit.

Abstract: The present invention discloses an electronic apparatus.

Abstract: A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: A switching DC converting device includes a switching DC converter and a synchronous clock circuit. The synchronous clock circuit is used to provide a wobbling synchronous clock input for the switching DC converter, and the central frequency of the wobbling synchronous clock avoids the operating frequency of a circuit powered by the switching DC converter.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The memory cell array has memory cells arranged therein at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a variable resistance element. The control circuit is configured to apply a voltage to a selected one of the first wirings and to a selected one of the second wirings. The control circuit includes a plurality of charge pump circuits and a plurality of clock oscillator circuits. The charge pump circuits generate a voltage applied to the first and second wirings. Each of the clock oscillator circuits is configured to supply a clock signal to a certain number of the charge pump circuits to control the timing of operation thereof. The clock oscillator circuits are configured to output clock signals at different frequencies.

Abstract: A count value generator includes an input for receiving a synchronizing count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronizing frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronizing frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronizing count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch.

Abstract: A data processing system comprises a plurality of sub-circuits, a clock generator provided with a control circuit, a pool of oscillator circuits comprising at least three oscillator circuits, and a multiplexing circuit coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input coupled to a control output of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input of each of the sub-circuits. The control circuit is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.

Abstract: Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.

Abstract: Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element.

Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Abstract: In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse.