Abstract: A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to receive a second clock signal, synchronous with the first clock signal, at a third frequency and an output intended to deliver a third clock signal at a frequency alternately equal to the first value or the third value.

Abstract: A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data.

Abstract: Disclosed herein is a phase-locked loop circuit including: a voltage controlled oscillator; a variable frequency divider circuit for frequency-dividing an oscillating signal of the voltage controlled oscillator into a 1/N (N is an integer) frequency; a phase comparator circuit for comparing phases of a frequency-divided signal and a reference signal of a reference frequency with each other; a charge pump circuit for outputting a charge pump current changed in pulse width; a loop filter for being supplied with the charge pump current and outputting a direct-current voltage changed in level; and a control circuit for calculating a value of the charge pump current as a function of the oscillating frequency of the voltage controlled oscillator and a coefficient for setting a phase locked loop band, and setting the value of the charge pump current in the charge pump circuit.

Abstract: Disclosed herein is a signal processing apparatus including: an input block receiving the predetermined number of items of data and a first enable signal taking an active state in an interval where data is valid in synchronization with a first clock; a count block counting the number of clocks in an interval where the first enable signal is inactive; an enable signal control block putting a second enable signal in an active state for the number of clocks equal to a predetermined number and putting the second enable signal in an inactive state for the number of clocks counted by the count block; an enable signal output block outputting the second enable signal; and a data output block outputting the predetermined number of items of data in synchronization with the second clock in an interval where the second enable signal is active.

Abstract: A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which transfers the internal clock signal and the long-period clock signal outputted from the clock output control circuit, a data input/output terminal, and an input/output circuit which outputs read data to the data input/output terminal in synchronization with the internal clock signal having been transferred by the clock transfer circuit.

Abstract: The phase detector compares the phase of a synchronous clock signal from the clock interpolator with the phase of serial data and outputs a phase error signal corresponding to a comparison result. The first integrator performs integration of the phase error signal and obtains a phase correction control signal for tracking phase shift of the serial data. The second integrator further performs integration of the phase correction control signal and obtains an up/down signal. The pattern generator generates a frequency correction control signal for tracking frequency shift of the serial data from the up/down signal. The product of the pattern length of the pattern generator and the count width of the second integrator is equal to or larger than a threshold that becomes larger as the count width of the first integrator is larger.

Abstract: The present invention relates to a frequency synthesizer comprising a main unit and a side unit. The main unit comprises a main phase detector to obtain a main control signal, a main oscillator that generates a main synthesized frequency output signal representing the frequency synthesizer output signal based on said main control signal, and a mixer that mixes said main synthesized frequency output signal with a side synthesized frequency output signal to obtain said mixer output signal. The side unit generates said side synthesized frequency output signal and comprises a frequency signal generation unit that provides a linear frequency sweep signal or a fixed-frequency control signal at a fine frequency resolution from said fixed-frequency side reference signal, and a side oscillator that generates said side synthesized frequency output signal based on said frequency sweep signal or said fixed-frequency control signal.

Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.

Abstract: Embodiments of a radio frequency (RF) circuit provide translational filtering in accordance with an input impedance response that is an impedance image of a reactive circuit impedance response from a polyphase reactive circuit. The RF circuit may include a first mixer circuit that provides a first frequency offset for the impedance image and a second mixer circuit that provides an additional frequency offset. Accordingly, the second mixer circuit may allow for adjustments to a total frequency offset of the impedance image. The second mixer circuit may also be configured so that the impedance image rejects a negative frequency impedance response of the reactive circuit impedance response.

Abstract: A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronization system connected to the master clocks. The synchronization system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network may include one or more slave synchronization data source for generating slave clock synchronization data derived from time information of the master clocks. The second sub-network may include one or more slave clocks and a slave clock time-base controller connected to the slave synchronization data source. The time-base controller may receive the slave clock synchronization data and control one or more of the one or more slave clocks in accordance with the slave clock synchronization data.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result.

Abstract: Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.

Abstract: Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit can include a multiplexer configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. Further, the clock gate circuit can include a logic module coupled to the multiplexer and configured to output the first logic signal and the second logic signal based on an enable signal and the output of the multiplexer.

Abstract: According to one embodiment, a data hold module is configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal differing from the first clock signal in frequency. A reception timing generator is configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal. The reception timing generator comprises flip-flops connected in cascade. An update timing adjusting module is configured to limit the timing to update the flip-flops in value on the basis of an update enable signal synchronized with the second clock signal.

Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: An electric circuit includes a first circuit, a second circuit, a synchronization detection circuit, a storage circuit, and a correction circuit. The first clock is configured to operate with a first clock, the second circuit is configured to operate with a second clock which is different in frequency from the first clock, and the synchronization detection circuit is configured to detect synchronization of the first and second clocks. The storage circuit is configured to store an output noise pattern of the second circuit, based on the synchronization detected by the synchronization detection circuit, and the correction circuit is configured to correct an output of the second circuit by using the output noise pattern.

Abstract: Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element.

Abstract: A method and a device having synchronizing capabilities, the device includes; (i) a first circuit that is adapted to receive a first clock signal; (ii) a second circuit that is adapted to receive a second clock signal; wherein the first and second clock signals and mutually asynchronous; and a (iii) synchronizer that is coupled between the first and second circuit and is adapted to receive the second clock signal, to receive an input signal from the first circuit and to output an output signal of definite values to the second circuit, wherein the input signal is synchronized with the first clock signal and the output signal is synchronized with the second clock signal.

Abstract: It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit.

Abstract: Provided is a synchronization detection circuit including: a multiphase clock generation circuit which includes a phase locked loop circuit that generates multiphase clock signals having a plurality of different phases, based on a reference clock signal, and which generates high-speed multiphase clock signals having a frequency obtained by multiplying a frequency of the reference clock signal, and low-speed multiphase clock signals having a frequency obtained by dividing a frequency of the high-speed multiphase clock signal; and a synchronous clock specifying circuit that specifies a clock signal synchronized with a synchronous signal from among the multiphase clock signals, and generates a synchronous position signal indicating a synchronous position of the synchronous signal, based on a comparison result between the synchronous signal and the high-speed multiphase clock signals and a comparison result between the synchronous signal and representative clock signals selected from the low-speed multiphase cloc

Abstract: A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

Abstract: A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.

Abstract: A circuit arrangement (10) for driving an electrical load (2) comprises an input (11) for feeding a power-supply voltage (Vs) with an AC component and an output (13) for providing an output signal (Sout) for driving a connectable electrical load (2). The circuit arrangement (10) further comprises a frequency processing circuit (20) for proving a reference frequency (f1) as a function of the AC component, and a demodulator (60) with a first input (61) for feeding the reference frequency (f1), with a second input (62) that is coupled to the input (11) of the circuit arrangement (10), and with an output (63) that is coupled to the output (13) of the circuit arrangement (10).

Abstract: Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

Abstract: A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register.

Abstract: Multi-lane PCI express busses devices, methods and systems are implemented in various fashions. According to one such implementation, a method is used for synchronizing data transfers between IC dies of a plurality of integrated-circuits (IC) dies. In a first IC die, a synchronizing signal is received and latched in a first clock domain and in the first IC die to produce a first latched output signal. The latched output signal is provided for use by each of the plurality of IC dies. In each of the plurality of IC dies, the first latched output signal is latched in the first clock domain to produce a second latched output signal. The second latched output signal is latched in a second clock domain to produce a third latched output signal. The third latched output signal is used to synchronize a respective communication lane.

Abstract: A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

Abstract: A clock signal generator circuit that receives periodic signals has a delay circuit, first and second multiplexers, and flip-flops. The delay circuit delays the periodic signals to generate delayed signals. The first multiplexer selects one of the delayed signals in response to a first select signal to generate an output clock signal. The second multiplexer selects one of the periodic signals in response to a second select signal. The flip-flops generate the first and the second select signals in response to the periodic signal selected by the second multiplexer.

Abstract: Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.

Abstract: Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: Embodiments of a synchronization circuit, a method for synchronizing clock signals, and electronic devices that include the synchronization circuit or a computer-program product (e.g., software) with instructions for operations in the method are described. This synchronization circuit synchronizes clock signals in different timing domains using state variables. In particular, the synchronization circuit generates a synchronization acquisition curve based on a temporal history of state-variable differences between the clock signals. Next, the synchronization circuit synchronizes the clock signals (without a discontinuous temporal transient in one or more state variables of a dependent one of the clock signals) based on the sum of the synchronization acquisition curve and the state-variable differences between the clock signals.

Abstract: A method is provided for estimating a frequency offset value. This method includes: receiving a signal from the transmitting device at the receiving device, the received signal having a transmitter frequency (510); generating a local signal at the receiving device, the local signal having a starting frequency (520); comparing a received signal phase and a local signal phase to determine an adjusted error signal representing a phase difference between the received signal and the local signal (530); adjusting a current frequency of the local signal from the starting frequency to the transmitting frequency over a time period (540); integrating the adjusted error signal over the time period to generate an integrated error signal (550); and filtering the integrated error signal to generate a frequency difference estimate indicative of the frequency difference between the transmitter frequency and the starting frequency (560).

Abstract: This disclosure relates to a phase locked loop and a frequency locked loop.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: Integrated circuit and process for aligning a first signal with a second signal. The integrated circuit includes a single latch, a switch control circuit coupled to an input of the single latch to align an edge of the first signal with an edge of the second signal, and a second switch control circuit coupled to the output of the single latch to produce a 50% duty cycle output.

Abstract: Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.

Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.