Abstract: A synchronizer eliminates metastability due to violation of either the setup time or the hold time of a circuit. The input of a first flip-flop (12a) is tied to a constant logic level (VDD or ground). The first flip-flop receives an asynchronous signal into the reset (preset or clear) input of the flip-flop. No violation of the setup or hold times of the flip-flop can occur. The second flip-flop (12c) receives the output of the first flip-flop as its clock input. The second flip-flop (12c) is configured as a toggler. The second flip-flop produces a synchronized partial signal (18a) of the original asynchronous signal (10a). Third and fourth flip-flops (12b,12d) may similarly be configured to produce a second synchronized partial signal (18b) of the asynchronous signal recovery and may prevent runt pulses from being received by the flip-flops.

Abstract: A test system for a design of a network device under test includes an oscillator configured for generating a first clock signal for a first clock domain, and field programmable gate arrays. Each field programmable gate array is configured for performing device operations according to the first clock domain and transferring data to another device at a network data rate based on a second clock domain. Each field programmable gate array includes clock conversion logic configured for generating a second clock signal for the second clock domain, based on the first clock signal. Hence, the generation of the second clock signal within each field programmable gate array ensures that timing accuracy is maintained, enabling communication between the field programmable gate arrays at high-speed data rates based on the second clock domain.

Abstract: A programmable current reference circuit is described. The programmable current reference circuit includes a programmable resistance, where the programmable resistance is programmable to provide one of a plurality of resistances, where each of the plurality of resistances corresponds to one of a plurality of programmable current reference circuit outputs. In one embodiment, the programmable current reference circuit includes a current source coupled to the programmable resistance. In one embodiment, the plurality of programmable current reference circuit outputs includes a plurality of reference currents. A phase locked loop including the programmable current reference circuit is also described.

Abstract: Methods and structure for improving accuracy of a master delay line associated with slave delay lines wherein the master delay line is design utilizing a higher clock frequency then the clock frequency applied to associated slave delay lines. The higher clock frequency applied to the master delay line in accordance with the present invention permits the master delay line to be comprised of fewer delay elements than would be the case for a master delay line using the same basic clock frequency as associated slave delay lines. The lower number of delay elements comprising the master delay line (i.e., the shorter length of the master delay line) helps reduce static phase errors associated with the master delay line inherent in the design, layout and fabrication of a longer delay line.

Abstract: A frequency synthesizer that includes an output oscillator, a difference circuit, a reference circuit, a feedback circuit and a comparator. The output oscillator generates an output signal whose frequency, FOUT, is determined by an oscillator input signal. The difference circuit generates a sampled signal having a frequency, Fsif=FOUT−FOFFSET. The reference circuit generates a reference signal having a frequency Fref. The reference circuit includes a reference oscillator for generating a high frequency reference oscillator output signal having a frequency F1 and a first division circuit for generating a signal having a frequency equal to F1 divided by R. The feedback circuit generates a feedback signal having a frequency, Ffb. The feedback signal generating circuit includes a second division circuit having a division factor chosen such that Fsif/Ffb is minimized. The comparator compares the reference signal and the feedback signal and generates the oscillator input signal.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module.

Abstract: A circuit (10) for producing a single output data (DOUT) stream and a corresponding single clock signal (CLKOUT). This circuit comprises an input for receiving a single input data stream (DIN), where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals (CLK0, CLK1), where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal (CLKF), where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling (L20, L21) the input data stream at the fast frequency, circuitry for outputting (M, LM) the sampled data as the single output data stream, and circuitry for outputting (CG) the single clock cycle in response to the fast clock signal.

Abstract: Circuitry and methodology for transferring a representation of a data signal between clock domains. In particular, the disclosure teaches a method for creating representations of signals input from a slow clock domain into a fast clock domain and vice versa. The methods and apparatus use a RAM-free architecture which may be easily incorporated into integrated circuits to enhance efficiency.

Abstract: A phase-locked loop circuit for providing a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequency range. The apparatus detects a frequency difference between at least one reference signal and an output signal, and generates a frequency error signal in response to the frequency difference. A phase difference is detected between a received input signal and the output signal, and a phase error signal is generated in response to the phase difference. The frequency error signal and the phase error signal are combined to control the frequency of the output signal by controlling an input-controlled oscillator.

Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.

Abstract: A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.

Abstract: A clock generation device includes a delay-locked loop and a plurality of programmable counters. The plurality of programmable counters are coupled to delay-locked loop. Each of the programmable counters has a separate output. The delay-locked loop is configured to generate a plurality of phase delay line outputs. A hard drive includes the delay-locked loop and the programmable counters, which generate multiple timing signals such as read, write, servo, and system timing signals. The method of generating timing signals includes delaying an input signal by a programmable delay and generating a plurality of timing pulses through the programmable counters.

Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Abstract: The invention relates to a digital timer (20) comprising a binary counter (21) driven by a counting clock signal (Hc), the counter (21) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS2) with a predetermined value when a counting order (N) is reached by the counter. According to the invention, the timer comprises wired logic means (22) arranged for detecting, at the output of the counter, a counting value (N−1) which is immediately before the counting order (N) in relation to the counting direction, and delivering an intermediate signal (DS1) with a predetermined value, as well means (24) for sampling the intermediate signal (DS1) at a moment when the counter receives the next counting pulse.

Abstract: The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.

Abstract: The present invention provides a logic unit and integrated circuit for clearing interrupts. The logic unit is coupled to a bus operating in a first clock domain, and is arranged to interface between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain. In accordance with the present invention, the logic unit comprises an interrupt source, responsive to a signal issued by the device, to assert a first interrupt signal in the second clock domain, and output logic, responsive to the first interrupt signal-to output a second interrupt signal via the bus to a processor operating in the first clock domain. The processor is arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt.

Abstract: A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference between the input signal and the output signal is zero, and a delay element control circuit for increasing and decreasing the phase of the output signal. This circuit design reduces processing delay, improves jitter performance, and extends the DLL operating frequency range.

Abstract: The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called “virtual” delay in the control loop of a PLL for the purpose of forcing the control loop to shift the phase of the PLL output clock signal, while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal, towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay, the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual is introduced by superimposing an external phasing control signal in the control loop of the PLL on the output signal/input signal of a control loop element.

Abstract: A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the successively connected plural ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors. A set line is connected to the other end of the successively connected plural ferroelectric capacitors. A bit line is connected to the drain of the reading transistor at one end thereof. A reset line is connected to the source of the reading transistor at one end thereof.

Abstract: This invention relates to an automatic detection method and apparatus for tuning the frequency and phase of displaying clock of a display to match the frequency and phase of pixel clock of a PC's display interface card. Based on the synchronized displaying clock, the image shown by digital display will be stable and bright in color. The automatic detection apparatus of invention includes a clock generation unit, a sampling unit, a data processing unit, an accumulation unit, and a decision unit. The clock generation unit creates a plurality of sampling clocks and according to these sampling packet sequences, the sampling unit samples and holds the pixel signals of image frames based on the pixel clock of display interface card, and then stores these data in its registers.

Abstract: The present invention includes a method and apparatus for smooth transitions (switching) between asynchronous clocks without the occurrence of glitches. In one embodiment the present invention is used when powering up and powering down a computer system and transitioning between a relatively faster primary clock and a slower alternate clock. In another embodiment the present invention is used for transitioning between a relatively faster primary clock to a slower alternate clock to conserve power, for example, when a laptop transitions between use mode and sleep mode.

Abstract: A method and apparatus for negotiating access to a shared resource by two independent domains. A request register is provided to each domain for receiving an ownership request signal. Request signals received from both domains are clock-synchronized and fed to a cross-coupled circuit. The cross-coupled circuit includes two blocks, each having a switch and a register for receiving a request signal. The registers are responsive to different portions of a clock cycle, e.g., rising and falling edges. The switch in each block receives a signal from one domain on one input and a signal from the output of the register in the same block on the other input. The switch of one block is controlled by the output signal of the register of the other block. The output of one of the blocks is used to control a domain switch to permit data streams from the independent domains to reach the shared resource. Each domain requests use of the shared resource by sending a request signal to its respective request register.

Abstract: A system and method for speed-up of the frequency switching time of a circuit, generally a voltage controlled oscillator having an operating frequency controlling input terminal. A first control circuit is coupled to the frequency controlling input terminal for maintaining the operating frequency of the oscillator at its first selected operating frequency. Circuitry is provided which is responsive to a directed change from the first operating frequency of the oscillator to a second different operating frequency of the oscillator to apply a voltage to the input terminal determined by the size of the directed change in the operating frequency and for a predetermined time period. This circuitry includes a switch coupled to the input terminal, a charge pump coupled to the switch and remote from the input terminal and a timer controlling the current output of the charge pump and the switch. The output of the charge pump is a current which is converted to a voltage.

Abstract: An apparatus comprising a memory section and a first circuit. The memory section may be configured to present a first output in response to (i) a first clock signal, (ii) a second clock signal, (iii) an input pulse and (iv) the first output. The first circuit may be configured to generate a second output in response to (i) the first output and (ii) the second clock signal, where the second output may comprise a pulse having a width equal to a period of the second clock signal. In one example, an input circuit may be configured to present the first output to the memory section in response to the input pulse and a first feedback of the output.

Abstract: A double-data rate (DDR) memory device is disclosed that can be configured for testing on an ordinary memory tester. The DDR memory may include a DDR input circuit (102), a single data rate input circuit (104), a word line control circuit (106), a bit line control circuit (108), and a memory cell array (110). Normal write operations may be performed by selecting the DDR input circuit (102). Test write operations may be performed by selecting the SDR input circuit (104). Such an arrangement can enable a DDR memory device to be tested in an ordinary SDR memory tester.

Abstract: A frequency-providing circuit is disclosed for providing an output signal at a frequency fout. The circuit comprises a frequency-generating unit, a frequency-changing circuit, and a synchronizing circuit. The frequency-generating unit receives a frequency-selecting control signal and provides a frequency output at a frequency fosc, whereby the frequency-generating unit is switchable between different frequencies substantially without a settling time. The frequency-changing circuit receives the frequency output and a frequency-changing control signal and derives the output signal therefrom, whereby the frequency fout of the output signal can be changed, with respect to the frequency fosc, in accordance with the setting of the frequency-changing control signal. The synchronizing circuit synchronizes the frequency-selecting control signal and the frequency-changing control signal.

Abstract: The present invention provides a circuit to transfer data from a first clocked domain to a second clocked domain. The circuit includes a first latch clocked by a first clock signal and a second latch clocked by a second clock signal that is faster than the first clock signal. The circuit further includes a clock enabling circuit to receive the second clock signal and the signal indicating that a transition of the first clock has occurred and to provide the second clock signal to the second latch after the transition of the first clock signal. In another embodiment, the present invention provides a circuit to transfer data from a first clock domain to a second clock domain that is asynchronous with respect to the first clock domain. The circuit includes a first latch sequenced by a first clock signal that has a first frequency and the second latch sequenced by a second clock signal that has a second frequency substantially lower than the first frequency.

Abstract: A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register.

Abstract: A serial bus speed-up circuit includes a data pattern detecting unit for detecting whether or not the data output from one of the devices to the serial bus consecutively takes the same value, and a clock frequency varying unit for increasing a frequency of the clock output to the serial bus when the data pattern detecting unit detects that the data consecutively takes the same value. By utilizing the fact that the valid delay time and the transition time of the data can be omitted in a case where there is no change in the data value, it is possible to increase the clock frequency and accordingly, increase the data transfer rate.

Abstract: A sampling clock signal generation circuit of a liquid crystal display device, includes a synchronousness compensation section receiving the reference synchronous signal and a master clock signal as input signals, to generate a synchronousness compensation signal, and a sampling clock signal generation section being initialized by the synchronousness compensation signal and dividing the master clock signal, to generate sampling clock signals synchronized with the reference synchronous signal.

Abstract: A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected. The latch has three sampling circuits (e.g., D flip-flops or DICE latches) that sample the logic data output at three different and distinct sampling times. The latch also has a sample release circuit coupled to the sampling circuits to select and output a majority of the samples collected by the sampling circuits at a fourth time that again is different and distinct from the three sampling times. The latch affords both spatial parallelism due to the multiple parallel sampling circuits and temporal parallelism resulting from the clocking scheme involving multiple time-spaced clock signals.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.

Abstract: A circuit for the glitch-free changeover between digital signals includes a multiplexer having a multiplicity of signal input terminals, signal select terminals and a signal output terminal. Furthermore, the circuit includes a counter logic unit for counting pulses in the output signal of the multiplexer and for outputting a count signal when a specific count value is reached. A delay logic unit delays a multiplexer select signal and outputs a switching signal and a delayed multiplexer select signal. During a set switching signal the counter logic unit is activated and the circuit output is deactivated.

Abstract: A method and apparatus for generating multiple frequency clock signals using a single input clock signal are provided. Each clock signal generated has a cycle time that is an integer multiple of the input clock cycle time. The fastest clock signal, i.e., the clock signal with the highest frequency generated has the same cycle time as the input clock. The rising edges of all the clock signals generated are synchronized and each clock signal generated has an approximate duty cycle of 50%. This is achieved by first applying the input clock signal to an input terminal of a plurality of registers and of a frequency control module of the signal generator, presenting control signals to input terminals of the registers and of the frequency control module, and generating a plurality of output clock signals in the frequency control module, dependent on the input clock signal and on the control signals.

Abstract: A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal.

Abstract: A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.

Abstract: A method and apparatus are provided for synchronizing communications between different integrated circuits having different individual clock rates. In accordance with exemplary embodiments of the invention, a common clock signal is provided having a frequency greater than or equal to the highest individual clock rate, and the common clock signal is divided to obtain individual clock signals for the different integrated circuits For each integrated circuit an arrangement including a switching device and an edge-triggered storage member is also provided. The arrangement has an input for receiving signals, for example from the other integrated circuits. The arrangement also has an output connected to an input of the integrated circuit. The common clock signal and the individual clock signal corresponding to the integrated circuit are provided to the arrangement.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

Abstract: A programmable device includes means for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Means for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the means for generating. The means for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created.

Abstract: An interface allowing to transfer serial test data from a Test Access Port (TAP) to controllers located in several clock domains is described. The clock frequencies can be different from each other and do not need to be related in phase to each other or with the clock of the TAP. The interface is proven to work reliably as long as the clock frequencies used for the test controllers and registers is 3 times higher than the one of the TAP used to source the serial test data.

Abstract: An even bus clock circuit generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a given range of processor clock to bus clock ratios that includes whole integers and half integers. The even bus clock circuit includes a delay element for receiving the bus clock and generating a delayed bus clock, a first flip-flop for receiving the processor clock at a data input and receiving the delayed bus clock at a clock input, and a second flip-flop for receiving a data output of the first flip-flop at a data input, receiving the processor clock at a clock input and generating a data output that is coupled to an asynchronous reset input of the first flip-flop. The logic pulses are generated at the data output of the first flip-flop and have a pulse width of substantially the same duration as a single cycle of the processor clock.

Abstract: A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

Abstract: An exchange system comprising a plurality of redundant clock supply modules for receiving respective clock signals to maintain synchronization. Each redundant clock supply module includes a phase locked loop coupled to receive a network synchronizing reference signal, for generating a most significant clock of the exchange system synchronized to the network synchronizing reference signal; a clock generator for counting the most significant clock to generate a plurality of system clocks including a least significant clock and a first frame pulse; and a redundancy synchronizer for synchronizing the first frame pulse and a second frame pulse from a counterpart redundancy module to generate a redundancy synchronization signal for establishing synchronization between redundancy modules from the most significant clock to the least significant clock.

Abstract: The present invention is directed to a method and apparatus for synchronizing one or more data signal lines of a data bus to multiple clocks, and for guaranteeing the validity of the synchronized values. Exemplary embodiments avoid the need to eliminate delays between the asynchronous clocks. Thus, exemplary embodiments of the present invention can be used for reliably synchronizing the in-pointer and out-pointer of a first-in first-out memory.

Abstract: To reduce drift in a sampling clock for framed data, a phase detector senses the time difference between (i) the time when a reference mark for the framed data is received and (ii) the time when the nominal number of oversampling clock cycles between reference timing marks is received. This difference is output to a clock controller which chooses a phase change rate based thereon. This phase change rate is applied to an oversampling clock to continuously, progressively, change the phase of the oversampling clock in a sense which tends to reduce this phase error. The phase changing clock is divided down by a frequency divider to generate a sampling clock. The phase of the oversampling clock is changed by generating multiple, equally spaced, phases of the oversampling clock and progressively changing the selection of the active phase.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A deviation of a clock rate of the timepiece clock signal is determined relative to a reference clock rate of a reference clock signal (CR) which is either issued while the mobile unit is switched on or is contained in a received signal. The reference clock rate is higher than the clock rate of the timepiece clock signal. A count number (N) is calculated based on the deviation of the clock rate of the timepiece clock signal. The clock signal is generated such that the clock pulses the clock signal are successively issued each time the clock pulses of the timepiece clock signal counted up to the count number.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.