Abstract: A frequency and/or phase locked loop architecture that eliminates the loop filter generally required in conventional phase locked loops, and which may be implemented in digital logic, for example, as a field programmable gate array. In one example, a frequency/phase locked loop includes both a frequency comparison component and a phase comparison component to allow locking of an output clock signal to both the frequency and phase of a reference signal.

Abstract: The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware.

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, including one or more of the following: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals by operating on the frequency reference clock signal, the plurality of frequencies signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator and selecting ones of said plurality of frequency signals and transmitting said selected ones of said plurality of frequency signals; and a plurality of differential units, each for receiving one of said selected ones of said plurality of frequency signals, each for applying a differential signal to said selected ones of said plurality of frequency signals, and each for adding time stamps to the selected ones of said plurality of frequency signals and outputting respective time sta

Abstract: A method for detecting which of two clock signals is the first to arrive may include providing a sense amplifier comprising first and second nodes located on first and second legs thereof. The sense amplifier is configured such that the first and second nodes have a substantially equivalent initial voltage. The method then includes receiving first and second clock signals. The sense amplifier is configured such that the voltage of the first node increases and the voltage of the second node decreases if the first clock signal arrives before the second clock signal. Similarly, the sense amplifier is configured such that the voltage of the second node increases and the voltage of the first node decreases if the second clock signal arrives before the first clock signal. The method may further include sampling the voltage of at least one of the first and second nodes to determine which of the first and second clock signals was the first to arrive.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.

Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

Abstract: A method and system are disclosed for reclocking a digital time-based signal. An exemplary method includes receiving a digital signal output at a first clock rate. Data transitions of the received digital signal are measured using a master clock having a second clock rate. The digital signal is filtered to determine approximate edge positions of the data transitions. A tolerance is enforced between the approximate edge positions to reconstruct the digital signal. The reconstructed signal is output. The exemplary system for reclocking a digital time-based signal includes an input section, a processor and a reconstruction section.

Abstract: Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two output signals including alternating samples of the input signal. Combinational logic circuitry is also provided to produce a clock-data recovery (CDR) signal indicative of the phase of the input signal with respect to a clock signal. The use of differential signals throughout the BBPD timing circuitry provides for the production of a low jitter CDR signal.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.

Abstract: Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the reference clock signal and generate a first output clock signal having a pre-determined frequency relative to the first frequency of the reference clock signal, and a second prescaler to receive the first output clock signal and generate a second output clock signal having a second pre-determined frequency relative to the first pre-determined frequency of the first output clock signal. The first output clock signal is substantially synchronous to the second output clock signal.

Abstract: Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing device, synchronizing a first timing reference of the multimedia decoder to a second timing reference of the multimedia encoder, receiving, at a network interface of the first multimedia processing device, an encoded multimedia data stream from a network interface of the second multimedia processing device, wherein the encoded multimedia data stream is encoded by the multimedia encoder based on the second clock and the second timing reference, and decoding the encoded multimedia data stream at the multimedia decoder based on the first clock and the first timing reference.

Abstract: A clock synchronization system includes a phase-locked loop to generate a multiplied clock based on a reference clock, a frequency divider to generate a plurality of frequency-divided clocks based on the multiplied clock, and a frame pulse generator to generate a frame pulse by frequency-dividing the reference clock, wherein the frequency-divided clocks are phase-locked by the frame pulse.

Abstract: A method for mitigating phase pulling in multiple frequency source system includes generating a first signal, the first signal referred to as an existing signal operating at an existing frequency point, the existing signal having a predefined pulling bandwidth around the existing frequency point. A request is received to generate a prospective signal at a prospective frequency point which is within the predefined pulling bandwidth of the existing signal. The prospective frequency is removed from within the predefined pulling bandwidth, and the prospective and existing signals are generated at the corresponding frequency points.

Abstract: A timing detection circuit including a first timing detection circuit, a second detection circuit, and an output circuit is disclosed. The first detection circuit detects, among multiphase clocks having n mutually different phases and a frequency of k times the frequency of a reference clock, a closest clock having a clock edge closest to a valid edge of the synchronizing signal and generates first detect signal DET_A indicating the detected clock. The second timing detection circuit detects within which of k successive cycles of the representative clock selected from the multiphase clocks the valid edge of the synchronizing signal is positioned and generates second detect signal DET_B indicating the detected cycle. The output circuit receives the first detect signal and the second detect signal and outputs first output signal OUT_A and second output signal OUT_B.

Abstract: The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

Abstract: A method and a system for configurably generating enabling pulse clocks are disclosed herein. In various embodiments, enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks.

Abstract: A ballast according to the present invention operates in an ignition state, a warm-up state, and a steady state for igniting and powering a lamp. The ballast comprises an igniter that ignites the lamp during the ignition state and a switching power inverter, for example, a full bridge DC-AC inverter implemented with MOSFET switching transistors, that powers the lamp during the warm-up and steady states. The switching power inverter, which drives the igniter, operates at a first switching frequency during the ignition state and operates at a second switching frequency during the steady state. Preferably, the first switching frequency, which in one exemplary embodiment is in the kHz range, is higher than the second switching frequency.

Abstract: Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment.

Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique comprises: creating a first code ring using the N-bit data sample, the first code ring having N ring-bit phase positions corresponding to N axis positions, with the N data bits of the N-bit data sample corresponding to one of the N ring-bit phase positions. Creating a pth Code Ring from a previous code ring using a preselected ring coding technique, the pth code ring having N ring-bit phase positions corresponding to N axis positions, with N data bits of the pth code ring corresponding to the N ring-bit phase positions of the pth code ring. Analyzing selected ones of the N data bits of the pth code ring for the presence of a sentinel condition.

Abstract: A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where the clock synchronization circuit has a sampling unit for sampling the second clock signal using the first clock signal in order to generate samples and edge detection values of the sampled second clock signal, a logic circuit for outputting the generated edge detection values as a reconstructed clock signal and generating an Edge-too-Early signal and an Edge-too-Late signal; and a signal delay circuit, which delays the reconstructed second clock signal on the bases of the Edge-too-Early signal or the Edge-too-Late signal.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: This invention provides a clock generator which is capable of improving modulation accuracy without accompanying an increase in consumption current by steady current when spectrum spread of a clock signal is executed. The phase balanced voltage Vf to be inputted to the voltage control oscillator (VCO) 9 is modulated within a dead band region in which no difference signals Pr, Pr are outputted from the charge pump circuit 7 when a difference in oscillation frequency between an output clock signal fo and a reference clock signal fr is detected. Consequently, the output clock signal fo is changed within the range of a lock frequency in a PLL circuit, so as to execute the spectrum spread of the output clock signal fo while maintaining the lock state of the oscillation frequency in the PLL circuit.

Abstract: A synchronization circuit for synchronizing low frequency digital circuitry and high frequency digital circuitry. The synchronization circuit produces an ordered series of clocks from the high-frequency digital clock. The clocks have a deterministic time relationship, with at least one clock having a period longer than the timing uncertainty associated with a synchronization signal. The synchronization signal is passed through a chain of latches, each one clocked by one of the divided down clocks with successively higher frequency. These latches align the synchronization signal with the clocks produced by the clock divider, ultimately aligning the synchronization signal with the high frequency clock. This synchronization circuit is described in connection with automatic test equipment used in the manufacture of semiconductor devices.

Abstract: A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input for receiving the externally generated main clock signal, a second input for receiving the internally generated ancillary clock signal, and an output for providing the externally generated main clock signal or the internally generated ancillary clock signal to a functional circuit. A resettable edge-triggered shift register has a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to the clock selection multiplexer for deselecting the internally generated ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.

Abstract: The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware.

Abstract: A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a clock frequency of second clock domain logic. Each flip flop is capable of sampling data only on an edge of a clock and outputting data only on an edge of the clock. By utilizing flip flops in the synchronizer, data values are only allowed to change on clock edges. This, in turn, greatly improves clock skew tolerance, and also setup time margins for the first clock domain logic and for the second clock domain logic.

Abstract: In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a pulse generator outputs the first to fourth signals successively. Received data stored in a receiving shift register is transferred to a received-data processing circuit synchronously with the first signal. The received data is further transferred to a timer-setting value register as a timer-setting value synchronously with the second signal. A timer present value is output from a timer present value register synchronously with the third signal. The timer present value is further written into a transmitting shift register as transmission data synchronously with the fourth signal.

Abstract: A oscillator controller (1300, 1500) is described. Differential logic receives a clock signal and an inverted version thereof (210, 210B) and an oscillator signal and an inverted version thereof (208, 208B), where the clock signal (210) and the oscillator signal (208) having different frequencies. The differential logic provides a differential output (1611, 1612) at least partially responsive to at least one of the clock signal and the oscillator signal. The differential logic is a combinational circuit in an oscillator alignment state and a sequential circuit in a hard-phase alignment state. Control signals (1317, 1318) are used in part to selectively alternate between putting the differential logic in the oscillator alignment state and in the hard-phase alignment state.

Abstract: Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.

Abstract: A method and circuit for transferring multiple bits of data across asynchronous clock domains is provided. The method includes detecting a change in a status bit of a data word being transferred from a source in a source clock domain to a destination register in a destination clock domain, the source clock and destination clock being asynchronous. The method includes sampling the detected change in reference to a change window where the change window is sized to encompass all bits of the data word. A stable input is selected for each bistable circuit of the destination register based on whether the detected change in the status bit is likely to produce metastability in the receiving register.

Abstract: A memory system includes a memory device that includes an active termination circuit. The memory system further includes a controller circuit that includes a frequency control circuit that is configured to modulate a system clock between a first frequency value and a second frequency value, greater than the first frequency value, responsive to a control signal. The controller circuit is further configured to determine an active termination value for the active termination circuit responsive to the system clock at the first frequency value, and to apply commands to the memory device responsive to the system clock at the second frequency value.

Abstract: For a phase-locked loop, disclosed is a method (and corresponding apparatus) for reducing electromagnetic interference caused by a clock signal produced by a voltage controlled oscillator, the method comprising: generating a control signal having a first type, e.g., sinusoidal, of slight variation in magnitude relative to a nominal magnitude value thereof; and providing the slightly varying control signal to a voltage-controlled oscillator (“VCO”) to obtain a clock signal exhibiting a second type, e.g., sinusoidal, of slight variation in frequency relative to a nominal frequency value thereof. The slight variation is non-negligible.

Abstract: An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Abstract: A method for switching between multiple clock signals in a digital circuit is provided that includes providing to a clock selector at least three distinct clock signals for the circuit. A master clock signal for the circuit is generated with the clock selector based on a first one of the distinct clock signals. The master clock signal is asynchronously blocked. The master clock signal for the circuit is generated with the clock selector based on a second one of the distinct clock signals. The master clock signal is synchronously unblocked.

Abstract: To be able to use a clock generation unit (2) for different mobile radio systems, the clock generation unit (2) which includes a phase-locked loop (4) for converting a reference clock (fR) into a working clock is provided and includes circuit portions (16a, 16b; 20a, 20b) which are designed for different reference clocks (fR) while a respective one of the circuit portions (16a, 20a) to which a special reference clock (fR) is assigned can be selected. The clock generation unit (2) can thus be operated with different reference clocks of different mobile radio systems.

Abstract: A gating signal checker system and method are provided to perform clock gating check on a logic cell. In accordance with one aspect of the invention, the system includes logic that determines a clock transition time of a clock input into the logic cell, and logic that determines a transition time of at least one gating signal input into the logic cell. Also included in the gating signal checker system is logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell, and logic that determines that the logic cell fails the clock gating check if the clock difference time is negative. In accordance with another aspect of the invention, a method performs a clock gating check on a logic cell by determining a clock transition time of a clock input into the logic cell, and determining a transition time of at least one gating signal input into the logic cell.

Abstract: A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line; a plurality of single logic circuits each including a plurality of transistors; a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits, said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.

Abstract: The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.