Abstract: In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.

Abstract: A phase-lock loop (PLL) circuit provides continuous closed-loop operation when switching between operating modes, which may be selection between multiple oscillators, multiple power modes or frequency divider/multipliers of an local clock generator having one or more oscillator circuits, or other changes that may disrupt operation of the PLL. The PLL includes a loop filter having an input coupled to an output of a phase-frequency comparator that compares the output of the oscillator circuit to a reference and a control circuit for storing and restoring the complete state of the loop filter from the storage in response to a change of operating mode, so that a lock time of the phase-lock loop circuit is reduced when selection of one of the at least two selectable different output frequency ranges of the local clock generator is changed.

Abstract: An integrator for use with a current sensor provides a feedback loop using a frequency discriminator, reducing drift while maintaining wide bandwidth.

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.

Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Abstract: A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.

Abstract: The present invention includes a voltage controlled oscillator circuit and a phase-locked loop device. The voltage controlled oscillator circuit comprises: a voltage-to-current conversion module, used for converting a control voltage of a voltage controlled oscillator into a control current as a linear function of the control voltage; and a current controlled oscillation module, used for outputting a low-amplitude oscillation signal based on the control current, so as to reduce power consumption. Further provided in the present invention is a phase-locked loop device comprising the voltage controlled oscillator circuit. According to the voltage controlled oscillator circuit, design parameters of low power consumption and high linearity may be achieved, thereby making a gain Kvco of the voltage controlled oscillator relatively stable, and it may be ensured that the voltage controlled oscillator and the phase-locked loop comprising the same have relatively excellent device performance.

Abstract: A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.

Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT). The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.

Abstract: A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.

Abstract: It is described a leakage compensation circuit for a measurement device which comprises a measurement circuit with a leaking device that is connected to a measurement path and causes a leakage current. The leakage compensation circuit comprises: i) a replica device of the leaking device, wherein the replica device is connected to a replica path, and wherein the replica device is configured to cause a replica leakage current that is essentially equal to the leakage current of the leaking device, ii) a voltage regulator which is connected to the measurement path and to the replica path, wherein the voltage regulator is configured to regulate the voltage in the replica path based on the voltage of the measurement path, and iii) a current mirror which is connected to the measurement path and to the replica path, wherein the current mirror is configured to mirror the replica leakage current of the replica device into the measurement path.

Abstract: An optical time of flight system includes a transmitter and a receiver. The transmitter is configured to generate a modulation signal having a modulation signal frequency that varies as a function of time, generate an optical waveform with amplitude modulation corresponding to the modulation signal, and direct the optical waveform toward a field of view (FOV). The receiver is configured to receive the optical waveform reflected off of an object within the FOV and determine a distance to the object based on a time of flight from the transmitter to the object and back to the receiver.

Abstract: Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF? terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: A sub-sampling phase-locked loop includes a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to the reference clock.

Abstract: A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.

Abstract: A voltage-controlled oscillator includes: a first transistor with its gate connected to an input terminal, its source connected to a first power supply, and its drain connected to a first node; a second transistor with its gate connected to a first bias voltage, its source connected to a second power supply, and its drain connected to the first node; and an inverter ring connected between the first node and the first power supply. The inverter ring is constituted by a plurality of stages of inverters connected in series, and an output of a final-stage inverter is connected to an output terminal and an input of an initial-stage inverter.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.

Abstract: A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal.

Abstract: An output terminal of a power supply circuit is coupled to a load. A control circuit charges multiple intermediate capacitors using an input voltage in a time-sharing manner. Furthermore, the control circuit selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors, and couples the intermediate capacitor thus selected to an output capacitor.

Abstract: According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.

Abstract: A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.

Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Abstract: Techniques are disclosed for phase detection in a phase-locked loop (PLL) control system, such as a millimeter-wave PLL. A PLL control system includes a voltage-controlled oscillator (VCO) circuit and a sub-sampling phase detector (SSPD). The VCO circuit is configured to generate an oscillating VCO output voltage based at least in part on an error signal generated by the SSPD. The error signal is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage. The SSPD includes a switched emitter-follower (SEF) sampling network, also referred to in this disclosure as an SEF circuit. In contrast to existing CMOS-based techniques, the SEF sampling network allows the SSPD to operate up to higher frequencies, for example, greater than 100 GHz, than possible using a CMOS sampler, and is also compatible with BiCMOS processes, which generally do not have access to advanced small-geometry CMOS.

Abstract: A phase locked loop of the present disclosure includes a phase comparator circuit, a loop filter, an oscillator circuit, an AD converter circuit, and a current generator circuit. The phase comparator circuit compares a phase of a first signal and a phase of a second signal based on a clock signal. The loop filter includes a resistor element and a capacitor element, and generates a control voltage on the basis of a phase comparison result of the phase comparator circuit. The resistor element has one end coupled to a first node and another end coupled to a second node. The capacitor element has one end coupled to the second node. The oscillator circuit generates the clock signal on the basis of the control voltage. The AD converter circuit converts a voltage difference between the two ends of the resistor element into a digital code. The current generator circuit generates a first current on the basis of the digital code and supplies the first current to the second node.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed back to a high-speed phase mixer to adjust/align the sampling point clock to the initial clock. Subsequently, the duplicate clock is generated and utilized to determine an optimal sampling point phase while the data sampling clock is utilized to read the received data signal, and then the closed-loop clock alignment circuit is re-used to re-align the data sampling clock to the duplicate clock when the optimal sampling point phase is identified.

Abstract: Example radar apparatuses including a phase lock loop circuit used for processing both transmission signals and reflection signals are provided herein. An example apparatus includes a transmit signal generator electrically connected to an antenna and configured to generate a transmission signal at a transmit frequency, a receiver circuit electrically connected to the antenna and configured to receive a radar return signal and downconvert the radar return signal at a downconvert frequency for signal processing, and a phase lock loop circuit configured to be tuned to output both at the transmit frequency for transmission of the transmission signal by the antenna and the downconvert frequency for downconverting a frequency of the radar return signal for further signal processing. The transmit frequency is different from the downconvert frequency.

Abstract: A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.

Abstract: In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further includes a multiplexer including a first input, a second input, and an output, wherein the first input of the multiplexer is configured to receive a first clock signal, the second input of the multiplexer is configured to receive a second clock signal, and the output of the multiplexer is coupled to the clock input of the bias generator.

Abstract: A Phase-locked loop circuit including: a local oscillator, configured to generate a timing signal; a variable-length shift register, controlled by the timing signal; and a feedback control circuit, which receives a pulsed input signal and receives a local signal from the shift register. The feedback control circuit detects whether each pulse of the input signal respects a condition of temporal proximity with a corresponding pulse of the local signal and detects, for each pulse of the input signal that respects the proximity condition, whether the edge falls early, late, or within a predefined portion of the corresponding pulse of the local signal. The feedback control circuit controls the length of the shift register and the frequency of the timing signal, as a function of the detections made.

Abstract: The present invention provides a delta-sigma modulator and associated signal processing method, wherein the signal processing method includes: generating a first difference signal according to a difference between an input signal and a first feedback signal; filtering the first difference signal to generate a filtered signal; generating a second difference signal according to a difference between the filtered signal and a second feedback signal; quantizing the second difference signal to generate an output signal; using a first DAC to generate the first feedback signal according to the output signal; using a second DAC to generate a first analog signal according to the output signal; delaying the output signal to generate a first delayed output signal; using a third DAC to generate a second analog signal according to the first delayed output signal; and generating the second feedback signal according to the first analog signal and the second analog signal.

Abstract: A pump circuit is disclosed. The pump circuit includes a first pump core circuit and a second pump core circuit. The second pump core circuit is coupled to the first pump core circuit. When a voltage value of a power source input to the pump circuit is not lower than a threshold voltage value, the first pump core circuit is operated and the second pump core circuit is not operated. When the voltage value of the power source is lower than the threshold voltage value, the first pump core circuit and the second pump core circuit are operated, so that a current value of the output current transmitted by the pump circuit is not lower than a threshold current value.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.

Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

Abstract: Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

Abstract: A clock filter includes a ring oscillator comprising a plurality of inverters cascaded in a ring topology and configured to output a plurality of internal voltages including a first internal voltage and a second internal voltage. The clock filter further includes a coupling circuit configured to couple an input voltage to the first internal voltage, a sampling circuit configured to output a control voltage by sampling the second internal voltage in accordance with the input voltage, and a current source configured to output the bias current in accordance with the control voltage.

Abstract: A clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pump unit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, the current-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.

Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.