With Charge Pump Patents (Class 327/157)
  • Patent number: 11228317
    Abstract: A sub-sampling phase-locked loop includes a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to the reference clock.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: January 18, 2022
    Assignee: Korea University Research and Business Foundation
    Inventors: Chul Woo Kim, Yoon Jae Choi
  • Patent number: 11228319
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: January 18, 2022
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 11218152
    Abstract: A charge pump circuit and phase-locked loop include start, bias, current mirror, charging and discharging feedback control, and charging and discharging matching modules, which are electrically connected in sequence. The start module starts the bias module. The bias module generates constant bias current and outputs same to the current mirror module, which receives and amplifies the bias current for output in two paths. The charging and discharging feedback control module detects the output voltage of a charge pump and controls, according to feedback of the output voltage, the current in the charging and discharging matching module, to suppress the mismatch between charging and discharging currents. The charging and discharging matching module receives an external charging or discharging control signal, to charge or discharge the output load of the charge pump. Charging and discharging currents can be matched within a wide output voltage range, without an operational amplifier.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 4, 2022
    Assignees: CHINA COMMUNICATION MICROELECTRONICS TECHNOLOGY CO., LTD., CHINA COMMUNICATION TECHNOLOGY CO., LTD.
    Inventors: Qing Ding, Haifeng Zhou, Guangsheng Wu, Xiaocong Li
  • Patent number: 11206028
    Abstract: A voltage-controlled oscillator includes: a first transistor with its gate connected to an input terminal, its source connected to a first power supply, and its drain connected to a first node; a second transistor with its gate connected to a first bias voltage, its source connected to a second power supply, and its drain connected to the first node; and an inverter ring connected between the first node and the first power supply. The inverter ring is constituted by a plurality of stages of inverters connected in series, and an output of a final-stage inverter is connected to an output terminal and an input of an initial-stage inverter.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 21, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Yoji Bando, Heiji Ikoma
  • Patent number: 11201624
    Abstract: A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: December 14, 2021
    Inventor: Hideo Haneda
  • Patent number: 11201625
    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11190190
    Abstract: An output terminal of a power supply circuit is coupled to a load. A control circuit charges multiple intermediate capacitors using an input voltage in a time-sharing manner. Furthermore, the control circuit selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors, and couples the intermediate capacitor thus selected to an output capacitor.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 30, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Masanobu Tsuji
  • Patent number: 11115032
    Abstract: According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: September 7, 2021
    Inventors: Ashish Lachhwani, Gireesh Rajendran
  • Patent number: 11095292
    Abstract: A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 17, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: David Lachartre
  • Patent number: 11031942
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 11005482
    Abstract: Techniques are disclosed for phase detection in a phase-locked loop (PLL) control system, such as a millimeter-wave PLL. A PLL control system includes a voltage-controlled oscillator (VCO) circuit and a sub-sampling phase detector (SSPD). The VCO circuit is configured to generate an oscillating VCO output voltage based at least in part on an error signal generated by the SSPD. The error signal is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage. The SSPD includes a switched emitter-follower (SEF) sampling network, also referred to in this disclosure as an SEF circuit. In contrast to existing CMOS-based techniques, the SEF sampling network allows the SSPD to operate up to higher frequencies, for example, greater than 100 GHz, than possible using a CMOS sampler, and is also compatible with BiCMOS processes, which generally do not have access to advanced small-geometry CMOS.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: May 11, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Mark E. Stuenkel, Mark D. Hickle
  • Patent number: 10998908
    Abstract: A phase locked loop of the present disclosure includes a phase comparator circuit, a loop filter, an oscillator circuit, an AD converter circuit, and a current generator circuit. The phase comparator circuit compares a phase of a first signal and a phase of a second signal based on a clock signal. The loop filter includes a resistor element and a capacitor element, and generates a control voltage on the basis of a phase comparison result of the phase comparator circuit. The resistor element has one end coupled to a first node and another end coupled to a second node. The capacitor element has one end coupled to the second node. The oscillator circuit generates the clock signal on the basis of the control voltage. The AD converter circuit converts a voltage difference between the two ends of the resistor element into a digital code. The current generator circuit generates a first current on the basis of the digital code and supplies the first current to the second node.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 4, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yinta Lin
  • Patent number: 10985766
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: April 20, 2021
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10944406
    Abstract: A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed back to a high-speed phase mixer to adjust/align the sampling point clock to the initial clock. Subsequently, the duplicate clock is generated and utilized to determine an optimal sampling point phase while the data sampling clock is utilized to read the received data signal, and then the closed-loop clock alignment circuit is re-used to re-align the data sampling clock to the duplicate clock when the optimal sampling point phase is identified.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 9, 2021
    Assignee: Synopsys, Inc.
    Inventors: Zhenchang Du, Choon H. Leong, David A. Yokoyama-Martin, John T. Stonick, Skye Wolfer
  • Patent number: 10935631
    Abstract: Example radar apparatuses including a phase lock loop circuit used for processing both transmission signals and reflection signals are provided herein. An example apparatus includes a transmit signal generator electrically connected to an antenna and configured to generate a transmission signal at a transmit frequency, a receiver circuit electrically connected to the antenna and configured to receive a radar return signal and downconvert the radar return signal at a downconvert frequency for signal processing, and a phase lock loop circuit configured to be tuned to output both at the transmit frequency for transmission of the transmission signal by the antenna and the downconvert frequency for downconverting a frequency of the radar return signal for further signal processing. The transmit frequency is different from the downconvert frequency.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 2, 2021
    Assignee: NAVICO HOLDING AS
    Inventors: Gregor Storz, Michael Cann
  • Patent number: 10908635
    Abstract: A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: February 2, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Harihara Subramanian Ranganathan, Vivek Sarda
  • Patent number: 10879882
    Abstract: In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further includes a multiplexer including a first input, a second input, and an output, wherein the first input of the multiplexer is configured to receive a first clock signal, the second input of the multiplexer is configured to receive a second clock signal, and the output of the multiplexer is coupled to the clock input of the bias generator.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: George Shing, Michael Fertsch
  • Patent number: 10879909
    Abstract: A Phase-locked loop circuit including: a local oscillator, configured to generate a timing signal; a variable-length shift register, controlled by the timing signal; and a feedback control circuit, which receives a pulsed input signal and receives a local signal from the shift register. The feedback control circuit detects whether each pulse of the input signal respects a condition of temporal proximity with a corresponding pulse of the local signal and detects, for each pulse of the input signal that respects the proximity condition, whether the edge falls early, late, or within a predefined portion of the corresponding pulse of the local signal. The feedback control circuit controls the length of the shift register and the frequency of the timing signal, as a function of the detections made.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 29, 2020
    Inventors: Marco Crepaldi, Gian Nicola Angotzi, Luca Berdondini
  • Patent number: 10879924
    Abstract: The present invention provides a delta-sigma modulator and associated signal processing method, wherein the signal processing method includes: generating a first difference signal according to a difference between an input signal and a first feedback signal; filtering the first difference signal to generate a filtered signal; generating a second difference signal according to a difference between the filtered signal and a second feedback signal; quantizing the second difference signal to generate an output signal; using a first DAC to generate the first feedback signal according to the output signal; using a second DAC to generate a first analog signal according to the output signal; delaying the output signal to generate a first delayed output signal; using a third DAC to generate a second analog signal according to the first delayed output signal; and generating the second feedback signal according to the first analog signal and the second analog signal.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventor: Xiaobo Zhou
  • Patent number: 10868546
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10868467
    Abstract: A pump circuit is disclosed. The pump circuit includes a first pump core circuit and a second pump core circuit. The second pump core circuit is coupled to the first pump core circuit. When a voltage value of a power source input to the pump circuit is not lower than a threshold voltage value, the first pump core circuit is operated and the second pump core circuit is not operated. When the voltage value of the power source is lower than the threshold voltage value, the first pump core circuit and the second pump core circuit are operated, so that a current value of the output current transmitted by the pump circuit is not lower than a threshold current value.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 15, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10862487
    Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Gupta, Nitin Jain
  • Patent number: 10855292
    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10840319
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10826387
    Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Vladislav Dyachenko, Nenad Pavlovic
  • Patent number: 10804912
    Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Utku Seckin, Simone Gambini, Benjamin W. Cook
  • Patent number: 10784872
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10778235
    Abstract: Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: September 15, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Yuval Kirschner
  • Patent number: 10771065
    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 8, 2020
    Assignee: INPHI CORPORATION
    Inventors: Simon Forey, Parmanand Mishra, Michael S. Harwood, Rajasekhar Nagulapalli
  • Patent number: 10763871
    Abstract: Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Manoj Kumar Patasani, Tarik Saric, Juan Felipe Osorio Tamayo
  • Patent number: 10720929
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 21, 2020
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10700669
    Abstract: A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 30, 2020
    Assignee: Aura Semiconductor Pvt. Ltd
    Inventors: Nigesh Baladhandapani, Sharanaprasad Melkundi, Raja Prabhu J, Augusto Marques
  • Patent number: 10686429
    Abstract: A clock filter includes a ring oscillator comprising a plurality of inverters cascaded in a ring topology and configured to output a plurality of internal voltages including a first internal voltage and a second internal voltage. The clock filter further includes a coupling circuit configured to couple an input voltage to the first internal voltage, a sampling circuit configured to output a control voltage by sampling the second internal voltage in accordance with the input voltage, and a current source configured to output the bias current in accordance with the control voltage.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 16, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10686454
    Abstract: A clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pump unit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, the current-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 16, 2020
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventor: Ming-Ting Wu
  • Patent number: 10630461
    Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Valentin Abramzon
  • Patent number: 10623007
    Abstract: An apparatus includes an oscillator circuit that may generate a clock signal with a frequency that is based on a voltage level of a control node, and a charge pump circuit that includes a first current source and a second current source. The first current source may be coupled between a first supply node and a first circuit node. The second current source may be coupled between a second supply node and a second circuit node. The charge pump circuit may be configured to pre-charge the first and second circuit nodes to voltage levels that differ from the control node and the first and second supply nodes. In addition, the charge pump circuit may select, based on phase information, either the first or second circuit node, and then modify, based on a voltage level of the selected circuit node, a voltage level of the control node.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Apple Inc.
    Inventors: Robert K. Kong, Shaobo Liu, Dennis M. Fischette, Jr., Patrick J Landy
  • Patent number: 10601312
    Abstract: An RF circuit comprises a charge pump configured to generate current pulses having a first current amplitude and a predetermined duration; and a capacitive element configured to receive the current pulses and to generate a tuning voltage depending thereon. An RF oscillator is configured to generate an RF signal having a frequency that is dependent on the tuning voltage. The RF circuit comprises a measuring circuit configured to generate a measurement signal representing the tuning voltage or the frequency of the RF signal. A controller circuit is configured to drive the charge pump in order to change the first amplitude of a current pulse by a current difference, and ascertain a first change in the measurement signal and a second change in the measurement signal. A measurement value for the first amplitude can be calculated based on the first change and the second change based on the current difference.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventor: Lukas Heschl
  • Patent number: 10573700
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 25, 2020
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10560080
    Abstract: A duty cycle correction circuit is disclosed. The duty cycle correction circuit includes an input stage, an output stage and a feedback component including a feedback amplifier and a low pass filter. The feedback component compares and adjusts the duty cycle of a signal from an input stage to a target value via a control voltage. The input stage reduces the rise and fall times of received signal to increase the duty cycle sensitivity to a control voltage from the feedback component. The output of the output stage is coupled to the input of the feedback component and the output stage amplifiers the duty cycle adjusted signal processed by both input stage and feedback component.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 11, 2020
    Assignee: NXP B.V.
    Inventors: Xu Zhang, Siamak Delshadpour, Ahmad Yazdi
  • Patent number: 10559678
    Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, ALi Salih
  • Patent number: 10535723
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 14, 2020
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10521638
    Abstract: The present invention provides a fingerprint identification system includes a charge pump circuit configured to generate a supply voltage, wherein the charge pump circuit receives a first clock signal; a pixel circuit, forming a touch capacitance, determining whether the pixel circuit is corresponding to a finger valley or a finger ridge according to the touch capacitance, wherein the pixel circuit receives a second clock signal and the supply voltage; and a clock generating circuit, configured to generate the first clock signal and the second clock signal; wherein the first clock signal is related to the second clock signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 31, 2019
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Hsmlun Li, MengTa Yang
  • Patent number: 10510387
    Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian Gradinariu, Gary Peter Moscaluk, Roger Jay Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 10498527
    Abstract: A communication system according to the present disclosure includes a transmission device and a reception device. The transmission device includes a phase synchronizer, a generator, and a controller. The phase synchronizer generates a first clock signal, and is configured to be able to change a frequency of the first clock signal. The generator generates a transmission signal on the basis of the first clock signal. The controller controls the generator and the phase synchronizer to change the frequency of the first clock signal while generating the transmission signal. The reception device receives the transmission signal.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 3, 2019
    Assignee: SONY CORPORATION
    Inventors: Ryota Shinoda, Takashi Masuda
  • Patent number: 10498231
    Abstract: Charge pump circuitry comprises a differential amplifier and parallel-connected reference, auxiliary and output current paths comprising first current-mirror transistors connected so an auxiliary current and a first output current along a first part of the output current path are dependent on the reference current. The auxiliary and output current paths comprise second-current-mirror transistors connected so a second output current flowing along a second part of the output current path is dependent on the auxiliary current. The auxiliary current path comprises a control transistor connected in series with the first-current-mirror transistor of that path. The differential amplifier receives first and second input signals from nodes in the auxiliary and output current paths, respectively, and controls the control transistor with its amplifier output signal to control the drain or collector voltage of the first-current mirror transistor in the auxiliary path.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 3, 2019
    Assignee: SOCIONEXT, INC.
    Inventor: David Hany Gaied Mikhael
  • Patent number: 10483845
    Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 19, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yu-Li Hsueh, Chih-Hsien Shen, Chao-Ching Hung, Po-Chun Huang
  • Patent number: 10476511
    Abstract: A PLL circuit includes a phase comparator, first and second charge pumps, a filter generating a first control voltage from a current of the first charge pump, a comparator comparing a voltage of a first node with a reference voltage, a switch section outputting the reference voltage to the first node and outputting a current of the second charge pump to a second node in a high-speed lock mode, and outputting the current of the second charge pump to the first node and outputting a result from the comparator to the second node in a normal lock mode, a second filter generating a second control voltage by integrating a current of the first node, a third filter generating a third control voltage by integrating a current of the second node, and a voltage controlled oscillator generating a clock signal of a frequency corresponding to the first to third control voltages.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuyuki Hiraku
  • Patent number: 10473530
    Abstract: A temperature sensor configured to generate a temperature-indicating signal with improved accuracy over a wide temperature range is disclosed. The temperature sensor includes a first oscillator configured to generate a first oscillating signal with a first frequency that varies with a sensed temperature and a reference parameter; a second oscillator configured to generate a second oscillating signal with a second frequency that varies with the reference parameter; and a time-to-digital converter (TDC) configured to generate a digital output indicative of the sensed temperature based on a ratio of the first frequency to the second frequency. Because the first and second frequencies depend on the reference parameter, and the temperature-indicating signal is a function of the ratio of the first and second frequencies, temperature-variation in the reference parameter cancels out in the temperature-indicating signal.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 12, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Philex Ming-Yan Fan, Richard Nguyen, Manjunatha Poojary
  • Patent number: 10461755
    Abstract: We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 29, 2019
    Assignee: Oracle International Corporation
    Inventors: Guanghua Shu, Frankie Y. Liu, Suwen Yang, Ziad Saleh Shehadeh, Eric Y. Chang
  • Patent number: 10439624
    Abstract: A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: October 8, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober, Herbert M Shapiro