With Charge Pump Patents (Class 327/157)
  • Patent number: 10411593
    Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Valentin Abramzon, Amir Amirkhany, Anup P. Jose
  • Patent number: 10401409
    Abstract: According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Cesare Buffa, Luis Hernandez-Corporales, Andreas Wiesbauer, Enrique Prefasi
  • Patent number: 10396657
    Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10395035
    Abstract: Some embodiments include apparatuses having diffusion regions located adjacent each other in a substrate, and connections coupled to the diffusion regions. The diffusion regions include first diffusion regions, second diffusion regions, and third diffusion regions. One of the second diffusion regions and one of the third diffusion regions are between two of the first diffusion regions. One of the first diffusion regions and one of the third diffusion regions are between two of the second diffusion regions. The connections include a first connection coupled to each of the first diffusion regions, a second connection coupled to each of the second diffusion regions, and a third connection coupled to each of the third diffusion regions.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Sudhir K Satpathy, Vikram B Suresh, Patrick Koeberl
  • Patent number: 10389371
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 20, 2019
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10374617
    Abstract: A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Ting-Kuei Kuan, Chin-Yang Wu, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10360840
    Abstract: To achieve a pixel circuit and the like capable of improving the accuracy for detecting the threshold voltage. The pixel circuit includes: a light emitting element; a driving transistor which supplies an electric current to the light emitting element according to an applied voltage; a capacitor part which holds a voltage containing a threshold voltage and a data voltage of the driving transistor and applies the voltage to the driving transistor; and a switch part which makes the capacitor part hold the voltage containing the threshold voltage and the data voltage. The switch part includes a reference voltage transistor which inputs a reference voltage from a reference voltage power supply line and a data voltage transistor which inputs a data voltage from a data line.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 23, 2019
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Yojiro Matsueda, Yoshihiro Nonaka, Kenichi Takatori
  • Patent number: 10348314
    Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 9, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Gagan Midha
  • Patent number: 10348414
    Abstract: A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 9, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ajay Yadav, Samir Aboulhouda, Faouzi Chaahoub
  • Patent number: 10333530
    Abstract: According to one embodiment, a voltage-controlled oscillator includes a voltage-current conversion circuit and hold circuit that outputs a first current corresponding to a control voltage, a current addition circuit that outputs a second current corresponding to the first current, and a current subtraction circuit that outputs a third current corresponding to the first current. The voltage-controlled oscillator also includes a narrow-band low-pass filter that passes a current in a first frequency band to reduce noise of the second current, a voltage-current converter that outputs a sixth current corresponding to a fifth current obtained by subtracting the third current from a fourth current corresponding to the control voltage, and a low-pass filter that passes a current in a second frequency band to reduce noise of the sixth current. The second frequency band is different from the first frequency band.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Makihiko Katsuragi
  • Patent number: 10297653
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 21, 2019
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10277117
    Abstract: A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10270341
    Abstract: A regulator circuit includes a first transistor reducing an external supply voltage and outputting an internal active voltage to an output node; a first detector receiving a criteria level, detecting the internal active voltage based on an enable signal, controlling a gate voltage of the first transistor, and adjusting an output current thereof; a second transistor reducing the external supply voltage, and outputting an internal standby voltage corresponding to the internal active voltage to the output node; a second detector receiving a reference voltage, detecting the internal standby voltage regardless of the enable signal, controlling a gate voltage of the second transistor, and adjusting an output current thereof; a first switch controlling whether to output the reference voltage as the criteria level of the first detector; and a second switch controlling whether to output the voltage of the output node as the criteria level of the first detector.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 23, 2019
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Atsushi Nakakubo
  • Patent number: 10211843
    Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 19, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • Patent number: 10199933
    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 5, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter Vlasenko, Huy Tuong Mai
  • Patent number: 10199986
    Abstract: Systems and methods are provided in which a voltage-controlled oscillator for a radio transmitter includes a LC tank circuit, and a muting circuit. The LC tank circuit includes an inductive element and a capacitive element; wherein the inductive element of the LC tank circuit includes the antenna of the transmitter. The muting circuit can include a variable resistor connected in parallel with the LC tank circuit.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 5, 2019
    Assignee: Olympus Corporation
    Inventors: John B. Groe, Anton Karnitski, Kishore Rama Rao
  • Patent number: 10171032
    Abstract: Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on a reference voltage. The pulse generator circuit may include a capacitor coupled between a first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the node in response to the periodic pulse, a resistor and a diode coupled in series between a second node and a second reference voltage, and a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and the a current.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jun Wu, Dong Pan
  • Patent number: 10164618
    Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
  • Patent number: 10153927
    Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 11, 2018
    Assignee: Nordic Semiconductor ASA
    Inventors: Ruben Undheim, Ola Bruset
  • Patent number: 10144373
    Abstract: A power supply system control device for controlling a power supply system including an electric generator, a first electricity storage configured to be charged with and to discharge electric power generated by the electric generator, a second electricity storage configured to be charged with and to discharge the generated electric power, two paths connecting between the first electricity storage and the second electricity storage, a switching unit including a first switch configured to switch between a conductive state and a non-conductive state of one of the paths, and a second switch configured to switch between a conductive state and a non-conductive state of the other of the paths, and an electric load of a vehicle that is connected to the first electricity storage side of the switching unit.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: December 4, 2018
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Masahiko Tahara, Terumasa Tsuchiya, Atsushi Tezuka, Tomoyuki Koike, Munemitsu Watanabe, Akifumi Koishi
  • Patent number: 10135450
    Abstract: A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit causes a current obtained by mirroring a reference current to flow to a first output terminal and a second output terminal. The first drive switch connects or disconnects the first output terminal and a charge pump output terminal. The switch circuit connects the capacitor either to a discharge path between the second output terminal and a node which provides a predetermined voltage or to a charge path between the charge pump output terminal and a GND.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 20, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic De4vices & Storage Corporation
    Inventors: Go Urakawa, Tsuneo Suzuki
  • Patent number: 10090994
    Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang
  • Patent number: 10075145
    Abstract: Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 11, 2018
    Assignee: The Regents of the University of California
    Inventor: Qun Gu
  • Patent number: 10070089
    Abstract: An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 4, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yusuke Tokunaga
  • Patent number: 10063244
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: August 28, 2018
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10063246
    Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 28, 2018
    Assignee: Perceptia Devices, Inc.
    Inventors: André Grouwstra, Julian Jenkins
  • Patent number: 10063247
    Abstract: A phase-locked loop (PLL) has at least two parallel loops. The loops share an oscillator, a counter connected with the oscillator, a multiplexer, and a loop filter. Each loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The loop forwards the integer difference between the sampled phase and the predicted phase to the multiplexer, which selects one of the loops and provides the difference to the loop filter. Loops that are not selected use a monitor-and-adjust function to keep the difference in track with the difference of a selected loop. Loops may provide a loop sleep function and the PLL may also provide an oscillator sleep function.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 28, 2018
    Assignee: Perceptia Devices, Inc.
    Inventors: Julian Jenkins, André Henri Grouwstra
  • Patent number: 10062423
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 28, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 10048731
    Abstract: Techniques for mitigating voltage offsets are described herein. A method for mitigating voltage offset includes receiving, via a sensor, charging current information. The method also includes adjusting, via a common mode adjustment circuitry, a common mode voltage based on charging current information and a physical layer circuit mode.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10020803
    Abstract: A drive unit includes a first transistor, a second transistor, a current source that is connected to a high-potential-side electrode of the first transistor, and delivers constant current, a current control circuit configured to perform control to start of charging of the gates of the first and second transistors using the current source, and a gate charge circuit that charges the gates of the first and second transistors, separately from the current source.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 10, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Yosuke Osanai
  • Patent number: 9985619
    Abstract: A duty cycle corrector (DCC) includes a duty corrector circuit configured to adjust a duty of an input signal to output a duty-adjusted signal; a duty detector circuit configured to generate a correction code associated with the adjustment of the duty, based on a charge pump operation and a counting operation; and a timing controller configured to generate a first control signal associated with the charge pump operation and a second control signal associated with the counting operation in synchronization with a first clock.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon Lee, Joung-wook Moon, Seong-hwan Jeon
  • Patent number: 9984613
    Abstract: A substrate includes first and second image processing circuits performing image processing of an image displayed by a display apparatus, a clock signal generator generating a plurality of spread spectrum clocks, which area plurality of clock signals subjected to spread spectrum processing, and a transmitter transmitting a first spread spectrum clock, which is one of the plurality of spread spectrum clocks, to the first image processing circuit and a second spread spectrum clock, which is one of the plurality of spread spectrum clocks to the second image processing circuit. The clock signal generator includes a signal generator that generates a clock signal subjected to the spread spectrum processing and a signal divider that divides the clock signal into the plurality of spread spectrum clocks. The first and second image processing circuits synchronize with each other in accordance with the first and second spread spectrum clocks.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 29, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuo Suzuki
  • Patent number: 9934830
    Abstract: In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongmin Park, Tae-Kyeong Ko, Do-Han Kim, Sungup Moon, Kyoyeon Won
  • Patent number: 9923566
    Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 20, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Gagan Midha
  • Patent number: 9923459
    Abstract: Charge-pump devices and corresponding methods are disclosed. A control input of a valve transistor of the charge pump device may be coupled with one of an input terminal or an output terminal via a further transistor.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Adolfo De Cicco, Bernard Blaise Tchodjie Tchamabe
  • Patent number: 9917511
    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: March 13, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter Vlasenko, Huy Tuong Mai
  • Patent number: 9893607
    Abstract: A low drop-out voltage regulator (LDO) includes an LDO unit, a switch circuit, a charge pump, and an initiation circuit. The switch circuit is coupled to a voltage input terminal and outputs a selected input voltage. The LDO unit receives the selected input voltage from the switch circuit and generates a regulated output voltage. The charge pump is coupled to the LDO unit to receive the regulated output voltage, and generate a control signal that is provided to the switch circuit. The initiation circuit receives the input voltage and generates an initiation voltage that greater than the regulated output voltage. The initiation voltage is provided to the charge pump circuit, along with the regulated output voltage. The initiation voltage drives the charge pump circuit when the regulated output voltage is not large enough to drive the charge pump circuit.
    Type: Grant
    Filed: July 9, 2017
    Date of Patent: February 13, 2018
    Assignee: NXP B.V.
    Inventors: Mingliang Wan, Xindong Duan, Jian Qing
  • Patent number: 9874893
    Abstract: A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 23, 2018
    Assignee: Analog Devices, Inc.
    Inventor: Alexandru A. Ciubotaru
  • Patent number: 9847785
    Abstract: In a PLL circuit, first an ILFD is connected to an output voltage Vtune from an LPF, thereby causing the ILFD to operate as an oscillator. The ILFD, a DIV, PFD, CP, and LPF form a PLL and thereby locking operations are initiated. When a predetermined time elapses, an output frequency from the ILFD converges into a certain value and the PLL is subjected to a locked state. After the locked state is reached, a sample hold circuit SH holds the output voltage Vtune from the loop filter as of that time and frequency adjustment of the ILFD is completed. Similar frequency adjustment is sequentially performed on other ILFDs.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 19, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takayuki Nakai
  • Patent number: 9829317
    Abstract: A drive circuit for a MEMS resonator can include closed loop means for detecting and amplifying a signal of the MEMS resonator, and means for feeding the detected and amplified signal as a feedback signal back to the MEMS resonator. The circuitry also comprises DC bias voltage means for generating for the MEMS resonator a first DC bias voltage, and a second DC bias voltage that is controlled according to measured amplitudes of the MEMS resonator, one of the DC bias voltages being summed into the feedback signal. The circuitry comprises also a start-up circuitry adapted to detect a start-up state, and in response to a detected start-up state change at last one of the DC bias voltages to a predefined level. The state of constant oscillation is achieved reliably and in short time.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: November 28, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Lasse Aaltonen
  • Patent number: 9831882
    Abstract: The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 28, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • Patent number: 9831766
    Abstract: A charge pump includes a current source circuit, a current sink circuit and a switch circuit. The switch circuit is coupled between the current source circuit and the current sink circuit, and is arranged for generating a first current at a first output terminal and generating a second current at a second output terminal according to a first control signal and a second control signal, wherein each of the first current and the second current is generated from the current source circuit.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 28, 2017
    Assignee: MEDIATEK INC.
    Inventor: Teng-Yi Wang
  • Patent number: 9806724
    Abstract: Various aspects of this disclosure describe switched-capacitor circuits in a PLL. Examples include routing current from a first current source through a capacitor to ground during a first clock phase, routing current from a second current source through the capacitor to ground during a second clock phase, and transferring charge on the capacitor to a loop filter capacitor during a third clock phase. The first current source may generate current responsive to UP error samples from a phase/frequency detector (PFD), and the second current source generates current responsive to DN error samples from the PFD.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mojtaba Sharifzadeh, Alireza Khalili, Mazhareddin Taghivand, Mohammad Emadi
  • Patent number: 9794089
    Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Tawfiq Musah, Gokce Keskin, Ganesh Balamurugan, James E. Jaussi, Bryan K. Casper
  • Patent number: 9787313
    Abstract: An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 10, 2017
    Assignee: XILINX, INC.
    Inventors: Matthew H. Klein, David F. Taylor
  • Patent number: 9774335
    Abstract: A phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 26, 2017
    Assignee: NXP USA, Inc.
    Inventors: Pierre Savary, Birama Goumballa, Didier Salle
  • Patent number: 9767248
    Abstract: A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS, CO., LTD.
    Inventors: Taejoong Song, Jung-Ho Do, Changho Han
  • Patent number: 9762120
    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: September 12, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter Vlasenko, Huy Tuong Mai
  • Patent number: 9742266
    Abstract: Cycle timing of a charge pump is adapted according to monitoring of operating characteristics of a charge pump and/or peripheral elements coupled to the charge pump. In some examples, this adaptation provides maximum or near maximum cycle times while avoiding violation of predefine constraints (e.g., operating limits) in the charge pump and/or peripheral elements.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 22, 2017
    Assignee: Arctic Sand Technologies, Inc.
    Inventors: David M. Giuliano, Gregory Szczeszynski, Jeffrey Summit, Raymond Barrett, Jr.
  • Patent number: 9735789
    Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John W. Stanton, Pradeep Thiagarajan