With Charge Pump Patents (Class 327/157)
  • Patent number: 10840319
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10826387
    Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Vladislav Dyachenko, Nenad Pavlovic
  • Patent number: 10804912
    Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Utku Seckin, Simone Gambini, Benjamin W. Cook
  • Patent number: 10784872
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10778235
    Abstract: Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: September 15, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Yuval Kirschner
  • Patent number: 10771065
    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 8, 2020
    Assignee: INPHI CORPORATION
    Inventors: Simon Forey, Parmanand Mishra, Michael S. Harwood, Rajasekhar Nagulapalli
  • Patent number: 10763871
    Abstract: Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Manoj Kumar Patasani, Tarik Saric, Juan Felipe Osorio Tamayo
  • Patent number: 10720929
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 21, 2020
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10700669
    Abstract: A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 30, 2020
    Assignee: Aura Semiconductor Pvt. Ltd
    Inventors: Nigesh Baladhandapani, Sharanaprasad Melkundi, Raja Prabhu J, Augusto Marques
  • Patent number: 10686429
    Abstract: A clock filter includes a ring oscillator comprising a plurality of inverters cascaded in a ring topology and configured to output a plurality of internal voltages including a first internal voltage and a second internal voltage. The clock filter further includes a coupling circuit configured to couple an input voltage to the first internal voltage, a sampling circuit configured to output a control voltage by sampling the second internal voltage in accordance with the input voltage, and a current source configured to output the bias current in accordance with the control voltage.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 16, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10686454
    Abstract: A clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pump unit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, the current-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 16, 2020
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventor: Ming-Ting Wu
  • Patent number: 10630461
    Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Valentin Abramzon
  • Patent number: 10623007
    Abstract: An apparatus includes an oscillator circuit that may generate a clock signal with a frequency that is based on a voltage level of a control node, and a charge pump circuit that includes a first current source and a second current source. The first current source may be coupled between a first supply node and a first circuit node. The second current source may be coupled between a second supply node and a second circuit node. The charge pump circuit may be configured to pre-charge the first and second circuit nodes to voltage levels that differ from the control node and the first and second supply nodes. In addition, the charge pump circuit may select, based on phase information, either the first or second circuit node, and then modify, based on a voltage level of the selected circuit node, a voltage level of the control node.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Apple Inc.
    Inventors: Robert K. Kong, Shaobo Liu, Dennis M. Fischette, Jr., Patrick J Landy
  • Patent number: 10601312
    Abstract: An RF circuit comprises a charge pump configured to generate current pulses having a first current amplitude and a predetermined duration; and a capacitive element configured to receive the current pulses and to generate a tuning voltage depending thereon. An RF oscillator is configured to generate an RF signal having a frequency that is dependent on the tuning voltage. The RF circuit comprises a measuring circuit configured to generate a measurement signal representing the tuning voltage or the frequency of the RF signal. A controller circuit is configured to drive the charge pump in order to change the first amplitude of a current pulse by a current difference, and ascertain a first change in the measurement signal and a second change in the measurement signal. A measurement value for the first amplitude can be calculated based on the first change and the second change based on the current difference.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventor: Lukas Heschl
  • Patent number: 10573700
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 25, 2020
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10559678
    Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, ALi Salih
  • Patent number: 10560080
    Abstract: A duty cycle correction circuit is disclosed. The duty cycle correction circuit includes an input stage, an output stage and a feedback component including a feedback amplifier and a low pass filter. The feedback component compares and adjusts the duty cycle of a signal from an input stage to a target value via a control voltage. The input stage reduces the rise and fall times of received signal to increase the duty cycle sensitivity to a control voltage from the feedback component. The output of the output stage is coupled to the input of the feedback component and the output stage amplifiers the duty cycle adjusted signal processed by both input stage and feedback component.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 11, 2020
    Assignee: NXP B.V.
    Inventors: Xu Zhang, Siamak Delshadpour, Ahmad Yazdi
  • Patent number: 10535723
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 14, 2020
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10521638
    Abstract: The present invention provides a fingerprint identification system includes a charge pump circuit configured to generate a supply voltage, wherein the charge pump circuit receives a first clock signal; a pixel circuit, forming a touch capacitance, determining whether the pixel circuit is corresponding to a finger valley or a finger ridge according to the touch capacitance, wherein the pixel circuit receives a second clock signal and the supply voltage; and a clock generating circuit, configured to generate the first clock signal and the second clock signal; wherein the first clock signal is related to the second clock signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 31, 2019
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Hsmlun Li, MengTa Yang
  • Patent number: 10510387
    Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian Gradinariu, Gary Peter Moscaluk, Roger Jay Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 10498527
    Abstract: A communication system according to the present disclosure includes a transmission device and a reception device. The transmission device includes a phase synchronizer, a generator, and a controller. The phase synchronizer generates a first clock signal, and is configured to be able to change a frequency of the first clock signal. The generator generates a transmission signal on the basis of the first clock signal. The controller controls the generator and the phase synchronizer to change the frequency of the first clock signal while generating the transmission signal. The reception device receives the transmission signal.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 3, 2019
    Assignee: SONY CORPORATION
    Inventors: Ryota Shinoda, Takashi Masuda
  • Patent number: 10498231
    Abstract: Charge pump circuitry comprises a differential amplifier and parallel-connected reference, auxiliary and output current paths comprising first current-mirror transistors connected so an auxiliary current and a first output current along a first part of the output current path are dependent on the reference current. The auxiliary and output current paths comprise second-current-mirror transistors connected so a second output current flowing along a second part of the output current path is dependent on the auxiliary current. The auxiliary current path comprises a control transistor connected in series with the first-current-mirror transistor of that path. The differential amplifier receives first and second input signals from nodes in the auxiliary and output current paths, respectively, and controls the control transistor with its amplifier output signal to control the drain or collector voltage of the first-current mirror transistor in the auxiliary path.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 3, 2019
    Assignee: SOCIONEXT, INC.
    Inventor: David Hany Gaied Mikhael
  • Patent number: 10483845
    Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 19, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yu-Li Hsueh, Chih-Hsien Shen, Chao-Ching Hung, Po-Chun Huang
  • Patent number: 10473530
    Abstract: A temperature sensor configured to generate a temperature-indicating signal with improved accuracy over a wide temperature range is disclosed. The temperature sensor includes a first oscillator configured to generate a first oscillating signal with a first frequency that varies with a sensed temperature and a reference parameter; a second oscillator configured to generate a second oscillating signal with a second frequency that varies with the reference parameter; and a time-to-digital converter (TDC) configured to generate a digital output indicative of the sensed temperature based on a ratio of the first frequency to the second frequency. Because the first and second frequencies depend on the reference parameter, and the temperature-indicating signal is a function of the ratio of the first and second frequencies, temperature-variation in the reference parameter cancels out in the temperature-indicating signal.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 12, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Philex Ming-Yan Fan, Richard Nguyen, Manjunatha Poojary
  • Patent number: 10476511
    Abstract: A PLL circuit includes a phase comparator, first and second charge pumps, a filter generating a first control voltage from a current of the first charge pump, a comparator comparing a voltage of a first node with a reference voltage, a switch section outputting the reference voltage to the first node and outputting a current of the second charge pump to a second node in a high-speed lock mode, and outputting the current of the second charge pump to the first node and outputting a result from the comparator to the second node in a normal lock mode, a second filter generating a second control voltage by integrating a current of the first node, a third filter generating a third control voltage by integrating a current of the second node, and a voltage controlled oscillator generating a clock signal of a frequency corresponding to the first to third control voltages.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuyuki Hiraku
  • Patent number: 10461755
    Abstract: We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 29, 2019
    Assignee: Oracle International Corporation
    Inventors: Guanghua Shu, Frankie Y. Liu, Suwen Yang, Ziad Saleh Shehadeh, Eric Y. Chang
  • Patent number: 10439569
    Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: October 8, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alberto Cattani, Germano Nicollini, Alessandro Gasparini
  • Patent number: 10439624
    Abstract: A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: October 8, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober, Herbert M Shapiro
  • Patent number: 10411593
    Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Valentin Abramzon, Amir Amirkhany, Anup P. Jose
  • Patent number: 10401409
    Abstract: According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Cesare Buffa, Luis Hernandez-Corporales, Andreas Wiesbauer, Enrique Prefasi
  • Patent number: 10396657
    Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10395035
    Abstract: Some embodiments include apparatuses having diffusion regions located adjacent each other in a substrate, and connections coupled to the diffusion regions. The diffusion regions include first diffusion regions, second diffusion regions, and third diffusion regions. One of the second diffusion regions and one of the third diffusion regions are between two of the first diffusion regions. One of the first diffusion regions and one of the third diffusion regions are between two of the second diffusion regions. The connections include a first connection coupled to each of the first diffusion regions, a second connection coupled to each of the second diffusion regions, and a third connection coupled to each of the third diffusion regions.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Sudhir K Satpathy, Vikram B Suresh, Patrick Koeberl
  • Patent number: 10389371
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 20, 2019
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10374617
    Abstract: A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Ting-Kuei Kuan, Chin-Yang Wu, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10360840
    Abstract: To achieve a pixel circuit and the like capable of improving the accuracy for detecting the threshold voltage. The pixel circuit includes: a light emitting element; a driving transistor which supplies an electric current to the light emitting element according to an applied voltage; a capacitor part which holds a voltage containing a threshold voltage and a data voltage of the driving transistor and applies the voltage to the driving transistor; and a switch part which makes the capacitor part hold the voltage containing the threshold voltage and the data voltage. The switch part includes a reference voltage transistor which inputs a reference voltage from a reference voltage power supply line and a data voltage transistor which inputs a data voltage from a data line.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 23, 2019
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Yojiro Matsueda, Yoshihiro Nonaka, Kenichi Takatori
  • Patent number: 10348414
    Abstract: A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 9, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ajay Yadav, Samir Aboulhouda, Faouzi Chaahoub
  • Patent number: 10348314
    Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 9, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Gagan Midha
  • Patent number: 10333530
    Abstract: According to one embodiment, a voltage-controlled oscillator includes a voltage-current conversion circuit and hold circuit that outputs a first current corresponding to a control voltage, a current addition circuit that outputs a second current corresponding to the first current, and a current subtraction circuit that outputs a third current corresponding to the first current. The voltage-controlled oscillator also includes a narrow-band low-pass filter that passes a current in a first frequency band to reduce noise of the second current, a voltage-current converter that outputs a sixth current corresponding to a fifth current obtained by subtracting the third current from a fourth current corresponding to the control voltage, and a low-pass filter that passes a current in a second frequency band to reduce noise of the sixth current. The second frequency band is different from the first frequency band.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Makihiko Katsuragi
  • Patent number: 10297653
    Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 21, 2019
    Assignee: Sony Corporation
    Inventor: Hitoshi Tsuno
  • Patent number: 10277117
    Abstract: A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10270341
    Abstract: A regulator circuit includes a first transistor reducing an external supply voltage and outputting an internal active voltage to an output node; a first detector receiving a criteria level, detecting the internal active voltage based on an enable signal, controlling a gate voltage of the first transistor, and adjusting an output current thereof; a second transistor reducing the external supply voltage, and outputting an internal standby voltage corresponding to the internal active voltage to the output node; a second detector receiving a reference voltage, detecting the internal standby voltage regardless of the enable signal, controlling a gate voltage of the second transistor, and adjusting an output current thereof; a first switch controlling whether to output the reference voltage as the criteria level of the first detector; and a second switch controlling whether to output the voltage of the output node as the criteria level of the first detector.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 23, 2019
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Atsushi Nakakubo
  • Patent number: 10211843
    Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 19, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • Patent number: 10199933
    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 5, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter Vlasenko, Huy Tuong Mai
  • Patent number: 10199986
    Abstract: Systems and methods are provided in which a voltage-controlled oscillator for a radio transmitter includes a LC tank circuit, and a muting circuit. The LC tank circuit includes an inductive element and a capacitive element; wherein the inductive element of the LC tank circuit includes the antenna of the transmitter. The muting circuit can include a variable resistor connected in parallel with the LC tank circuit.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 5, 2019
    Assignee: Olympus Corporation
    Inventors: John B. Groe, Anton Karnitski, Kishore Rama Rao
  • Patent number: 10171032
    Abstract: Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on a reference voltage. The pulse generator circuit may include a capacitor coupled between a first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the node in response to the periodic pulse, a resistor and a diode coupled in series between a second node and a second reference voltage, and a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and the a current.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jun Wu, Dong Pan
  • Patent number: 10164618
    Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
  • Patent number: 10153927
    Abstract: A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signal 302 to both a phase detector 308 and an edge detector 314, and using the respective output signals 310, 318, 320 of the phase detector 308 and edge detector 314 to determine an end of a modulation symbol 340 in the signal 302.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 11, 2018
    Assignee: Nordic Semiconductor ASA
    Inventors: Ruben Undheim, Ola Bruset
  • Patent number: 10144373
    Abstract: A power supply system control device for controlling a power supply system including an electric generator, a first electricity storage configured to be charged with and to discharge electric power generated by the electric generator, a second electricity storage configured to be charged with and to discharge the generated electric power, two paths connecting between the first electricity storage and the second electricity storage, a switching unit including a first switch configured to switch between a conductive state and a non-conductive state of one of the paths, and a second switch configured to switch between a conductive state and a non-conductive state of the other of the paths, and an electric load of a vehicle that is connected to the first electricity storage side of the switching unit.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: December 4, 2018
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Masahiko Tahara, Terumasa Tsuchiya, Atsushi Tezuka, Tomoyuki Koike, Munemitsu Watanabe, Akifumi Koishi
  • Patent number: 10135450
    Abstract: A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit causes a current obtained by mirroring a reference current to flow to a first output terminal and a second output terminal. The first drive switch connects or disconnects the first output terminal and a charge pump output terminal. The switch circuit connects the capacitor either to a discharge path between the second output terminal and a node which provides a predetermined voltage or to a charge path between the charge pump output terminal and a GND.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 20, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic De4vices & Storage Corporation
    Inventors: Go Urakawa, Tsuneo Suzuki
  • Patent number: 10090994
    Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang