With Digital Element Patents (Class 327/159)
  • Patent number: 10972080
    Abstract: Clock generation and control in a semiconductor system having process, voltage and temperature (PVT) variation. A semiconductor device may include at least first and second ring oscillators, each disposed at locations respectively closest to first and second logic circuits of an operation circuit, and generating first and second oscillating signals. A detecting circuit is configured to perform a predetermined logic operation on the first oscillating signal and the second oscillating signal to generate a first clock signal. A calibration circuit is configured to receive the first clock signal from the detecting circuit and perform a delay control on each of the first ring oscillator and the second ring oscillator to generate a second clock signal for operating the operation circuit.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Hwan Kim, Wook Kim, Ji Youn Kim
  • Patent number: 10958491
    Abstract: The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 23, 2021
    Assignee: Auburn University
    Inventors: Fa Dai, Hechen Wang
  • Patent number: 10958162
    Abstract: A dual loop regulated switched-capacitor converter circuit includes a switched capacitor array that includes a plurality of switches and capacitors; a digital controller for controlling the switched capacitor array; a pulse modulator connected to the digital controller; a clock generator connected to the digital controller; a first comparator connected to the pulse modulator; and a feedback network connected to the first comparator.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 23, 2021
    Assignee: Vidatronic, Inc.
    Inventors: Sameh Assem Ibrahim, Mohammad Ahmed Radwan, Michael A Nix
  • Patent number: 10944412
    Abstract: Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Perceptia IP Pty Ltd
    Inventor: Julian Jenkins
  • Patent number: 10848137
    Abstract: A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: November 24, 2020
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Mikhail Rodionov, Stephen Victor Kosonocky, Joyce Cheuk Wai Wong
  • Patent number: 10727846
    Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
  • Patent number: 10693480
    Abstract: A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 23, 2020
    Inventor: Julian Jenkins
  • Patent number: 10685617
    Abstract: A display device having a charging compensation circuit to reduce/eliminate display stains based on pixels being charged at unequal charging rates. A data driving circuit of a display device includes an output circuit for converting an image signal into a data signal in response to a clock signal, and providing the data signal to a plurality of data lines, and a clock generating and compensating circuit for receiving a main clock signal and generating the clock signal, wherein the clock generating and compensating circuit detects a slew rate of the data signal provided to at least one of the plurality of data lines, and adjusts a phase of the clock signal depending on the detected slew rate.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Taegon Im, Boyeon Kim, Dongwon Park, Junghwan Cho
  • Patent number: 10651862
    Abstract: A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 12, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: James D. Barnette, Krishnan Balakrishnan
  • Patent number: 10637637
    Abstract: A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Hadi Goudarzi, Jon Boyette, Eskinder Hailu, Julian Puscar
  • Patent number: 10630299
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 21, 2020
    Assignee: Apple Inc.
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • Patent number: 10605861
    Abstract: The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 31, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Po-Lin Chen, Chun-Yi Kuo, Ying-Yen Chen
  • Patent number: 10594300
    Abstract: A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 17, 2020
    Assignee: Microsemi Semiconductor ULC
    Inventor: Qu Gary Jin
  • Patent number: 10567154
    Abstract: A Bluetooth Low-Energy (BLE) transmitter is presented for used in ultra-low-power radios in short range IoT applications. The power consumption of state-of-the-art BLE transmitter has been limited by the relatively power-hungry local oscillator due to the use of LC oscillators for superior phase noise performance. This disclosure addresses this issue by analyzing the phase noise limit of a BLE TX and proposes a ring oscillator-based solution for power and cost savings. The proposed transmitter features: 1) a wideband all-digital phase locked loop (ADPLL) featuring an fRF/4 RO, with an embedded 5-bit TDC; 2) a 4× frequency edge combiner to generate the 2.4 GHz signal; and 3) a switch-capacitor digital PA optimized for high efficiency at low transmit power levels. These not only help reduce the power consumption and improve phase noise performance, but also enhance the transmitter efficiency for short range applications.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 18, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: David D. Wentzloff, Xing Chen
  • Patent number: 10560109
    Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: February 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Simon Jacques Damphousse
  • Patent number: 10498562
    Abstract: Provided is an electric signal transmission device which corrects a data error caused by data transition in a pulse amplitude modulation signal to increase an EYE width. The electric signal transmission device can operate as follows: A data pattern determined by an equalizer and a phase relationship between data and a clock detected by a phase detector are used to calculate a correction amount according to the data pattern and the phase relationship, and the received data is corrected to a correct value by adding a correction amount in a data transition direction.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 3, 2019
    Assignee: Hitachi, Ltd.
    Inventor: Takayasu Norimatsu
  • Patent number: 10498344
    Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
  • Patent number: 10439561
    Abstract: An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Adam Lee Shook
  • Patent number: 10389366
    Abstract: A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Eskinder Hailu, Bupesh Pandita, Jon Boyette
  • Patent number: 10374614
    Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal, a memory element to store the values of the output information, a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information, and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Sarath Makala, Kowshik Gandham, Chun Lee
  • Patent number: 10340923
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • Patent number: 10298244
    Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Farshid Aryanfar
  • Patent number: 10218364
    Abstract: A time to digital converter has a counter to measure the number of cycles of a first signal, a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference, a first capacitor to be charged with an electric charge, a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1, a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor, a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more, and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 26, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihide Sai, Masanori Furuta, Tetsuro Itakura, Satoshi Kondo, Hidenori Okuni, Tuan Thanh Ta
  • Patent number: 10181856
    Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Elan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
  • Patent number: 10169140
    Abstract: A mechanism is provided for loading a phase-locked loop (PLL) configuration into a PLL module using Flash memory. A Flash data image configuration from the Flash memory is loaded into a set of holding registers in response to the PLL module locking a current PLL configuration from a set of current configuration registers. The Flash data image configuration in the set of holding registers is compared to the current PLL configuration in the set of current configuration registers in response to the Flash data image configuration failing to be corrupted. The Flash data image configuration onto a PLL module input in response to the Flash data image configuration differing from the current PLL configuration. The Flash data image configuration is loaded in the set of holding registers into the set of current configuration registers in response to the PLL module locking the Flash data image configuration.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gerald M. Grabowski, Daniel F. Moertl, Michael J. Palmer, Kelvin Wong
  • Patent number: 10128881
    Abstract: A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Kondo, Akihide Sai, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
  • Patent number: 10067224
    Abstract: A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, and provide a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: John Kevin Moore, Neale Dutton
  • Patent number: 10048719
    Abstract: The configuration of an apparatus for automatically calibrating a clock of a non-crystal oscillator and method thereof are disclosed. The proposed method for automatically calibrating the clock of the non-crystal oscillator includes sending a NACK signal to a host and fine-tuning the clock of the non-crystal oscillator via a frequency calibration system for non-crystal oscillator when a USB device receives an in-token command from the host, and outputting a datum from the USB device to the host.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 14, 2018
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventor: Fu-Yuan Hsiao
  • Patent number: 9954540
    Abstract: A system that generates a click signal includes a first digitally controlled oscillator (DCO) having a first fundamental frequency, and a second DCO having a second fundamental frequency. The system also includes a Muller C-element, which combines outputs of the first and second DCOs to produce the clock signal, which feeds back into the first and second DCOs. During a calibration operation, while the second DCO is set to a frequency larger than the target frequency, the system adjusts the first DCO with reference to a first feedback loop, which includes the first DCO, so that the clock signal matches the target frequency, and while the first DCO is set to the adjusted first fundamental frequency plus a frequency offset, the system adjusts the second DCO with reference to a second feedback loop, which includes the second DCO, so that the clock signal matches the target frequency.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 24, 2018
    Assignee: Oracle International Corporation
    Inventors: Yifan YangGong, Sebastian Turullols, Changku Hwang, Nicolas M. Huynh, Daniel S. Woo
  • Patent number: 9954538
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Invecas, Inc.
    Inventors: Narasimhan Vasudevan, Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9939839
    Abstract: A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 10, 2018
    Assignee: Ambiq Micro, Inc.
    Inventor: Stephen James Sheafor
  • Patent number: 9853807
    Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang
  • Patent number: 9805304
    Abstract: A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 31, 2017
    Assignee: Google Inc.
    Inventor: Jonathan Ross
  • Patent number: 9735948
    Abstract: System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 15, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 9735952
    Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel IP Corporation
    Inventors: Ashoke Ravi, Ofir Degani, Rotem Banin, Assaf Ben-Bassat
  • Patent number: 9692397
    Abstract: A structure is provided for sensing an analyte in an environment. The structure may include a ring oscillator on a semiconductor substrate, the ring oscillator includes an AND gate, an odd number of inverters, and a carbon device connected in series, the carbon device is exposed to an environment such that a frequency of the ring oscillator changes when the carbon device is exposed to the analyte in the environment.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Keith A. Jenkins
  • Patent number: 9590646
    Abstract: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 7, 2017
    Assignee: NXP B.V.
    Inventors: Yuan Gao, Frank Leong, Robert Bogdan Staszewski
  • Patent number: 9564912
    Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 7, 2017
    Assignee: RAMBUS INC.
    Inventors: Marko Aleksić, Brian S. Leibowitz
  • Patent number: 9553570
    Abstract: An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 24, 2017
    Assignee: Integrated Device Technology, Inc.
    Inventor: Jagdeep Bal
  • Patent number: 9490727
    Abstract: The invention relates to a method for calibrating a multiphase, in particular three-phase, inverter (1) having a respective switching element (T1, T2, T3) on the high-voltage side and a respective switching element (T4, T5, T6) on the low-voltage side for each of the phases thereof as well as a respective current sensor for at least some of the phases (I, II, III). The following steps are proposed: (f) switching off all switching elements (T1-T6), (g) switching on a switching element (T1) on the high-voltage side for a first phase (I) and a switching element (T5) on the low-voltage side for a second phase (II), (h) measuring the currents flowing through the first phase (I) and the second phase (II), (i) forming an average value from the measured currents, and (j) calibrating the inverter (1) on the basis of the formed average value. The invention also relates to an apparatus, a computer program and a computer program product.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 8, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Daniel Raichle, Mark Damson
  • Patent number: 9479206
    Abstract: A modulated signal is demodulated to obtain a modulation signal. The modulated signal is contained within an input signal. A periodic time segment sequence is defined having a plurality of ordered time segments. Signal values are acquired, from the input signal, during each ordered time segment. Signal values acquired during each ordered time segment are combined with signal values acquired during the same ordered time segment over multiple periods of the periodic time segment sequence. A local clock is generating. The modulated signal is demodulated by weighting the combined signal values by the local clock to obtain the modulation signal. the modulation signal is low-pass filtered to obtain a control signal. The generation of the local clock is controlled with the control signal.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: October 25, 2016
    Assignee: Innoventure L.P.
    Inventor: David K Nienaber
  • Patent number: 9472255
    Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 18, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 9461657
    Abstract: Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 4, 2016
    Assignee: Qualcomm Incorporated
    Inventor: Ian Galton
  • Patent number: 9438204
    Abstract: Embodiments of the invention disclose a signal processing device and a signal processing method and a device and a method for signal processing. The signal processing device includes a sampling module, a first segmentation module, a second segmentation module, and a detection module. The sampling module samples an input signal to generate a sample signal. The first segmentation module calculates a first segment value according to the sample signal during a first time interval. The second segmentation module calculates a second segment value according to the sample signal during a second time interval different in length from the first time interval. The detection module generates a detection signal according to the determination of whether the first segment value lies out of a first range, and whether the second segment value lies out of a second range.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 6, 2016
    Assignee: MEDIATEK INC.
    Inventor: Chien-Hua Hsu
  • Patent number: 9432031
    Abstract: A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 30, 2016
    Assignee: NINGBO UNIVERSITY
    Inventors: Yuejun Zhang, Pengjun Wang, Zhidi Jiang, Xuelong Zhang
  • Patent number: 9362928
    Abstract: A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a fractional N-frequency synthesizer.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 7, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pankaj Goyal, Jagdeep Bal
  • Patent number: 9337850
    Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 10, 2016
    Assignee: NXP, B.V.
    Inventor: Ulrich Moehlmann
  • Patent number: 9312864
    Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 12, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Yifan YangGong, Sebastian Turullols, Changku Hwang, Daniel S. Woo
  • Patent number: 9300305
    Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: March 29, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chun-Ming Kuo, Chii-Horng Chen, Shih-Chi Shen
  • Patent number: 9287885
    Abstract: An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chia-Chun Liao