With Digital Element Patents (Class 327/159)
  • Patent number: 10374614
    Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal, a memory element to store the values of the output information, a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information, and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Sarath Makala, Kowshik Gandham, Chun Lee
  • Patent number: 10340923
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • Patent number: 10298244
    Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Farshid Aryanfar
  • Patent number: 10218364
    Abstract: A time to digital converter has a counter to measure the number of cycles of a first signal, a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference, a first capacitor to be charged with an electric charge, a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1, a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor, a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more, and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 26, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihide Sai, Masanori Furuta, Tetsuro Itakura, Satoshi Kondo, Hidenori Okuni, Tuan Thanh Ta
  • Patent number: 10181856
    Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Elan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
  • Patent number: 10169140
    Abstract: A mechanism is provided for loading a phase-locked loop (PLL) configuration into a PLL module using Flash memory. A Flash data image configuration from the Flash memory is loaded into a set of holding registers in response to the PLL module locking a current PLL configuration from a set of current configuration registers. The Flash data image configuration in the set of holding registers is compared to the current PLL configuration in the set of current configuration registers in response to the Flash data image configuration failing to be corrupted. The Flash data image configuration onto a PLL module input in response to the Flash data image configuration differing from the current PLL configuration. The Flash data image configuration is loaded in the set of holding registers into the set of current configuration registers in response to the PLL module locking the Flash data image configuration.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gerald M. Grabowski, Daniel F. Moertl, Michael J. Palmer, Kelvin Wong
  • Patent number: 10128881
    Abstract: A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Kondo, Akihide Sai, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
  • Patent number: 10067224
    Abstract: A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, and provide a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: John Kevin Moore, Neale Dutton
  • Patent number: 10048719
    Abstract: The configuration of an apparatus for automatically calibrating a clock of a non-crystal oscillator and method thereof are disclosed. The proposed method for automatically calibrating the clock of the non-crystal oscillator includes sending a NACK signal to a host and fine-tuning the clock of the non-crystal oscillator via a frequency calibration system for non-crystal oscillator when a USB device receives an in-token command from the host, and outputting a datum from the USB device to the host.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 14, 2018
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventor: Fu-Yuan Hsiao
  • Patent number: 9954538
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Invecas, Inc.
    Inventors: Narasimhan Vasudevan, Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9954540
    Abstract: A system that generates a click signal includes a first digitally controlled oscillator (DCO) having a first fundamental frequency, and a second DCO having a second fundamental frequency. The system also includes a Muller C-element, which combines outputs of the first and second DCOs to produce the clock signal, which feeds back into the first and second DCOs. During a calibration operation, while the second DCO is set to a frequency larger than the target frequency, the system adjusts the first DCO with reference to a first feedback loop, which includes the first DCO, so that the clock signal matches the target frequency, and while the first DCO is set to the adjusted first fundamental frequency plus a frequency offset, the system adjusts the second DCO with reference to a second feedback loop, which includes the second DCO, so that the clock signal matches the target frequency.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 24, 2018
    Assignee: Oracle International Corporation
    Inventors: Yifan YangGong, Sebastian Turullols, Changku Hwang, Nicolas M. Huynh, Daniel S. Woo
  • Patent number: 9939839
    Abstract: A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 10, 2018
    Assignee: Ambiq Micro, Inc.
    Inventor: Stephen James Sheafor
  • Patent number: 9853807
    Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang
  • Patent number: 9805304
    Abstract: A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 31, 2017
    Assignee: Google Inc.
    Inventor: Jonathan Ross
  • Patent number: 9735952
    Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel IP Corporation
    Inventors: Ashoke Ravi, Ofir Degani, Rotem Banin, Assaf Ben-Bassat
  • Patent number: 9735948
    Abstract: System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 15, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 9692397
    Abstract: A structure is provided for sensing an analyte in an environment. The structure may include a ring oscillator on a semiconductor substrate, the ring oscillator includes an AND gate, an odd number of inverters, and a carbon device connected in series, the carbon device is exposed to an environment such that a frequency of the ring oscillator changes when the carbon device is exposed to the analyte in the environment.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Keith A. Jenkins
  • Patent number: 9590646
    Abstract: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 7, 2017
    Assignee: NXP B.V.
    Inventors: Yuan Gao, Frank Leong, Robert Bogdan Staszewski
  • Patent number: 9564912
    Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 7, 2017
    Assignee: RAMBUS INC.
    Inventors: Marko Aleksić, Brian S. Leibowitz
  • Patent number: 9553570
    Abstract: An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 24, 2017
    Assignee: Integrated Device Technology, Inc.
    Inventor: Jagdeep Bal
  • Patent number: 9490727
    Abstract: The invention relates to a method for calibrating a multiphase, in particular three-phase, inverter (1) having a respective switching element (T1, T2, T3) on the high-voltage side and a respective switching element (T4, T5, T6) on the low-voltage side for each of the phases thereof as well as a respective current sensor for at least some of the phases (I, II, III). The following steps are proposed: (f) switching off all switching elements (T1-T6), (g) switching on a switching element (T1) on the high-voltage side for a first phase (I) and a switching element (T5) on the low-voltage side for a second phase (II), (h) measuring the currents flowing through the first phase (I) and the second phase (II), (i) forming an average value from the measured currents, and (j) calibrating the inverter (1) on the basis of the formed average value. The invention also relates to an apparatus, a computer program and a computer program product.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 8, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Daniel Raichle, Mark Damson
  • Patent number: 9479206
    Abstract: A modulated signal is demodulated to obtain a modulation signal. The modulated signal is contained within an input signal. A periodic time segment sequence is defined having a plurality of ordered time segments. Signal values are acquired, from the input signal, during each ordered time segment. Signal values acquired during each ordered time segment are combined with signal values acquired during the same ordered time segment over multiple periods of the periodic time segment sequence. A local clock is generating. The modulated signal is demodulated by weighting the combined signal values by the local clock to obtain the modulation signal. the modulation signal is low-pass filtered to obtain a control signal. The generation of the local clock is controlled with the control signal.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: October 25, 2016
    Assignee: Innoventure L.P.
    Inventor: David K Nienaber
  • Patent number: 9472255
    Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 18, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 9461657
    Abstract: Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 4, 2016
    Assignee: Qualcomm Incorporated
    Inventor: Ian Galton
  • Patent number: 9438204
    Abstract: Embodiments of the invention disclose a signal processing device and a signal processing method and a device and a method for signal processing. The signal processing device includes a sampling module, a first segmentation module, a second segmentation module, and a detection module. The sampling module samples an input signal to generate a sample signal. The first segmentation module calculates a first segment value according to the sample signal during a first time interval. The second segmentation module calculates a second segment value according to the sample signal during a second time interval different in length from the first time interval. The detection module generates a detection signal according to the determination of whether the first segment value lies out of a first range, and whether the second segment value lies out of a second range.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 6, 2016
    Assignee: MEDIATEK INC.
    Inventor: Chien-Hua Hsu
  • Patent number: 9432031
    Abstract: A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 30, 2016
    Assignee: NINGBO UNIVERSITY
    Inventors: Yuejun Zhang, Pengjun Wang, Zhidi Jiang, Xuelong Zhang
  • Patent number: 9362928
    Abstract: A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a fractional N-frequency synthesizer.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 7, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pankaj Goyal, Jagdeep Bal
  • Patent number: 9337850
    Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 10, 2016
    Assignee: NXP, B.V.
    Inventor: Ulrich Moehlmann
  • Patent number: 9312864
    Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 12, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Yifan YangGong, Sebastian Turullols, Changku Hwang, Daniel S. Woo
  • Patent number: 9300305
    Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: March 29, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chun-Ming Kuo, Chii-Horng Chen, Shih-Chi Shen
  • Patent number: 9287885
    Abstract: An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chia-Chun Liao
  • Patent number: 9197402
    Abstract: A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 24, 2015
    Assignee: INTEL CORPORATION
    Inventors: Hyung Seok Kim, Ashoke Ravi, William Y. Li, Kailash Chandrashekar
  • Patent number: 9148153
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 29, 2015
    Assignee: Intel Corporation
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • Patent number: 9113520
    Abstract: A light emitting diode (LED) backlight system and a driving apparatus and a driving method thereof are provided. The driving apparatus is suitable for an LED backlight system with N LED strings, where N is a positive integer greater than 1, and which includes an LED driver and a switching unit. The LED driver is configured to receive a dimming signal and time-divisionally generate N control signals in response to a counting clock and an enabling time and a period time both related to the dimming signal. The switching unit is coupled to the LED driver and the N LED strings, and is configured to respectively control an on-off time ratio of a current flowing through each of the LED strings in response to the N control signals.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Power Forest Technology Corporation
    Inventor: Hsiu-Ping Lin
  • Patent number: 9093996
    Abstract: A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 28, 2015
    Assignee: FURUNO ELECTRIC COMPANY LIMITED
    Inventors: Katsuhisa Yamashina, Kazunori Miyahara
  • Patent number: 9065242
    Abstract: An apparatus and method is provided to enable precision and fast laser frequency tuning. For instance, a fast tunable slave laser may be dynamically offset-locked to a reference laser line using an optical phase-locked loop. The slave laser is heterodyned against a reference laser line to generate a beatnote that is subsequently frequency divided. The phase difference between the divided beatnote and a reference signal may be detected to generate an error signal proportional to the phase difference. The error signal is converted into appropriate feedback signals to phase lock the divided beatnote to the reference signal. The slave laser frequency target may be rapidly changed based on a combination of a dynamically changing frequency of the reference signal, the frequency dividing factor, and an effective polarity of the error signal. Feed-forward signals may be generated to accelerate the slave laser frequency switching through laser tuning ports.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 23, 2015
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics Space Administration
    Inventors: Jeffrey R. Chen, Kenji Numata, Stewart T. Wu, Guangning Yang
  • Patent number: 9065653
    Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: June 23, 2015
    Assignees: Korea Advanced Institute of Science & Technology, Terasquare Co., Ltd.
    Inventors: HyunMin Bae, Joon Yeong Lee, Jin Ho Park, Tae Ho Kim
  • Publication number: 20150145571
    Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.
    Type: Application
    Filed: July 31, 2014
    Publication date: May 28, 2015
    Inventor: Michael H. Perrott
  • Publication number: 20150145566
    Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventor: Michael H. Perrott
  • Publication number: 20150145572
    Abstract: A time-to-digital converter (TDC) that has high resolution, excellent linearity, and a widerange. The TDC includes a first oscillator unit that generates and outputs a pair of first oscillation signals based on a pair of predetermined clock signals that have a predetermined phase difference, a second oscillator unit that generates and outputs a second oscillation signal that have a predetermined frequency based on the pair of first oscillation signals outputted from the first oscillator unit, and a quantizer that calculates a quantized value based on a number of edges of the second oscillation signal outputted from the second oscillator unit.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventor: Hideyuki Sato
  • Publication number: 20150145570
    Abstract: A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.
    Type: Application
    Filed: July 31, 2014
    Publication date: May 28, 2015
    Inventor: Michael H. Perrott
  • Publication number: 20150138016
    Abstract: A method of generating a correlation function for a CBOC(6,1,1/11) signal according to the present invention includes generating a delayed signal delayed based on a phase delay, with respect to a signal pulse train of a CBOC(6,1,1/11)-modulated received signal, generating first to twelfth partial correlation functions by performing an autocorrelation operation of the received signal and the delayed signal with respect to a total time, generating a basic intermediate correlation function by performing an elimination operation on sixth and seventh partial correlation functions, acquiring first to fifth and eighth to twelfth additional intermediate correlation functions by performing an elimination operation on each of partial correlation functions, excluding the sixth and seventh partial correlation functions from the first to twelfth partial correlation functions, and a basic intermediate correlation function, and acquiring the main correlation function by simply summing the basic intermediate correlation func
    Type: Application
    Filed: November 6, 2014
    Publication date: May 21, 2015
    Applicant: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Seok Ho YOON, Keun Hong CHAE
  • Patent number: 9035683
    Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 19, 2015
    Assignee: SILICON WORKS CO., LTD.
    Inventors: Hong Jun Yang, Yong Hwan Moon, Sang Ho Kim
  • Publication number: 20150130518
    Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: Yen-Jen CHEN, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU
  • Patent number: 9024668
    Abstract: A clock generation circuit of a semiconductor apparatus includes a first clock generation unit configured to output a first signal which swings between a level of a power supply voltage and a level of a set voltage; a second clock generation unit configured to output a second signal which swings between the level of the set voltage and a level of a ground voltage; and a regulator configured to supply the set voltage to the first clock generation unit and the second clock generation unit.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung Geun Baek, Hyun Woo Lee
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Publication number: 20150116018
    Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.
    Type: Application
    Filed: June 30, 2014
    Publication date: April 30, 2015
    Inventors: Huan-Neng CHEN, Kuang-Kai YEN, Feng-Wei KUO, Hsien-Yuan LIAO, Tsung-Hsiung LEE, Chewn-Pu JOU, Robert Bogdan STASZEWSKI
  • Patent number: 9020089
    Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventor: Nicola Da Dalt
  • Patent number: 9019017
    Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 28, 2015
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Win Chaivipas, Masazumi Marutani, Daisuke Yamazaki
  • Patent number: 9019016
    Abstract: There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 28, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Eizo Ichihara