Abstract: A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.

Abstract: In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop circuit is configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal. A path selection circuit is configured to select, in response to a select signal, one of a first signal path through the first delay locked loop circuit and a second signal path through the second delay locked loop circuit as a signal path for at least one of transmitting and receiving the information.

Abstract: A calibration circuit for a DCO includes a signal-conditioning module configured for (i) receiving at input an oscillating signal generated by the DCO and a reference signal, both designed to oscillate between a high logic value (“1”) and a low logic value (“0”), and (ii) detecting a respective first and second stable logic value of the reference signal and of the oscillating signal; and a period-to-voltage converter module coupled to the signal-conditioning module and configured for (iii) generating a difference signal identifying a difference between the period of the reference signal and the period of the oscillating signal, and (iv) controlling, on the basis of the difference signal, the DCO so as to conform the duration of the period of the oscillating signal to the duration of the period of the reference signal. Likewise described is a calibration method implemented by the calibration circuit.

Abstract: Embodiments provide a multi-phase clock generator. The clock generator includes a loop oscillator, a RC filter, a bias current source and a frequency injection source. The loop oscillator includes N levels of CMOS phase inverters which are connected in series and form a loop, N represents an odd number greater than 1. The N levels of CMOS phase inverters have the same structures, each of which includes a CMOS phase inverter main body and a tail current source which is a current mirror of the bias current source. As an effect of RC filter, a clock input signal inputted by the frequency injection source is applied to the first level tail current source, while other tail current sources are not influenced. Injection locking is induced, such that phase noise and frequency stray can be reduced.

Abstract: A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: A signal transmission method suitable for a signal transmitter includes: providing a plurality of clock signals with different phases, selecting some of the clock signals as a plurality of intermediate signals; transmitting the intermediate signals to a signal output circuit via a clock distribution network; selecting one of the intermediate signals as a reference clock of the signal output circuit to output data.

Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Abstract: A touch sensing device includes a display panel including a touch screen on which a plurality of touch sensors are formed, a touch sensing circuit including at least one sensing unit which receives self capacitance signals of a first touch sensor and a second touch sensor adjacent to the first touch sensor at differential input method and detects changes in capacitances of the first and second touch sensors, and a touch controller which analyzes touch raw data received from the touch sensing circuit and calculates coordinates of a touch input position. The sensing unit generates delays corresponding to a difference between the capacitances of the first and second touch sensors, accumulates the number of delays, converts an accumulated value of the delays into digital data, and generates the touch raw data.

Abstract: Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.

Abstract: A digital controlled oscillator includes: a delay circuit which includes m elements transmitting a pulse signal with delay; a timing signal generator generating a timing signal corresponding to timing-selection data from passing signals, based on the timing-selection data specifying any of timings which are obtained by dividing a circulation period of the pulse signal by m×n; and an output signal generator which sets the timing-selection data based on control data specifying a period of an output pulse signal and the timing-selection data, and generates the output pulse signal based on the timing-selection data by using the timing signal. The timing signal generator generates the timings obtained by dividing the circulation period by m×n by using pulse edge shift circuits which generate n shift signals whose timings differ by a unit delay from one input signal, the unit delay being 1/n of delay time in the element.

Abstract: A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

Abstract: A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.

Abstract: Techniques for designing baseband processing circuitry for radio IC's. In an aspect, techniques for differential-to-single-ended conversion in a baseband portion of the IC are disclosed to reduce the pin count and package size for RF IC's. In another aspect, the converter includes selectable narrowband and wideband amplifiers, wherein the wideband amplifiers may be implemented using transistor devices having smaller area than corresponding transistor devices of narrowband amplifiers. Further techniques for bypassing one or more elements, and for implementing a low-pass filter of the converter using an R-C filter network, are described.

Abstract: A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.

Abstract: A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.

Abstract: An in situ pulse-based delay variation monitor that predicts timing errors caused by process and environmental variations is revealed. The monitor includes a sequential storage device having a mater storage device and a slave storage device, a transition detector that is electrically connected to a node set on an electrical connection pathway from a master storage device to the slave storage device, and a warning signal generator electrically connected to the transition detector. The transition detector receives output of the master storage device to form a warning area by delay buffer, and generates a pulse width output correspondingly according to transition of the data input. Thus the warning signal generator generates a warning signal according to logic action at the pulse width and the clock input when the data input reaches the warning area. Thereby timing errors caused by static process variations and dynamic environmental variations are predicted.

Abstract: A receiver circuit includes: first and second phase adjusters that generate first and second clock signals; first and second determinators that perform binary determination on input data in synchronization with the first and second clock signals; a phase detection circuit that detects a phase on the basis of determination values of the first and the second determinators; a filter that performs filtering on the detected phase and thereby outputs first phase information to the second phase adjuster; an adder that adds a shift amount to the first phase information and thereby outputs second phase information to the first phase adjuster; and a corrector that outputs third phase information for decreasing variation in phase difference of the first clock signal with respect to the second clock signal to the first phase adjuster.

Abstract: Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency.

Abstract: Among other things, one or more techniques or systems for delay path selection are provided. A digitally controlled oscillator comprises an arrangement of inverters, such as tri-state inverters, that are selectively utilized to provide a process, voltage, temperature (PVT) condition output used to generate a frequency output for the digitally controlled oscillator. Delay path interpolation is used to generate a relatively high resolution range of PVT condition outputs, which results in a reduction of frequency gain (KDOC) between PVT condition outputs for improved performance of the digitally controlled oscillator.

Abstract: This document discusses, among other things, digital-to-time converters (DTCs) and more particularly to parallel implementations of DTCs. In an example, an apparatus can include a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information of a polar transmitter and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information of the polar transmitter and to provide a second portion of phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal.

Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Abstract: Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.

Abstract: A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

Abstract: Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.

Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Abstract: A semiconductor device including an integrator circuit, in which electric discharge from a capacitor can be reduced to shorten time required for charging the capacitor in the case where supply of power supply voltage is stopped and restarted, and a method for driving the semiconductor device are provided. One embodiment has a structure in which a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit. Further, in one embodiment of the present invention, a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit; the transistor is on in a period during which power supply voltage is supplied; and the transistor is off in a period during which supply of the power supply voltage is stopped.

Abstract: A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.

Abstract: An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tuneable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network.

Abstract: A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.

Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Abstract: A voltage controlled oscillator (VCO) includes a sensing circuit, where the sensing circuit is configured to generate a plurality of compensation control signals. The VCO further includes a voltage-to-current converter comprising a plurality of current sources which are configured to generate a current signal in response to the plurality of compensation control signals. Additionally, the VCO includes a plurality of switching circuits, each of the plurality of switching circuits being configured to selectively enable or disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals. Furthermore, the VCO includes a current controlled oscillator configured to generate an oscillating signal in response to the current signal.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range.

Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

Abstract: A phase-locked loop (PLL) device includes synchronization means suitable for synchronizing a frequency-converted signal produced by a frequency divider of the PLL device, with a reference signal supplied to the PLL device. A time duration of a frequency/phase lock acquisition step which is performed upon starting an operation of the PLL device can be reduced. In addition, when operating several PLL devices simultaneously, the synchronization units allow recovering target values for phase differences that exist between the respective frequency-converted signals of the PLL devices. To this end, synchronization is requested at a same time for all the PLL devices after they are all running in locked state.

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.

Abstract: A self-biased Phase Locked Loop (PLL) is provided. The self-biased PLL includes a bias current generator configured to generate a bias current Ib, wherein the bias current Ib includes one or more adjustable parameters for adjusting a loop bandwidth wn of the self-biased PLL. The one or more adjustable parameters in the bias current Ib includes at least one of a reference voltage Vref and a reference frequency Fref.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.