Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract: The invention discloses a charge pump, a phase locked loop circuit and a charge pump method. The charge pump comprises an input port, a switch and an output port. The input port receives a phase frequency adjustment parameter. The switch switches a first current on or off, according to the phase frequency adjustment parameter, and keeps a second current on. The first current is larger than the second current. The output port outputs a sum of the first current and the second current to a low pass filter.

Abstract: A control circuit of a power converter is provided. The control circuit includes a switching circuit and a charge pump circuit. The switching circuit generates a switching signal for controlling the power converter. The charge pump circuit includes an oscillator for generating an oscillation signal synchronized with the switching signal. The oscillation signal is coupled to control a switch of the charge pump circuit for generating a voltage source.

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract: A wideband frequency synthesizer and a frequency synthesizing method thereof are provided. The wideband frequency synthesizer includes a phase-locked loop unit, a first voltage-controlled oscillating unit and a first frequency mixer unit. The phase-locked loop unit receives a reference signal and a feedback signal and generates a first oscillating signal according to the reference signal and the feedback signal. The first voltage-controlled oscillating unit generates a second oscillating signal. The first frequency mixer is coupled to the phase-locked loop unit and the first voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal for mixing frequencies of the first oscillating signal and the second oscillating signal to generate an output signal and taking the output signal as the feedback signal for outputting to the phase-locked loop unit.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected.

Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected.

Abstract: A charge pump phase-locked loop circuit includes an active loop filter, an adjustable reference voltage source, and a charge pump. The active loop filter includes an amplifier that has a negative input node, a positive input node, and an output node. The adjustable reference voltage source is coupled to the positive input node to provide an adjustable reference voltage. The charge pump is coupled to the negative input node to provide a current to or draw a current from the active loop filter in response to a signal from a phase detector. The charge pump includes a first current source coupled to a first voltage and a second current source electrically coupled to a second voltage, the second current source including a resistor. The second current source is configured such that a current provided by the second current source depends on a resistance value of the resistor and a difference between the reference voltage and the second voltage.

Abstract: A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.

Abstract: Disclosed herein are a delay-locked loop circuit using a phase inversion locking algorithm and a method of controlling the same. There is provided a delay-locked loop circuit using a phase inversion locking algorithm, including a phase inversion controller configured to control whether or not to use the phase inversion locking algorithm by determining a phase error between an input clock signal and an output clock signal, an inverter configured to invert the input clock signal and output the inverted input clock signal, a multiplexer configured to receive the input clock signal and the inverted input clock signal of the inverter and output the input clock signal in response to the control signal of the phase inversion controller or the inverted input clock signal, and a delay-locked loop connected to the output terminal of the multiplexer and configured to perform phase synchronization in response to the output signal of the multiplexer.

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device tests a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: A method includes providing an active circuit element in a feedback path between an output node and a bypass node of a charge pump of a Phase Locked Loop (PLL). The bypass node is a node to which a charge current or a discharge current is steered to by the charge pump when neither charging the output node nor discharging the output node is required. The method also includes servoing the bypass node to the output node through the active circuit element in the feedback path to maintain a same voltage at the output node and the bypass node when neither the charging of the output node nor the discharging of the output node is required.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: A phase-locked loop circuit includes an oscillator circuit that generates a clock signal. The oscillator circuit has gears. Each of the gears of the oscillator circuit corresponds to a respective frequency range of the clock signal. A gear control circuit includes a regulator circuit that provides a supply voltage to the oscillator circuit. Each of the gears of the oscillator circuit corresponds to a different supply voltage provided by the regulator circuit. The regulator circuit varies the supply voltage to change a selected one of the gears of the oscillator circuit. The gear control circuit varies the supply voltage for one of the gears of the oscillator circuit to adjust a frequency range of that gear of the oscillator circuit.

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: A phase lock loop having a lock detector is provided. The lock detector is based on a replica charge pump and includes: a charge pump, a filter and a comparing circuit. The charge pump is arranged for providing an output according to a phase difference between an output signal and a reference signal. The filter is coupled to the charge pump, and is arranged for filtering the output of the charge pump to generate a filtered output voltage. The comparing circuit is coupled to the filter, and is arranged for comparing the filtered output voltage with a threshold setting to generate a lock indication signal to indicate whether the output signal is locked to the reference signal.

Abstract: A circuit for generating a voltage is disclosed. The voltage has an amplitude greater than an available power supply. The circuit includes a driver to supply the voltage on an output terminal to an electrode of a touch sense array. The circuit also includes a charge pump array coupled to the driver. The charge pump array includes an array of charge pumps to supply an input voltage to the driver. The circuit also includes a feedback circuit coupled to the charge pump array. The feedback circuit is configured to measure the input voltage and to select different combinations of the array of charge pumps to maintain the voltage on the output terminal.

Abstract: A charge pump phase-locked loop circuit includes an active loop filter, an adjustable reference voltage source, and a charge pump. The active loop filter includes an amplifier that has a negative input node, a positive input node, and an output node. The adjustable reference voltage source is coupled to the positive input node to provide an adjustable reference voltage. The charge pump is coupled to the negative input node to provide a current to or draw a current from the active loop filter in response to a signal from a phase detector. The charge pump includes a first current source coupled to a first voltage and a second current source electrically coupled to a second voltage, the second current source including a resistor. The second current source is configured such that a current provided by the second current source depends on a resistance value of the resistor and a difference between the reference voltage and the second voltage.

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.

Abstract: A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane.

Abstract: An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract: A clock and data recovery circuit includes a phase detector circuit, a charge pump circuit, and a voltage controlled oscillator. The phase detector circuit receives a data signal from an external device and a clock signal from the voltage controlled oscillator and generates a first and a second phase difference signal. The charge pump circuit includes an OR gate receiving on its inputs the first and the second phase difference signals and configured to generate a current if the first and/or second phase difference signal is high.

Abstract: A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1 ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a calibration signal, and an output to generate a control voltage. The replica charge pump includes up and down input terminals to receive DN and UP control signals, a control terminal to receive the calibration signal, and an output to generate a replica voltage. The op-amp generates the calibration signal in response to the control voltage and the replica voltage.

Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock.

Abstract: A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.

Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

Abstract: A circuit comprising a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals, and a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a feedback signal based on the one or more tuning signals, wherein generating the one or more tuning signals is based on the feedback signal.

Abstract: A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.

Abstract: A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.

Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Abstract: Systems and methods for capacitance multiplication using one charge pump for a phase lock loop employ a digital controlled loop filter that operates in a time division mode. Embodiments of the loop filter block the current from the charge pump according to the digital control, such that the charge pump cannot charge or discharge the integral capacitor when the digital control is enabled. Because at least a portion of the current is blocked, it takes more time for the charge pump to charge or discharge the capacitor to a certain level. The capacitor then appears to be larger than its actual value with respect to operation of the phase lock loop.