Abstract: In the present invention, wasted power consumption caused when a clock and data recovery unit in an optical network unit in a PON system is activated from a power-saving state is reduced and rapid, secure communication is performed. A clock and data recovery unit includes a phase-locked loop that can be set to normal mode or power-saving mode and that includes a voltage-controlled oscillator and recovers a clock signal and a data signal from input signals. The clock and data recovery unit includes a reference clock multiplier circuit that multiplies a reference clock signal and outputs the multiplied reference clock signal; and a frequency training loop that includes the same voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop transitions from power-saving mode to normal mode.

Abstract: An electrical circuit including a controllable oscillator, a transmission line and a control loop. The controllable oscillator is configured to generate an oscillating signal. The transmission line is connected to an output of the oscillator, wherein the transmission line has a length which is a fraction of a wavelength of the oscillating signal. The control loop is configured to detect a difference between a first value of a signal parameter of the oscillating signal and a second value of the signal parameter of the oscillating signal having passed the transmission line. Furthermore, the control loop is configured to control the controllable oscillator in accordance with the difference.

Abstract: An apparatus includes a first oscillator configured to generate a reference signal and a second oscillator configured to generate an output signal having a controllable frequency. The apparatus also includes a frequency difference detector configured to generate a difference signal having a frequency based on a frequency difference between the reference signal and the output signal. The apparatus further includes a discriminator configured to modify the frequency of the output signal based on the difference signal. The frequency difference detector can be configured to generate the difference signal having multiple pulses. The discriminator can be configured to count a number of pulses in the difference signal during a specified time period and to modify the frequency of the output signal based on the counted number of pulses. The specified time period can be adjustable.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.

Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal.

Abstract: A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO.

Abstract: An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone.

Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

Abstract: A charge pump circuit includes a switching circuit for providing a charge and discharge current, and a control circuit for controlling the switching circuit. The switching circuit includes a first switch for controlling the charging speed. The control circuit generates a signal for controlling the first switch based on the pulse width of the input signal. The charge pump circuit of the present invention quickens the locking time of the phase locked loop.

Abstract: A method includes tracking a tuning voltage at a first circuit coupled to a first drain node of a first supply of a charge pump. The method also includes tracking the tuning voltage at a second circuit coupled to a second drain node of a second supply of the charge pump. The method further includes stabilizing a first voltage of the first drain node and a second voltage of the second drain node responsive to the tuning voltage.

Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.

Abstract: A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.

Abstract: A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.

Abstract: Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.

Abstract: A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal.

Abstract: A circuit containing a pair of charge pumps and an active filter receives outputs of a phase frequency detector used in a phase locked loop. The charge pump is implemented using switches and resistors to reduce performance variations due to component mismatches. The loop filter includes a resistor and a capacitor coupled in series, the resistor and the capacitor determining a zero of the transfer function of the loop filter. The charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node formed by a junction of the resistor and the capacitor. The polarity of the first current pulse is the opposite of the polarity of the second current pulse. Multiplication of the capacitance of the capacitor is thereby achieved, enabling implementation of the loop filter in integrated circuit form.

Abstract: A reference current generating circuit includes a generator that generates a reference voltage, a bias generator includes plural transistors of a different conductive types from each other and generates a first bias voltage and a second bias voltage, respectively, a first output transistor and a second output transistor of a different conductive type that outputs a current corresponds to a reference current when the first bias voltage or the second bias voltage is supplied thereto, an input-output unit that one terminal connected between the first output transistor and the second output terminal and the other terminal connected to a load, and supplies current from the first output transistor to the load or from the load to the second output transistor, and a switch that turns on/off the first and the second output transistors based on the output voltage of the input-output unit.

Abstract: A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.

Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

Abstract: The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter.

Abstract: In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage.

Abstract: Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations.

Abstract: Output driver feedback circuitry limits output slew rates across a wide range of output loads. A transition time lock loop architecture of the feedback circuitry compares a transition time pulse with a reference pulse to adjusts transition time of an output signal for various process-voltage-temperature (PVT) process corners, output voltage domains and output capacitances. Reference pulse generation circuitry provides a reference pulse in phase with the transition time pulse for each rise and fall of the output signal.

Abstract: A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages.

Abstract: A delay lock loop circuit includes a voltage controlled delay line for generating a plurality of specific phase differential signals and a feedback signal according to an input clock source and a control voltage, a detector for comparing at least one of phases and frequencies of the input clock source and the feedback signal to generate at least one detection signal, a charge pump for generating the control voltage according to the at least one detection signal, and a phase selection buffer for generating the output clock source according to the plurality of specific phase differential signals, wherein each of the plurality of specific phase differential signals includes at least a non-inversion signal and an inversion signal, and the feedback signal is the inversion signal of one of the plurality of specific phase differential signals.

Abstract: Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio.

Abstract: A fractional-N frequency synthesizer having reduced fractional switching noise and spurious signals is provided. The synthesizer includes a voltage controlled oscillator for providing an output signal. A fractional-N divider is responsive to the voltage controlled oscillator for providing a divided output signal having fractional switching noise. A band pass filter is responsive to the fractional-N divider for reducing the fractional switching noise and non-linearities that result in spurious signals. A phase detector is responsive to a reference signal and the band pass filter for providing a control signal representative of the phase difference between the reference signal and the signal from the band pass filter. A loop filter is responsive to the phase detector for filtering the control signal to control the voltage controlled oscillator, the output of the loop filter having reduced fractional switching noise and spurious signals.

Abstract: An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a “Charge Pump Output Voltage Replica Node” (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor.

Abstract: A display driving device includes an output circuit that drives display elements. The output circuit includes a bias circuit, an amplifier stage and an output stage. The bias circuit generates bias signals that include constant-current-control signals of a first bias signal and a second bias signal of the same polarity. The first and second bias signals are short circuited by a vertical line in the bias circuit and the vertical line is shielded. The amplifier stage is formed in a first well and constant-current-controlled by the first bias signal to amplify an input display signal. The output stage is formed in a second well. The first and second wells are formed separately in a semiconductor substrate. The output stage is constant-current-controlled by the second bias signal and supplies an output signal of the amplifier stage to the display element.

Abstract: Charge-based charge pumps are described which include a switchable capacitor configured for connection to a voltage source, a ground, and a charge pump output. A first pair of switches include a first switch configured to connect the switchable capacitor to ground and a second switch configured to connect the switchable capacitor to the voltage source. A second pair of switches include a third switch configured to connect a first node, between the switchable capacitor and ground, to the charge pump output, and a fourth switch configured to connect a second node, between the switchable capacitor and the voltage source, to the charge pump output. Locked loop designs, such as phase locked loops or delay locked loops, are described that include charge-based charge pumps.

Abstract: A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.

Abstract: A frequency generating system including a phase-locked loop (PLL) and a control signal generation unit is provided. The PLL outputs a phase-locked clock and controls a voltage-controlled oscillator (VCO) therein by using a dual-path architecture. The VCO includes a varactor. The control signal generation unit is coupled to the PLL and disposed in one of the dual paths. The control signal generation unit provides an up voltage, a down voltage, or a middle voltage as a control signal to control the VCO according to an up signal and a down signal of the PLL. The control signal generation unit provides the middle voltage in response to an electrical characteristic of the varactor to compensate the control signal.

Abstract: A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.

Abstract: An apparatus and a method for frequency calibration in a frequency synthesizer are disclosed. The present invention includes an up/down processor. The up/down processor is utilized for outputting one of a GND voltage and a VDD voltage to a voltage-controlled oscillator via a loop filter in an open loop status, or outputting one of a step-up voltage and a step-down voltage in accordance with a phase difference to the voltage-controlled oscillator via the loop filter in a close loop status. When the up/down processor outputs one of the GND voltage and the VDD voltage in the open loop status, a memory bank selector compares frequencies for selecting a value of a memory bank and then adds an offset to the value of the memory bank so as to determine a final value of a VCO memory bank in the phase locked loop.

Abstract: A phase difference detecting circuit 3 includes a sync detecting circuit 21 for detecting establishment of phase sync from phase difference signals D and U generated by a D-type flip-flop 13, and a switch 22 for supplying, unless the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage Vt1 generated by the current-output-matching loop filter 15 to a voltage-controlled oscillator 4, and for supplying, when the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage Vt2 generated by the voltage-output-matching loop filter 20 to the voltage-controlled oscillator 4.

Abstract: According to one embodiment, a lock detection circuit includes an initial state response circuit. The initial state response circuit is configured to output a third control signal to delay lines and cause a charge pump to stop an output of a second control signal when a pulse width modulation signal is not input, the third control signal is configured to control a delay amount to cause a delay amount of an entire delay circuit to be within one selected from a range in which an OVER signal generation circuit is operable, a range in which an UNDER signal generation circuit is operable, and a range that is greater than an UNDER threshold and less than an OVER threshold.

Abstract: A method and apparatus for implementation of PLL minimum frequency via voltage comparison have been described.

Abstract: In a PLL frequency synthesizer, a loop is constituted by a phase comparison unit, a gate unit, a charge pump, a capacitive element, a potential adjustment unit, a voltage-controlled oscillator, and a feedback division unit. In this loop, the gate unit and the charge pump are provided in parallel with the potential adjustment unit. A charging/discharging current is input from the charge pump to the capacitive element and the potential of a first end of the capacitive element is adjusted by the potential adjustment unit, so that a phase difference between a reference oscillation signal and a feedback oscillation signal input to the phase comparison unit is small.

Abstract: An electrical circuit including a controllable oscillator, a transmission line and a control loop. The controllable oscillator is configured to generate an oscillating signal. The transmission line is connected to an output of the oscillator, wherein the transmission line has a length which is a fraction of a wavelength of the oscillating signal. The control loop is configured to detect a difference between a first value of a signal parameter of the oscillating signal and a second value of the signal parameter of the oscillating signal having passed the transmission line. Furthermore, the control loop is configured to control the controllable oscillator in accordance with the difference.

Abstract: An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.

Abstract: Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.

Abstract: A delay lock loop circuit includes a voltage controlled delay line for generating a plurality of specific phase differential signals and a feedback signal according to an input clock source and a control voltage, a detector for comparing at least one of phases and frequencies of the input clock source and the feedback signal to generate at least one detection signal, a charge pump for generating the control voltage according to the at least one detection signal, and a phase selection buffer for generating the output clock source according to the plurality of specific phase differential signals, wherein each of the plurality of specific phase differential signals includes at least a non-inversion signal and an inversion signal, and the feedback signal is the inversion signal of one of the plurality of specific phase differential signals.

Abstract: A charge pump circuit includes a charge generation circuit, a tracking circuit, a replica circuit, and a main charge pump. The main charge pump generates a charge current and a discharge current to a subsequent loop filter according to a UP signal and a DOWN signal. The replica circuit generates a first voltage in response to the current values of the first current source and the second current source of the main charge pump. The tracking circuit adjusts the current values of the first current source and the second current source of the main charge pump according to the first voltage and a second voltage, wherein the second voltage is in response to a voltage of an output node of the main charge pump.