Abstract: A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units bein

Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.

Abstract: Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: This invention generates two pulses for semiconductor testing that have leading edges coordinated in time by synchronizing the pulses from two different styles of pulse generators (pulsers). One pulser uses spark discharge pulse generation and the other pulser is a typical solid state pulser. The spark discharge pulser has high power pulse generation but its pulse timing can not be tightly controlled. The output pulse of the spark discharge pulser is split unequally, with a small amount used to trigger the solid state pulser, and the large pulse energy delayed by a cable of length for a signal propagation delay equal or greater than the trigger-input-to-pulse-output delay of the solid state pulser. Variable attenuators control the trigger signal amplitude and a level shifting circuit makes the trigger signal compatible with standard logic signal levels. The two pulses can be applied to semiconductors with their leading edges adjustable relative to each other to measure the semiconductors operation.

Abstract: A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal.

Abstract: A digital ring oscillator outputting a toggled clock signal. The clock signal is generated by a plurality of electronic cells that are arranged in series. At least one of the plurality of electronic cells receives a feedback of the clock signal. Control signals are received at an input for the plurality of electronic cells. Each electronic cell includes a first logic gate, a second logic gate, and an inverted logic gate coupled between the first logic gate and the second logic gate. For each electronic cell, a respective control signal controls whether an output signal received from the first logic gate of a preceding electronic cell is transferred through the first logic gate to the first logic gate in a succeeding electronic cell, or is inverted and transferred through the second logic gate to the second logic gate in a preceding electronic cell, based on the control signal.

Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.

Abstract: A clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock is presented. The circuit and method include a clock enable control circuit generating a clock enable control signal controlled by a power supply voltage and a power-down signal. The circuit and method also include a clock generating circuit receiving an input clock which selectively generates an internal clock synchronized to an external clock using the input clock using the clock enable control signal. Whereupon, a locking failure can be prevented by performing a phase update operation selectively in accordance with whether the power supply voltage is varied or not in the power-down mode. Furthermore, current consumption can be reduced by controlling phase update time in accordance with a variable magnitude of the power supply voltage.

Abstract: A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A change-point detection circuit 16 extracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A system comprises first timing logic configured to produce a first signal and second timing logic configured to produce a second signal. The system also comprises processing logic coupled to the first and second timing logic. The system further comprises clock logic that determines elapsed time using the first signal. The processing logic compares the first and second signals and, based on the comparison, the system adjusts the elapsed time.

Abstract: A delay apparatus, and a delay locked loop circuit and a semiconductor memory apparatus using the same are provided. A delay locked loop circuit includes a register controlled delay part that delays a plurality of clocks input during an initial operation by delay amounts among initial delay amounts to be varied, which are set according to initial state setting signals, and increases or decreases the set delay amounts according to a phase detecting signal after the initial operation, a phase comparator that compares a phase of any one of the plurality of clocks and a phase of any one of the plurality of clocks delayed by the register controlled delay part and outputs the phase detecting signal, and an initial state setting unit that generates the initial state setting signals.

Abstract: A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is changed when electromagnetic interference (EMI) is detected, for the DLL clock to have frequencies within a delay locking range, and a data output circuit configured to output data in synchronization with the DLL clock.

Abstract: A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.

Abstract: A data recovery apparatus and method for receiving at least an original clock and at least an original data stream output from a transmitter to output at least one recovery data are provided. The original data stream and the recovery data respectively include N steps in a period T of the original clock, wherein N is an integer larger than 0. The data recovery apparatus includes a sampling unit and a processing unit. The sampling unit samples the original data stream according to the original clock, wherein the sampling unit samples the corresponding data of the original data stream at least three times with T/(4N) sample period in each step. The processing unit receives and compares the sampled result output from the sampling unit, and recovers the sampled result to the recovery data according to the compared result.

Abstract: A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

Abstract: Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.

Abstract: A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.

Abstract: An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal.

Abstract: A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

Abstract: Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.

Abstract: Provided is a pulse phase difference detecting circuit including: a first delay circuit that receives a first pulse signal to output a signal obtained by delaying the first pulse signal as a second pulse signal and includes multiple serially-connected delay units having the same delay amount; a second delay circuit that receives the second pulse signal and includes multiple serially-connected delay units having the delay amount; a first delay adjustment circuit that adjusts a delay amount with respect to the second pulse signal and outputs the adjusted second pulse signal back to the first delay circuit as a third pulse signal; and a pulse arrival position detecting circuit that detects a pulse arrival position of the first pulse signal based on outputs of the delay units of the first and second delay circuits that are transmitted as the third and second pulse signals, respectively.

Abstract: A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal ‘IOSTB’, and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal.

Abstract: An operation mode setting apparatus includes an operation mode setting control unit that discriminates the phase of a reference clock from the phase of a feedback clock and generates a locking suspension signal, and an operation mode setting unit that generates a locking completion signal in response to a pulse signal and a phase comparison signal under the control of a reset signal and the locking suspension signal.

Abstract: A ring oscillator includes a first logic block having a first input connected to a specific point along a delay path, a first output and a second output, and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path, and a first output connected to the beginning of the delay path. The first logic block is arranged to alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to alternately select its first input and its second input every time a rising edge is input into its third input.

Abstract: High Speed I/O interfaces (600) such as DVI, S-ATA or PCI-Express require expensive test equipment. Loop-back tests are widely used as one alternative, but lack coverage of timing-related defects. A system and method for on-chip jitter injection using a variable delay (203) with controllable amplitude (501) and high accuracy is provided that improves the coverage of loop-back tests.

Abstract: The semiconductor device may include a calibration circuit, a control unit, and a delay unit. The calibration circuit may be configured to output an output signal. The control unit may be configured to generate and output the control signal in response to the output signal of the calibration circuit. The control unit may generate the control signal by using a correlation between a signal transmission speed of the semiconductor device and the output signal of the calibration circuit. The delay unit may be configured to delay a clock signal in response to the control signal and output the delayed clock signal to the output driver.

Abstract: A delay amount estimating apparatus includes a delay value search section that searches for a first delay value smaller than a delay setting value at which a given correlation value between an input signal and a feedback signal is provided, and also for a second delay value greater than the delay setting value, the feedback signal coming from a signal processing apparatus that applies signal processing on the input signal, wherein respective correlation values of the first delay value and the second delay value satisfy a given condition; and a delay estimating section that estimates a delay amount of the feedback signal relative to the input signal based on the first delay value and the second delay value.

Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.

Abstract: A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

Abstract: A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.

Abstract: A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit. A wait time determination unit selects one of the wait time signals and provides the selected wait time signal to a clock control unit. The wait time determination unit includes a data holding circuit which generates a selection signal in accordance with the initial value, a selection circuit which selects one of the wait time signals based on the selection circuit, and an initial value setting circuit enabling the initial value to be varied.

Abstract: A clock signal generating circuit includes a main delay circuit and a variable delay circuit. The main delay circuit receives a feedback clock signal, and outputs an output clock signal after a first delay when receiving the feedback clock signal. The variable delay circuit receives the output clock signal, and updates the feedback clock signal after a second delay when receiving the output clock signal. The second delay is periodically varied and is shorter than the first delay.

Abstract: A DLL circuit comprising: delay circuits which output first and second delayed clock signals obtained by delaying the reference clock signal by a delay times selected according to control signals; an interpolation circuit which interpolates a phase difference between the delayed clock signals to output an internal clock signal; an output circuit which generates a predetermined signal; a dummy output circuit which has the same transmission characteristics as the output circuit and outputs a feedback clock signal having the same phase as the predetermined signal; a phase comparison circuit which compares phases of the reference clock signal and the feedback clock signal; delay control circuits which controls the control signals in a direction where both phases are equal; wherein the delay time of the second delayed clock signal is larger than the first delayed clock signal by an amount equivalent to one cycle of the reference clock signal.

Abstract: A DLL circuit includes a first delay line circuit, a first phase comparison circuit, a control circuit, and a first selecting circuit. The first delay line circuit can change a delay amount and provide a delay to a first clock signal. The first phase comparison circuit can detect a phase difference between the first clock signal and an output signal of the first delay line circuit, and a phase difference between a test clock signal of which frequency is lower than the first clock signal and an output signal of the first delay line circuit or a signal after dividing the output signal. The control circuit controls a delay amount of the first delay line circuit according to the detection result of the first phase comparison circuit.

Abstract: A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another.

Abstract: A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.

Abstract: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Abstract: A circuit includes a sensing circuit, a control circuit, and a programmable delay circuit. The sensing circuit generates delay compensation signals that change in response to variations in at least one of a process and a temperature of the circuit. The control circuit generates dynamic control signals in response to the delay compensation signals. The programmable delay circuit is configurable to delay a signal transmitted through an external terminal of the circuit by a delay that is selected by the dynamic control signals.

Abstract: A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal.

Abstract: A digital DLL circuit includes: a first register configured to hold a first delay specifying value to specify a delay of a rising edge side of a signal; a second register configured to hold a second delay specifying value to specify a delay of a falling edge side of a signal; and a digitally-controlled variable delay circuit configured to be allowed to individually control delays of a rise side and a fall side of a signal. The digital DLL circuit further includes a control circuit configured to implement control so that a rise-side delay and a fall-side delay by the variable delay circuit are kept at the first delay specifying value of the first register and the second delay specifying value of the second register, respectively.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Optionally, the programmable delay element utilizes current-mode logic (CML) and the control signal is a thermometer coded digital signal. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.

Abstract: An output circuit includes a detector receiving a parallel data signal, detecting a level change degree for the parallel data signal between a first time point and a second time point, and outputting a select signal according to the level change degree; a delay adjusting device receiving and differentially delaying the parallel data signal into a first and a second delayed parallel data signals with a first and a second delay time, respectively; and a first multiplexer electrically connected to the detector and the delay adjusting device, and selecting one of the first and the second delayed parallel data signals to be outputted in response to the select signal.

Abstract: A variable delay circuit 1 includes: a multistage delay circuit 20 constructed by connecting delay elements D1 to Dn in series; a selecting unit 21 which selects one delayed signal obtained by introducing different amounts of delay by passing a reference clock through one or more of the delay elements D1 to Dn; a decision unit 23 which, at decision timing synchronized to the reference clock, makes a decision on the logic state of each delayed signal sequentially selected from among the plurality of delayed signals; and a changing point detection unit 24 which detects at least two delay elements Dm and Dk where a change has occurred in the logic state of the reference clock at the decision timing, and wherein the difference (k?m) between the numbers of delay elements through which the clock signal has passed until reaching one of the two detected delay elements Dm and Dk is used as the number of delay elements that provides a desired delay time.

Abstract: A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.