Abstract: Through the use of a multi-step sweep, the present invention is capable of increasing the speed and improving the error resistance of a signal alignment. In a specific embodiment of the invention, a method for the signal alignment of a target signal and an adjustable signal is disclosed. The target signal is sampled using three or more phase shifted versions of the adjustable signal to obtain a group of target signal state values. Next, through reference to the group of target signal state values it is determined that an edge of the target signal lies between a first phase shifted version and a second consecutive phase shifted version. In response, the first phase shifted version is selected as the starting point for a second sweep. During the second sweep, the phase of the first phase shifted version is sequentially adjusted in relatively small incremental steps to minimize the phase difference relative to the target signal.

Abstract: A DLL circuit includes an input circuit generating a synchronization reference signal, a first delay unit delaying the synchronization reference signal to generate a plurality of delayed synchronization reference signals and selecting one of the delayed synchronization reference signals, a timing offset circuit adjusting a synchronization position of the delayed synchronization reference signal to generate a signal to be synchronized, a phase comparison circuit comparing phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit selecting an output signal of the first delay unit, a second delay unit delaying the synchronization reference signal or the signal to be synchronized to generate a plurality of delayed signals, a configuration information memory storing configuration information, and a second control circuit selecting an output signal of the second delay unit if the comparison result of the phase comparison circuit is within a predetermined range

Abstract: A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.

Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Abstract: A semiconductor integrated circuit includes an update control unit configured to generate an update control signal in response to a first command and a second command; and a DLL (Delay Locked Loop) circuit configured to generate an output clock by controlling a phase of an external clock in response to the update control signal.

Abstract: A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.

Abstract: The phase interpolator includes two adjustable delays 30 and 31, phase comparator 32 which detects a phase difference between a signal delayed by the adjustable delay 30 and a signal delayed by the adjustable delay 31, an integrator 33 which integrates the outputs of the phase comparator 32 and multipliers 34-1 and 34-2 which set a control voltage for the adjustable delays 30 and 31. The feedback loop comprising phase comparator 32 and integrator 33 controls a delay amount of the adjustable delay 30 thereby securing a phase relation between {ACK1, ACK2} and ICK to achieve a stable ICK phase.

Abstract: Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical.

Abstract: A delay locked loop circuit and a method for controlling the same including a delay locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal synchronized to the external clock signal includes at least two delay chains having different types of delay cells for delaying the external clock signal. Thus, the layout area and power consumption can be reduced, and logic failures can be prevented or minimized by replacement or compensation of the main delay cells.

Abstract: This invention relates to devices, a chip, a method and a computer-readable medium for controlling operation of a delay-locked loop. A delay-locked loop unit is adapted to trigger generation of first-type edges of a target signal. A main control unit is adapted to control operation of the delay-locked loop unit in a way that the delay-locked loop unit is turned on before generation of each first-type edge of the target signal and turned off after generation of each first-type edge.

Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Abstract: An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal. The clock input is delayed by a phase delay magnitude to generate a second phase signal and the second phase signal is delayed by about the phase delay magnitude to generate a last phase delay signal. A phase difference is detected between the first phase delay signal and the last phase delay signal and adjustments are made to at least one of the phase delay magnitude and the alignment magnitude.

Abstract: Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed.

Abstract: A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device.

Abstract: Two versions of a binary signal having an irregular sequence of states are processed by deriving (i) a first value which represents the average time derivative of one signal at the times of transitions in the other signal, and (ii) a correlation value for the two signals, and then combining the first value with the correlation value. For a given relative delay introduced between the signals, the resultant combined value indicates whether the introduced delay brings the transitions in the two signals into coincidence. The process can be repeated for other introduced delays to determine the amount of delay between the two signals.

Abstract: A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.

Abstract: A semiconductor device includes a first signal generator that generates a plurality of second signals having a delay relative to a first signal and having states that change at different timings, a second signal generator that generates a third signal having a delay relative to the first signal, and a detector that detects, when a state of the third signal changes, a delay state of a signal based on the states of the second signals, wherein the first signal generator and the second signal generator are different from each other in an amount of change in delay relative to a change in an operating state.

Abstract: A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals.

Abstract: A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.

Abstract: In a semiconductor device, a delaying circuit is configured to delay an input signal based on an internal setting data to output as a timing signal. A delay determining section is configured to determine a delay state of each of a plurality of delay signals obtained by delaying the timing signal, based on the plurality of delay signals. A program section is configured to change the internal setting data based on the delay state.

Abstract: A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.

Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.

Abstract: A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to delay an external clock signal to produce a substantially in-phase output clock signal, a main loop configured to control delay through the delay line, and a secondary loop configured to adjust delay through the main loop. The clock synchronization method generally includes adjusting a delay along a delay line in response to a first phase difference between an input clock to the delay line and a shared clock signal delayed by a shared dynamic I/O model of an output driver. The method further includes adjusting the shared dynamic I/O model in response to a second phase difference between an output clock signal and the shared clock signal.

Abstract: Error occurrence is predicted before the error occurs. Included are: a clock regeneration circuit (11) that regenerates, from a data input signal (Din), a clock signal (CK1) related to the data input signal (Din); a sampling clock generation circuit (12) that generates one or more sampling clock signals (CK2 and CK3) that are synchronous with the regenerated signal (CK1) and have a constant phase difference with respect to the regenerated clock signal (CK1); a sample and hold circuit (13) that samples and holds the data input signal (Din) according to the one or more sampling clock signals (CK2 and CK3) and the regenerated clock signal (CK1) respectively; and an error determination circuit (14) that outputs an error prediction signal (Ep) in a case where logical values of respective sampling results of the sample and hold circuit (13) are not all identical.

Abstract: The phase interpolator includes two adjustable delays 30 and 31, phase comparator 32 which detects a phase difference between a signal delayed by the adjustable delay 30 and a signal delayed by the adjustable delay 31, an integrator 33 which integrates the outputs of the phase comparator 32 and multipliers 34-1 and 34-2 which set a control voltage for the adjustable delays 30 and 31. The feedback loop comprising phase comparator 32 and integrator 33 controls a delay amount of the adjustable delay 30 thereby securing a phase relation between {ACK1, ACK2} and ICK to achieve a stable ICK phase.

Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.

Abstract: Deskewing method and apparatus, including: an up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions by using the result of the sampling, a lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area, an upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area, a phase detection unit determines a delay amount according to the upper limit detected by the upper limit detection unit and the lower limit detected by the lower limit detection unit, a buffer unit delays the data signal by the delay amount determined by the phase detection unit.

Abstract: Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor (17) (internal voltage (Va)) to increase from a ground voltage (VSS) to a voltage equal to or higher than an inverting threshold voltage of a constant current inverter (19) (threshold voltage (Vtn) of an NMOS transistor (16)). Therefore, the delay time period is determined with reference to the ground voltage (VSS). Note that the same holds true for an internal delay circuit (20). If the input signal (Vin) becomes High, the delay circuit utilizes the delay time period caused by an internal delay circuit (10). On the other hand, if the input signal (Vin) becomes Low, the delay circuit utilizes the delay time period caused by the internal delay circuit (20).

Abstract: A DLL circuit includes: a phase determining circuit that compares phases of respective rising edges of CK and LCLK to generate a determining signal R-U/D; a phase determining circuit that compares phases of respective falling edges of CK and LCLK to generate a determining signal F-U/D; a first adjusting circuit that adjusts a position of an active edge of LCLKR based on the determining signal R-U/D; a second adjusting circuit that adjusts a position of an active edge of LCLKF based on the determining signal F-U/D; a clock generating circuit that generates LCLK based on LCLKR and LCLKF; and a stop circuit that stops an adjusting operation by the second adjusting circuit in response to an adjusting direction of the active edge of LCLKR being opposite to each other to an adjusting direction of the active edge of LCLKF.

Abstract: A duty cycle correction circuit with wide-frequency working range utilizes a pulse generator having adjustable pulse width function to adjust the width of the pulse and outputs a clock signal with the duty cycle of 50%. The pulse generator includes a NAND gate, a modulation device, and an inverter. The inverter is coupled between the second input end of the NAND gate and the modulation device. The modulation device modulates the low-level status of the input clock signal and accordingly outputs to the inverter. The first input end of the NAND gate receives the input clock signal. The NAND gate operates NAND calculation to the signals received on the input ends of the NAND gate and accordingly outputs a periodic low-level pulse signal.

Abstract: Embodiments for positioning rising and/or filling edges of data strobe signals are disclosed. One example embodiment may comprise receiving a data signal, positioning an edge of a first delayed data strobe signal associated with the data signal by a first programmable amount, and positioning an edge of a second delayed data strobe signal associated with the data signal by a second programmable amount, wherein the second delayed data strobe signal is shifted approximately one bit-time in relation to the first delayed data strobe signal.

Abstract: Methods and apparatus are provided for digital compensation of clock timing errors in a VCDL. Clock timing errors in a clock and data recovery system having a voltage controlled delay loop comprised of a plurality of delay elements are compensated for by evaluating a phase of data recovered from an input signal; generating one or more uncompensated clock phase adjustment values based on the phase evaluation; generating one or more compensation terms that compensate for a non-ideal delay for one or more of the delay elements; and determining an adjustment to one or more clock phases produced by the voltage controlled delay loop based on the uncompensated clock phase adjustment values and the one or more compensation terms. The one or more compensation terms can be subtracted from the uncompensated clock phase adjustment values to generate the adjustment to the one or more clock phases.

Abstract: Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Abstract: A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

Abstract: A transit state element circuit. The transit state element circuit includes a clock input stage coupled to receive a clock signal, an output stage configured to drive an output signal on an output node and an activation stage coupled to an input node. The activation stage is configured to, responsive to the clock input stage detecting a transition from a first logic level to a second logic level and detecting a logical transition of an input signal on the input node, activate the output stage to drive an output signal on the output node. A storage element is configured to capture a logic value of the input signal when the clock is at the second logic level and to store the logic value, and to provide the output signal on the output node when the clock signal is at the first logic level.

Abstract: The invention relates to a method for the digital transmission of an analogue measuring signal (M), comprising the following steps: comparing momentary values of a triangular signal (D) with a value of the measuring signal (M) for generating a binary measurement pulse (PM); comparing momentary values of the triangular signal (D) with a predeterminable first reference variable (R1) for generating a binary reference pulse (PR) that corresponds to the measurement pulse (PM) and transmitting the measurement pulse (PM) and reference pulse (PR) at a constant phase.

Abstract: A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.

Abstract: Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.

Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.

Abstract: The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal.

Abstract: A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.

Abstract: A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively comparing a phase of a delayed feedback signal and a phase of the feedback signal with a phase of the external clock signal; a clock selecting block for selecting one of the first and second internal clock signals based on one comparison result to thereby generate a selected internal clock signal; a stuck checking block for determining a delay value based on the other comparison result; a delay line block for delaying the selected internal clock signal by the delay value; and an output buffer for buffering an outputted signal from the delay line block to thereby generating a DLL clock signal.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.