Abstract: Methods of sensory input integrity attestation are provided. Artifacts included within devices under test inject a known noise signal into the output signal of one or more output devices that are detectable by one or more input devices (i.e., sensors) of an embedded device, and monitor the received input data. By comparing the received signal against the expected noise signal, attestation of the validity of sensory input data is possible. Such sensory input data attestation is capable either locally or using a remote attestation device with knowledge of the expected data stream.

Abstract: A signal width repair circuit and method, and an electronic device are provided. The signal width repair circuit includes: a delay unit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a low-level signal; a signal reconstruction unit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection unit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Abstract: A communication device and a communication signal generation method that perform, adaptively, a wired power line communication that is given desired communication characteristics being in such a level as to satisfy user demands is provided. The communication device includes a selection unit a selection unit which selects a mode that prescribes a number of one or more channels prepared in a prescribed frequency band used for a communication to be performed with another communication device via a wired medium and a channel to be used for the communication in the mode; and a signal processing unit which generates communication frames to be used for the communication by performing signal processing on input data according to the selected mode and channel.

Abstract: The present disclosure relates to a data communication method and system. The method includes: a first terminal continuously generating a communication carrier signal; sending by the first terminal a communication data signal carrying a data packet to be processed, beginning to record the first number of pulses when the first terminal completes sending the data packet to be processed; receiving by the second terminal the communication data signal, beginning to record the second number of pulses when the second terminal completes receiving the data packet to be processed, generating a response data packet sending, by the second terminal, the response data packet to the first terminal when detecting that the second number reaches a pulse number threshold N; and allowing, by the first terminal, to begin receiving the response data packet when detecting that the first number is within a threshold range.

Abstract: A resonant converting apparatus and a control method thereof are provided. The resonant converting apparatus includes a resonant converting circuit, a load detector, a control signal generator and a pulse frequency modulation (PFM) signal generator. The resonant converting circuit converts an input voltage into an output voltage to drive a load according to a PFM signal. The load detector detects a load status of the load. The control signal generator generates the control signal according to the load status and a PFM range. When the load status is a light load status, the control signal is divided into a plurality of first time periods and second time periods which are respectively arranged alternatively. The PFM signal is maintained to a reference voltage during the second time periods, and is a periodical signal having frequency substantially equal to a resonant frequency during the first time periods.

Abstract: A method for compensating for a sampling clock-offset includes calculating a positive threshold and a negative threshold of pulse-shaped data symbols to be received, calculating a positive sum ratio and a negative sum ratio from received samples, and compensating for a sampling clock-offset in response to the positive sum ratio being less than or equal to the positive threshold and the negative sum ratio being less than or equal to the negative threshold.

Abstract: An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.

Abstract: A communication device includes a reception buffer configured to receive a pulse signal cyclically transmitted from a transmission source device via a transmission line; a branch circuit configured to generate a branch pulse signal by branching the pulse signal; a delay circuit configured to add a predetermined delay time to the generated branch pulse signal; and a transmission buffer configured to transmit the branch pulse signal to which the predetermined delay time was added to the transmission source device via the transmission line.

Abstract: A clock frequency adjusting system is disclosed. The clock frequency adjusting system includes a sensing clock generating unit, a frequency-dividing unit and a controller. The frequency-dividing unit makes frequency of the sensing clock signal be divided by a frequency-dividing modulus and then outputs a clock calibration signal. The controller includes a period counter and a frequency adjusting unit. The period counter samples the clock calibration signal through the external clock signal so as to acquire a second count value. The frequency adjusting unit calculates a frequency difference data between the clock calibration signal and the predetermined clock signal according to the first count value and the second count value, and determines a number of adjustment according to the frequency difference data and a step adjusting frequency so as to output a clock adjusting signal to the sensing clock unit to adjust frequency of the sensing clock signal.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. The inputs to the QTF may be either single input, multiple outputs, or alternatively, multiple inputs, multiple outputs. Furthermore, the second state of either of the two QTF transformations may be either positive or negative. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications.

Abstract: A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

Abstract: A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.

Abstract: An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.

Abstract: Method of synchronizing clocks between a first reference clock and a second clock to be slaved on the frequency of the reference clock, the two sharing a common clock, this method comprising the following steps: calculation of the integer part of the timestamp using the reference clock and the common clock; generation of a system clock local to the reference clock; calculation of the phase shift between the system clock signal and the reference clock signal; calculation of the phase shift between the system clock signal and the common clock signal; calculation of the decimal part of the timestamp; sending of the decimal timestamp to the second clock; slaving of the second clock using the common clock and the timestamp received.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A clock data recovery circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract: A local skew detecting circuit for a semiconductor apparatus include a reference delay block located on the center of the semiconductor apparatus, the reference delay block being configured to receive a predetermined signal and generate a reference delay signal by delaying the predetermined signal by a delay time and a first timing detecting block located on one edge of the semiconductor apparatus, the first timing detecting block being configured to receive the predetermined signal, generate a first delay signal by delaying the predetermined signal by the delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an Onlx mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal is used to terminate the ForceSL and Onlx modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during Onlx exit, and resulting in faster DLL locking time.

Abstract: A method for synchronizing input sampling to desired phase angles of sinusoidal signals including determining a delay time period for converging a next sample point to a next desired phase angle based on a phase error value.

Abstract: Method of controlling the drifting of a low-frequency LFO circuit in a wheel unit of a tire pressure monitoring system, each wheel unit including temperature and pressure sensors in conjunction with a signal control circuit, the sensors being activated according to an LFO circuit time base integrated into the control circuit. An RF emission circuit of each wheel unit transmits data stored in a memory and an identifier of the unit to a central unit. The emission circuit is regulated by a high-precision clock. In each wheel unit, a variation between a measured temperature and a reference temperature is compared with a variation threshold and a drift between the periods of the time base of the LFO circuit and of the clock is determined. The drift is used to adjust the time base to the period of the clock if the temperature variation ?Ti is greater than this threshold ?T.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.

Abstract: The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: The present invention discloses a frequency synthesizer which includes: a PLL including an oscillator for generating an oscillator signal and a first frequency divider for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit for switching the PLL to either an open loop status or a closed loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result.

Abstract: A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods.

Abstract: The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Abstract: A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.

Abstract: In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.

Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

Abstract: Various embodiments of a delay locked loop circuit of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the delay locked loop circuit may include an input correction unit configured to correct a duty ratio of an input clock based on a duty control signal and generate a reference clock; a delay line configured to delay the reference clock by a delay time and generate a delay locked clock; an output correction unit configured to correct a duty ratio of the delay locked clock based on the duty control signal and generate a corrected clock; and a control signal generation unit configured to generate the duty control signal when a correction activation signal is enabled.

Abstract: Disclosed are apparatus and methodology subject matters for providing improved functionality of a meter in a 2-way communications arrangement, such as an Advanced Metering System (AMS) or Infrastructure (AMI). More particularly, the present technology relates to methodologies and apparatus for providing load sensing for utility meters which preferably are operable with remote disconnect features in an Advanced Metering Infrastructure (AMI) open operational framework. Meters per the present subject matter utilize a detection circuit, and separately utilize certain remote disconnect functionality. In particular, disconnect functionality is coupled with consideration of electric load information, such as load current as determined by the metering functionality.

Abstract: An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A signal synchronizing system includes comparison circuitry and control circuitry. The comparison circuitry compares a synchronizing signal with an input signal to generate a comparison result. The control circuitry adjusts the synchronizing signal into a range that is determined by the input signal, and controls the range according to the comparison result.

Abstract: A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2?. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.

Abstract: Method of controlling the drifting of a low-frequency LFO circuit in a wheel unit of a tire pressure monitoring system, each wheel unit including temperature and pressure sensors in conjunction with a signal control circuit, the sensors being activated according to an LFO circuit time base integrated into the control circuit. An RF emission circuit of each wheel unit transmits data stored in a memory and an identifier of the unit to a central unit. The emission circuit is regulated by a high-precision clock. In each wheel unit, a variation between a measured temperature and a reference temperature is compared with a variation threshold and a drift between the periods of the time base of the LFO circuit and of the clock is determined. The drift is used to adjust the time base to the period of the clock if the temperature variation ?Ti is greater than this threshold ?T.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.