Abstract: A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data.

Abstract: A power supply has a TRIAC dimmer, and an AC-DC converter connected to the TRIAC dimmer. The AC-DC converter has a power switch, a bleed switch, and a controller. The controller turns off the bleed switch in a first time duration and turns on the bleed switch in a second time duration. Magnitude of a current of the power switch in the first time duration is larger than magnitude of a current of the power switch in the second time duration. Magnitude of a current of the bleed switch in a third time duration within the second time duration is smaller than magnitude of a current of the bleed switch in a fourth time duration within the second time duration.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: Method of synchronising clocks between a first reference clock and a second clock to be slaved on the frequency of the reference clock, the two sharing a common clock, this method comprising the following steps: calculation of the integer part of the timestamp using the reference clock and the common clock; generation of a system clock local to the reference clock; calculation of the phase shift between the system clock signal and the reference clock signal; calculation of the phase shift between the system clock signal and the common clock signal; calculation of the decimal part of the timestamp; sending of the decimal timestamp to the second clock; slaving of the second clock using the common clock and the timestamp received.

Abstract: Various techniques are described for periodically performing a calibration routine to calibrate a low-power system clock within an implantable medical device (IMD) based on a high accuracy reference clock also included in the IMD. The system clock is powered continuously, and the reference clock is only powered on during the calibration routine. The techniques include determining a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles, and adjusting a trim value of the system clock to compensate for the clock error. Calibrating the system clock with a delta-sigma loop, for example, reduces the clock error over time. This allows accurate adjustment of the system clock to compensate for errors due to trim resolution, circuit noise and temperature.

Abstract: In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.

Abstract: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Abstract: Methods, devices, and computer programs described herein may segment a reference signal that corresponds to a non-degraded signal into a plurality of reference signal segments; generate filter coefficients based on each reference signal segment; and filter each reference signal segment with its corresponding generated filter coefficients. The methods, devices, and computer programs may also filter a degraded signal, which includes a delayed signal of the reference signal, with each of the generated filtering coefficients to produce a number of degraded signals equivalent to a number of the plurality of reference signal segments; perform time-wise alignment for each filtered degraded signal with respect to each corresponding filtered reference signal segment; and output a time offset based on the performing.

Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract: Systems and methods of clock generation for radio frequency receiver. In radio frequency receiver, the system requires accurate local oscillating (LO) signal and system clocks for proper operation and to ensure high quality performance. In order to achieve accurate LO frequency and system clock, a crystal or and accurate reference clock is provide to the clock generation circuit. How a low-cost receiver, it is desirable to eliminate the requirement for a crystal or an accurate reference clock. The present invention discloses systems and methods to utilize a pilot signal embedded in the transmitted signal. The pilot signal usually has very accurate frequency which is particular true for broadcast system such as FM broadcast. In various embodiments of the present invention, the systems and methods measure the relation between the frequency of the pilot signal and the current clock generated.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract: A signal processing device includes: a wiring unit including a plurality of signal input terminals, wirings extending from the signal input terminals, and a wiring concentration section on which the wirings are concentrated; a plurality of electronic circuit units, each including a device that outputs a signal, an output control section that controls a timing at which the device outputs the signal, and a signal output terminal coupled to the signal input terminal; and a control unit that supplies a reference timing signal to the plurality of electronic circuit units, wherein each of the output control section controls a timing at which the signal is output based on the reference timing signal and phase difference information indicative of a phase difference between the signal and the reference timing signal.

Abstract: A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plurality of data signals is changed.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermined delay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: A method, apparatus and system for correcting different clock domains are disclosed. The disclosed implementations correct a second clock domain by making reference to a resampling filter, or similar device, used to correct a first clock domain. The implementations thereby facilitate clock correction using fewer or a different variety of elements.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source includes of a controllable digital fractional divider receiving a control value from digital comparator and a clock input from a digital clock synthesizer driven by a fixed oscillator.

Abstract: PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.

Abstract: Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.

Abstract: An integrated circuit audio processor having an internal-oscillator generated intermediate frequency reference provides for operation of an audio processor without requiring an external master clock. Input audio streams are sample-rate converted to an intermediate sample rate derived from the internal oscillator, which may be an LC oscillator. One or more output audio streams are generated from the one or more input audio streams at the intermediate sample rate and are converted from the intermediate sample rate to corresponding output sample rates. A divider generates the intermediate sample rate from the oscillator output, and is programmed to control the intermediate sample rate to ensure that the intermediate sample rate is in the proper range for operation of the integrated circuit. The divider can be programmed to accommodate changes in process, voltage and/or temperature of the IC, so that the intermediate sample rate is maintained near an expected frequency.

Abstract: Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

Abstract: A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.

Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.

Abstract: A clock generating apparatus has an integral ratio divider for, according to frequency-dividing parameters for generating a second clock signal including a second frequency by using a first clock signal including a first frequency, outputting the second clock signal, and a frequency-dividing parameter generating portion for comparing program clock reference inputted from outside with an STC value based on the second clock signal and outputting the frequency-dividing parameters so as to converge a discrepancy between the program clock reference and the STC value within a predetermined range, and wherein the frequency-dividing parameter generating portion generates new frequency-dividing parameters each time the program clock reference is inputted from outside.

Abstract: An apparatus for generating an audio output clock is disclosed. The apparatus at least includes a plurality of dividers and a frequency synthesizer. The apparatus utilizes the dividers to achieve dispersive frequency-division operations such that the anti-noise ability of the apparatus can be improved. In addition, the apparatus also utilizes dynamic phase adjustment to increase accuracy of the frequency of the audio output clock.

Abstract: A load drive device for driving an inductive load by PWM controlling a switching element includes synchronization control unit, a synchronization signal input terminal, and a synchronization signal output terminal. The synchronization control unit outputs the PWM signal to the switching element. The synchronization control unit receives a synchronization signal through the input terminal from an exterior. The synchronization control unit outputs the synchronization signal through the output terminal to an exterior. When the synchronization control unit does not receive the synchronization signal, the synchronization control unit outputs the synchronization signal such that a first switching period of the PWM signal is prevented from overlapping with a second switching period of a PWM signal of an external device. When the synchronization control unit receives the synchronization signal, the synchronization control unit generates the PWM signal based on the synchronization signal.

Abstract: A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such.

Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.

Abstract: A clock generating apparatus for use in an electronic device, such as a radio or other audio device, which generates a clock signal based on an AC input signal received, for example, from a wall outlet. The clock generating apparatus detects and monitors the frequency of the AC input signal and automatically adjusts the clock signal based on the detected frequency of the AC input signal.

Abstract: A control device for controlling a switch unit of a resonant direct current/direct current converter includes a frequency modulation controller and a pulse selector. The frequency modulation controller is adapted to be coupled electrically to the converter for receiving a correcting threshold value and output information of the converter, and for generating a synchronization signal according to the correcting threshold value and the output information received thereby. The pulse selector is adapted to be coupled electrically to the converter and the frequency modulation controller for receiving the correcting threshold value, the output information and the synchronization signal, and for generating a driving signal according to the correcting threshold value, the output information and the synchronization signal received thereby. The driving signal is adapted to drive the switch unit and has a working period.

Abstract: In a memory area having portions of predictable access frequency, such as in a memory area of a real time clock unit, a synchronous design may be implemented by associating storage cells of identical access frequency with a clock gating mechanism, thereby reducing power consumption. Hence, the synchronous design of the real time clock unit may provide reduced implementation effort and enhanced verification capability.

Abstract: A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay circuit itself or caused by a load variation of a power supply. The consumption current balance circuit includes a delay circuit for giving a delay time to a timing pulse signal, a compensation circuit for interpolating the consumption current of the delay circuit, a ring oscillator provided in the same power supply area as the delay circuit; an output period counter for measuring the output period of the ring oscillator; and a heater circuit current amount adjusting circuit for adjusting the current amount of the heater circuit to minimize the difference in the output period between the stand-by state and the active state of the ring oscillator.

Abstract: Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced.

Abstract: Timebase variation compensation in a measurement instrument is achieved by simultaneously acquiring both a signal under test and a reference signal. The reference signal is derived from a source that has very stable timing with respect to the timebase. Timing variations are measured from the acquired signals. Timing variations detected in the reference signal are deemed to reflect variations in the timebase of the test and measurement instrument. The timing variations in the reference signal are used to detect, and compensate for, timebase variation in the signal under test to produce a corrected signal under test that reflects the actual timing variations present in the signal under test.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency.

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.

Abstract: System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common reference. Each device is configured to transmit respective signals to the STM within a common clock cycle. Respective delays corresponding to the devices are determined based on the respective transmission times, where the respective delays are applicable to respective signals received from the devices to synchronize received corresponding pulses in the signals to within a common clock cycle. The respective delays are applied to respective signals received from the plurality of devices to synchronize received corresponding pulses in the signals to within the common clock cycle, after which the STM is operable to trigger the devices as a single device.

Abstract: Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.