Abstract: A device for generating a clock signal includes: a timer unit for generating a period signal that indicates a period defined on the basis of a reference clock and a period control signal; an output unit for reversing an output level thereof in response to the period signal generated by the timer unit and providing a resultant output as a clock signal; and a control unit for producing the period control signal according to the clock signal output from the output unit and controlling the timing of generation of the period signal for the timer unit. A cycle of the clock signal output from the output unit is controlled using the period control signal, so that the cycle corresponds to an odd number of pulse spacings of the reference clock. Owing to this configuration, a deviation of an actual output frequency from a desired output frequency relative to an identical input clock can be minimized, and thus a high-precision output clock can be provided.

Abstract: A communications controller coupled to a synchronous network generates local clock reference signals from network clock signals. The network clock signals are used to transport data over the network at a constant rate. The controller receiving a bit stream while generating the local clock reference signals. The bit stream including program clock reference signals, the program clock reference signals being independent of the network clock signals. The program clock reference signals are extracted from the bit stream and compared, after normalization, with the local clock reference signals. If the program clock reference signals are, time-wise, in advance of the local clock reference signals, transport of the bit stream is suspended, otherwise the bit steam is transported over the network. While transport of the bit stream is suspended, data from an alternative bit stream can be transported.

Abstract: A frequency synchronous circuit has a first selection unit, a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first selection unit is used to select one sampling signal from a first sampling signal having a first sampling time and a second sampling signal having a second sampling time shorter than the first sampling time. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during the sampling time of the selected one sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the selected one sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit.

Abstract: A frequency synchronous circuit has a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during a sampling time which is defined by a sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal of the storage/average unit with an output signal of the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit.

Abstract: A data synchronizer (10) for synchronizing data generated by a data source (16) at a first rate includes a first timer (22) for generating a first timing signal at the first rate. A first register (20) connected to the first timer (22) has an input connected to the data source (16). The first register (20) temporarily stores multi-bit data words from the date source (16). A second timer (26) generates a second timing signal at the second rate. A second register (24) connected to the second timer (26) has an input connected to an output of the first register (20). The second register (24) temporarily stores multi-bit data words from the first register (20). A synchronizer connected to the first and second timers (22, 26) generates a good data signal when the multi-bit data words from the first register (20) is available at an output of the second register (24).

Abstract: A sensor circuit is disclosed for use with a clock circuit providing a periodic timing signal to a clock output, wherein a timing reference for the periodic timing signal is provided by a crystal connected between a crystal input and a crystal output of the clock circuit, or alternatively provided by an external periodic logic signal coupled to the crystal input. The sensor circuit provides a sensor output in a first state, thereby indicating the presence of an external periodic logic signal timing reference, in response to at least a given number of large-signal voltage transitions on the crystal input within a certain period of time, and otherwise provides a second state on the sensor output, typically to indicate the presence of a crystal timing reference. Also disclosed is a clock circuit including a sensor circuit, and further including means for disabling a feedback resistor necessary for crystal operation when the timing reference is determined to be provided by an external periodic logic signal.