Abstract: A phase-locked loop circuit having a frequency dividing circuit which is reset in response to a reset signal. The reset signal is generated by a first frequency divided signal generated by dividing the frequency of a reference clock signal and an output signal from a voltage controlled oscillator. The phase-locked loop circuit adjusts rapidly the frequency and the phase of the output signal of the voltage controlled oscillator to correspond to that of the reference clock signal.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input buffers of both the address path and the clock path include input buffer cells configured to reduce timing delay differences caused by process variations while minimizing current leakage. An exemplary input buffer cell described herein includes a first inverter stage with a pair of NMOS devices connected in series with a PMOS device and a second inverter stage having an additional PMOS device connected along a feedback path around an inverter. The PMOS device along the feedback path operates to assist the pair of NMOS devices to pull a voltage input to the inverter to a high logic state, when an input to the cell is held low, to prevent leakage current through the inverter.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples.

Abstract: An analog mixed digital DLL includes a digital mode controller and an analog mode controller. The digital mode controller compares phases of delay clock signals outputted from a plurality of delay blocks and a first clock signal, detects an initial locking point, selects one delay clock signal at the detected initial locking point and controls the operation of the delay clocks. The analog mode controller compares the phase of the delay clock signal selected by the digital mode controller and the phase of a first clock signal. The analog mixed digital DLL can provide an externally inputted first control voltage or a second control voltage to the delay blocks in accordance with the digital and analog operation modes and implements a wide band frequency operation, has a short duration of jitters, prevents a multi-locking during a wide band frequency operation and decreases a current consumption.

Abstract: Digital circuitry synchronizes clock signals in a digital circuit. A value of a reference clock is sampled at a plurality of points near a transition point of a generated clock. It is determined whether the reference clock transitioned from a first state to a second state before, after or within an acceptable range of a transition point of the generated clock. Upon determining that the reference clock transitioned before the transition point of the generated clock, one period of the generated clock is shortened. Upon determining that the reference clock transitioned after the transition point of the generated clock, one period of the generated clock is lengthened.

Abstract: The present invention relates to an electro-optic sampling oscilloscope which carries out measurement of a measured signal using an optical pulse generated based on a timing signal from a timing generation circuit. The timing generation circuit includes a frequency measurement circuit which generates a gate signal for a gate interval which is a specified multiple N of the cycle of the desired sampling rate, and counts the input trigger signals during the gate interval of the gate signal; a division circuit which divides the count value of said frequency measurement circuit by the specified multiple N, and determines a divider ratio; and a frequency divider which divides the trigger signals by the divider ratio determined by the division circuit, and outputs the result as the timing signal.

Abstract: A motor rotational pulse generating circuit for a motor is provided which generates a correct pulse signal even at an initial turning-on stage of the motor, by adjusting a filter cutoff frequency in response to motor rotational condition. The motor rotational pulse generating circuit includes a rotational pulse generation circuit 20 which generates ripple pulses based on a signal being inputted from the DC motor 1, in which a ripple is superposed whose frequency is in proportion to a rotation number of the DC motor 1. A filter 3 makes a cutoff frequency variable on the basis of a clock signal issued from a PLL circuit 6. An oscillation frequency at an oscillator VCO10 is determined by the ripple pulses and a motor rotation condition signal inputted by way of circuits 12 to 16 inclusive. A microcomputer 20 operates, when the motor is turned on, to cause the oscillator VCO10 to issue a preliminary clock signal.

Abstract: A technique controls a charge pump bias circuit in a phase-locked loop (PLL) circuit. The charge pump bias circuit biases a charge pump circuit. A digital phase detector generates direction control signals based on reference and pre-scale count signals from reference and pre-scale counting circuits, respectively. The direction control signals control direction of current pumped by the charge pump circuit. A charge pump enable generator generates an enable signal based on look-ahead reference and pre-scale count signals from the reference and pre-scale counting circuits, respectively. The look-ahead reference and pre-scale count signals are generated before the corresponding reference and pre-scale count signals by a predetermined time interval. The enable signal powers down the charge pump bias circuit after the charge pump circuit pumps the current.

Abstract: The present invention is directed to an improved PLL which produces an output signal that is in-phase with a reference clock input despite switching of the reference clock. A quadrature signal is generated using a quadrature decoder having a counter, a state decoder and a flip flop. A local oscillator having a local clock output having a frequency which is a multiple of the reference clock frequency is provided. The local clock output is divided down with a binary counter to match the reference signal frequency. The counter state is decoded using an AND in combination with a flip flop. The divided clock output is then re-synchronized with the reference clock using the local clock output coupled to the clock input of the flip flop. The output of the flip flop is an quadrature copy of the reference clock, and this quadrature signal is fed back to the phase detector.

Abstract: A data/strobe output buffer performs data output according to an outputting internal dock signal DLLCLK from a DLL (Delayed Locked Loop) circuit and an output enable signal. During a time period for a data reading operation including a time period in which the output enable signal is in an active state, a control circuit suspends a phase adjusting operation of the clock signal DLLCLK in the DLL circuit. Thus, occurrence of edge-to-edge jitter in the internal clock signal defining the timing of data output can be suppressed.

Abstract: A system and method for preventing time-walking in a digital switching network when switching from a first clock to a second clock. The first and second clock can be identical in frequency and independent in phase, where the highest resolution frequency available is that of said first and second clock. The system can include a clock divider selection circuit, an enhanced digital phase aligner, and a clock select control circuit. The clock divider selection circuit can output an on-line divided clock and an off-line clock to the enhanced digital phase aligner. The enhanced digital phase aligner can sample the on-line divided clock with four phases of the off-line clock and output an off-line divided clock which is time shifted such that the off-line divided clock is in phase with the on-line divided clock within plus or minus one-half the clock period of the off-line clock.

Abstract: A data line driving circuit comprises a shift register for sequentially generating sampling pulses according to a clock pulse, a buffer connected to each stage of the shift register, and a sampling switch for sampling a data signal according to the sampling pulse outputted from the buffer. The buffer is provided with a logic gate for synchronizing the output of the shift register with the clock signal.

Abstract: A signal production circuit for producing a control signal used in a driving and controlling circuit of a display device externally input to the driving and controlling circuit, using an external interface signal. There is a vertical synchronization signal having a predetermined frequency and a reference clock signal in synchronization with the vertical synchronization signal. The signal production circuit includes: a first counter circuit for counting a number of reference clock signal pulses up to a value of a parameter which is preset based on a time interval of one cycle of the vertical synchronization signal and a predetermined target period.

Abstract: A phase-locked loop circuit with dynamic backup is disclosed. The phase-locked loop circuit with dynamic backup includes a phase comparator, a lowpass filter, a voltage-controlled oscillator, and a detection circuit. The phase comparator compares an input reference signal and a feedback output signal from an output of the phase-locked loop circuit for generating a voltage signal representing the phase difference between the input reference signal and the feedback output signal. After the voltage signal is filtered by the lowpass filter, the filtered voltage signal is sent to the voltage-controlled oscillator for generating the feedback output signal. Coupled to the phase comparator, the detection circuit detects whether or not the phase-locked loop circuit is in lock with the input reference signal.

Abstract: A stable and flexible phase locked loop system and method are disclosed. The system comprises a first phase frequency detector for detecting a difference between an internal clock signal and an external clock signal, and for generating a first control signal representing the difference. A first voltage controlled oscillator coupled to the first phase detector generates a first timing signal based on the first control signal. A first divider circuit coupled to the first voltage controlled oscillator divides the first timing signal by a first predetermined number to provide an output signal. A second phase frequency detector detects a difference between the first timing signal and a second timing signal, to generate a second control signal representing the difference. A second voltage controlled oscillator coupled to said second phase detector generates a third timing signal based on the second control signal.

Abstract: A semiconductor memory device having a delay locked loop includes a delay locked loop and a voltage supply unit. The delay locked loop reduces the skew between a clock and data. The voltage supply unit supplies the voltages required by the delay locked loop when the delay locked loop is operating and is deactivated when the delay locked loop is not operating.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to be a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuitry discriminates between valid input signals and spurious signals or noise. Further, the programmable device includes circuitry for suspending a clock signal. In one embodiment, input signal having at least a minimum duration is received and used to generate an asynchronous logic derived clock signal.

Abstract: A clock generating system used to generate a clock signal which compensates for chip operating conditions. The system includes a delay line oscillator and a reference clock which determines the actual propagation time of delay elements on the chip. A clock generator which includes a number of serially connected delay units uses this information to generate a clock signal for the chip logic functions. The output clock rums the chip logic functions at the proper frequency for the current chip conditions.

Abstract: A trap and delay pulse generator for command signals triggered off of a high speed clock allows a device to develop signals before initiating a function and to complete the function after the clock pulse expires and allows overlap of sequential functions. When a device receives a sequence of clock pulses triggering command signals it is necessary that the device complete the functions after the clock pulse expires before receiving a new command signal triggered off of a subsequent clock pulse. The trap and delay pulse generator latches the command signal triggered off of the clock pulse and delays it to ensure an operation is ready to proceed even if the clock signal expires before the present command is completed.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input buffers of both the address path and the clock path include input buffer cells configured to reduce timing delay differences caused by process variations while minimizing current leakage. An exemplary input buffer cell described herein includes a first inverter stage with a pair of NMOS devices connected in series with a PMOS device and a second inverter stage having an additional PMOS device connected along a feedback path around an inverter. The PMOS device along the feedback path operates to assist the pair of NMOS devices to pull a voltage input to the inverter to a high logic state, when an input to the cell is held low, to prevent leakage current through the inverter.

Abstract: A phase-locked-loop-stabilized voltage controlled oscillator relies on a sampling of the analog-frequency-control voltage of a voltage-controlled oscillator in a phase-locked-loop circuit to act as a reference voltage for a second free-running voltage-controlled oscillator. A vernier-adjustment voltage is injected into the control input of the second voltage-controlled oscillator to produce a finely variable derivative frequency not otherwise producible by a conventional phase-locked-loop circuit.

Abstract: A frequency multiplying circuit includes a plurality of frequency multipliers in a series array. The multiplying ratio of the initial stage frequency multiplier is the greatest compared with the remaining frequency multiplier or multipliers. Further, at least one of the frequency multipliers uses a voltage controlled delay circuit.

Abstract: A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional "high" and "low" levels normally available.

Abstract: In an high-frequency LSI chip, a clock signal generating circuit establishes accurate synchronization between an input clock signal and an internal clock signal to prevent an input circuit from causing a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting in amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thus, the influences of a delay caused by the input circuit, which would not be avoided in the prior art, can be avoided and the accurate internal clock signal can be generated.

Abstract: A synchronous clock regeneration system is implemented in a modem to enable the generation of a clock waveform at the same frequency as that of the transmitting device. The synchronous clock regeneration system receives an error signal indicating the timing difference in the receiving modem and the remote modem. The value in the error signal is added to a value in an offset integrator which integrates all of the error signals produced in a given transmission. The data is then relayed to a modulo subtractor which subtracts a predetermined value from the data if the value of the data is greater than the predetermined value. The data is then introduced to the offset integrator for integration and to a waveform generator. The waveform generator uses the data to offset a supply waveform an appropriate amount to match the frequency of the remote modem. As a result, the waveform generator produces a waveform that synchronously and smoothly tracks the clock waveform generated by the remote modem.

Abstract: In the present invention, when a phase comparison circuit, which compares the phase of a reference clock divided by a frequency divider that frequency divides a supplied clock, to that of a variable clock, detects the phase-matching of the two clocks, it generates a phase synchronization detection signal, and this phase synchronization detection signal increases the frequency division ratio of a frequency divider, lowering the frequency of operation of the phase comparator. The present invention is further characterized in that, at reset, when an inactive state becomes an active state, the time required to phase synchronize both clocks is shortened by resetting the above-described phase synchronization detection signal, thereby setting the frequency division ratio of the frequency divider to its original low state, and the frequency of operation of the phase comparator to its original high state.

Abstract: Phase locked loops include a controlled oscillator that is responsive to a control signal, to generate an output signal, the frequency of which is a function of the control signal. A phase detector is responsive to a reference frequency input signal and to the output signal, to produce an error signal. A loop filter filters the error signal, to thereby produce the control signal. A bandpass filter is responsive to the error signal, to produce a filtered error signal at twice the frequency of the reference frequency, and an envelope detector is responsive to the filtered error signal to sense the amplitude of the filtered error signal. A variable attenuation circuit is responsive to the envelope detector output, to variably attenuate a phase locked loop input signal based on the amplitude of the filtered error signal, and thereby produce the reference frequency input signal.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal.

Abstract: A programmable device includes means for generating an asynchronous logic derived clock signal from one or more of a plurality input signals. Means for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the means for generating the asynchronous logic derived clock signal. The means for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to be a reference clock signal are coupled to the circuitry for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuits discriminate between valid input signals and spurious signals or noise.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Further circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the generating circuitry. The synchronizing circuit generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal.

Abstract: In a computer or other digital system a double side band suppressed carrier (DSB-SC) signal is derived from a clock or other synchronous signal. The clock or other synchronous signal is amplitude modulated at a source using a broadband low frequency envelope signal. The modulated signal is the DSB-SC signal, which then serves as a clock or other synchronous signal for the source and/or a destination circuit.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices.

Abstract: In a computer or other digital system a clock or other synchronous signal is routed from a source to a destination as a double side band suppressed carrier (DSB-SC) signal. The clock or other synchronous signal is amplitude modulated at the source using a broadband low frequency envelope signal. The modulated signal is the DSB-SC signal, which then is routed over PC board traces to the destination. At the destination, the DSB-SC signal is demodulated to achieve the clock or other synchronous signal.

Abstract: Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11.

Abstract: A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated circuit switching regulators operating at much lower frequencies. The circuitry provides three switch drive currents: a first (nominal) current that is provided while the switch is off in order to conserve power; a second (boosted) current, provided while the switch is transitioning from off to on in order to increase the speed at which the switching element switches on; and a third (drive) current, provided after the switch has turned on for maintaining the switch at a desired point in saturation. The drive current, additionally, varies as a function of the load on the switch in order, again, to conserve power. Additional circuitry increases the speed at which the switch turns off, by momentarily boosting base discharge current during the on-to-off transition period of the switch.

Abstract: A variable delay circuit is disclosed comprising first and second clock delay sections, first and second phase comparison circuits, first and second data delay sections, and a selector. The first and second clock delay sections delay a clock signal to generate first and second delayed clock signals. The first and second phase comparison circuits respectively detect a phase difference between the clock signal and the first delayed clock signal and a phase difference between the clock signal and the second delayed clock signal. The first and second phase comparison circuits then respectively supply first and second delay control signals indicating the phase differences to the first and second clock delay sections so as to equalize the delay times of the clock delay sections to a period of the clock signal. The first and second data delay circuits delay a data signal.

Abstract: A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.

Abstract: A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock.

Abstract: A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable.

Abstract: In a data transfer system for use in an integrated circuit, a data output circuit comprises a D-FF for latching data to be transferred, in synchronism with an external clock signal, an output buffer receiving and outputting the data latched in the D-FF, and another output buffer receiving the external clock signal for outputting a delayed clock signal which is delayed from the external clock signal by a delay amount of the D-FF. On the other hand, a data input circuit including a first D-FF for receiving the data to be transferred outputted from the D-FF of the data output circuit, in synchronism with the delayed clock signal supplied from the D-FF of the data output circuit, and a second D-FF for fetching the data received in the first D-FF, in synchronism with the external clock signal.

Abstract: The circuit for clock signal extraction from a high speed data stream which allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit has a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.

Abstract: A relay control circuit that includes a zero cross detector, a latch, and a delay circuit. The zero cross detector circuit detects when the voltage waveform or current waveform on an AC power line is at the zero crossing. The output of the zero cross detector clocks the latch (flip-flop), which receives a control signal at its data input. The flip-flop latches the control signal on the zero crossing point and outputs the latched signal to the delay circuit. The delay circuit delays the control signal for a predetermined time period depending on the make and break times of the relay so that the relay is switched ON and OFF substantially near the next zero crossing point of the AC voltage waveform.

Abstract: In a power supply monitor which outputs a reset signal when the power supply voltage decreases, a first voltage is generated by a first voltage generator in proportion to a power supply voltage, and a comparator supplying a first signal when the first voltage becomes lower than a reference voltage. On the other hand, a slewing rate detector supplies a second signal when a slewing rate of decreasing in power supply voltage is larger than a threshold value. Then, a signal generator supplying a signal set by a trailing edge of the second signal received from the slewing rate detector except a period after the second signal is received and reset by a trailing edge of the first signal received from the comparator. That is, even if the power supply voltage decreases, the monitor does not generate a reset signal when the decrease in the power supply voltage is instantaneous.

Abstract: A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively.

Abstract: Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11.

Abstract: A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator.