Abstract: A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.

Abstract: A pulse width modulation (PWM) frequency converter converts an input PWM signal to an output PWM signal having a different frequency while maintaining a substantially equal duty ratio. The PWM frequency converter samples the input PWM signal for a PWM cycle using a sampling clock. A filter module filters the resulting set of one or more PWM parameters to compensate for noise introduced by potential clock mismatch, clock jitter, ambient variations, and other non-deterministic issues, thereby generating filtered PWM parameters. The sampling employed by the filter module compares a difference between the one or more current PWM parameters and previous (or historical) PWM parameters from an earlier sampled PWM cycle to a predetermined change threshold in determining a filtered set of one or more PWM parameters. The filtered set of one or more PWM parameters then is used to generate one or more corresponding PWM cycles of the output signal.

Abstract: The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first and second differential pairs each differentially receiving input signals, a load element pair connected between output pairs of the first and second differential pairs and a power supply, and a current source stage that supplies respective driving currents to the first and second differential pairs.

Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: A method of generating a MPWM signal for a portable device such as a cellular telephone. For a first duty cycle that includes a MPWM frequency having N magnitude levels, the method generates a first waveform comprising a first and a second On pulse during a first MPWM frequency period. The first and second On pulses are separated by an Off period.

Abstract: One embodiment provides a system for generating a reference waveform. The system can include a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency. A second PWM channel is configured to provide a second PWM waveform having a second duty cycle and the first frequency. Combinational logic is configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.

Abstract: A pulse signal generator includes a period setting unit that receives a period set signal including an information indicative of a pulse period, and that outputs a period control signal controlling the pulse period, a duty ratio setting unit that receives a duty ratio set signal including an information indicative of a duty ratio of a pulse, that receives a signal including the pulse period set in the period setting unit, and that generates a duty ratio control signal controlling the duty ratio of the pulse on a basis of the pulse period and the duty ratio set signal, and a pulse generation unit that generates a pulse signal including the pulse period and the duty ratio of the pulse on a basis of the period control signal and the duty ratio control signal.

Abstract: A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information.

Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process that generates a series of groups of PWM cycles that gradually transition from the original duty to the new duty. Each group includes a corresponding set of a predetermined number of PWM cycles that is repeated one or more times over a predetermined duration for the group. Each set has a certain proportion of PWM cycles having the new duty to PWM cycles having the original duty, whereby the proportion increases for each successive group of the series. This gradual transition in the PWM signal from the original duty to the new duty effectively provides an effective higher duty resolution for the PWM signal generator during the duty transition.

Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.

Abstract: A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.

Abstract: A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.

Abstract: A clock/data recovery circuit includes a data duty correction circuit which outputs corrected data by correcting the duty of input data in accordance with the level of a correction signal, a clock recovery circuit which generates a recovered clock in synchronism with the edge timing of the corrected data, a data decision circuit which performs data decision of the corrected data based on the recovered clock, and a data duty detection circuit which detects the duty of the corrected data based on the recovered clock and outputs the correction signal representing a duty correction amount to the data duty correction circuit.

Abstract: A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a first division clock. The clock delay unit is configured to delay the first division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second division clock. The duty cycle correction clock generation unit is configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first division clock and the second division clock. The duty cycle correction voltage generation unit is configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A communication apparatus including: a modulator which modulates a reference clock signal having a predetermined basic frequency and outputs a modulated clock signal whose value fluctuates at a first frequency with respect to the basic frequency; a PWM signal generator which generates a PWM signal at a second frequency, with the modulated clock signal being as an operation clock; a switching portion which outputs a signal by switching an analog signal on the basis of the PWM signal; a filter which passes a signal included in an output signal of the switching portion, a frequency of the passed signal being lower than a third frequency, and a setting portion which sets the first frequency and the second frequency such that a fourth frequency in which a duty value of the PWM signal fluctuates is higher than the third frequency and such that the first frequency is higher than the second frequency.

Abstract: A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.

Abstract: A drive circuit includes a duty cycle adjusting circuit that changes the duty cycle of a first signal; and a calculating circuit that with respect to signals that include the first signal for which the duty cycle has been adjusted and a second signal having a phase and amplitude that differ from that of the first signal, performs any one of subtracting one of the signals from the other signal and adding the signals.

Abstract: A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.

Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: A pulse width modulated (PWM) controller includes a triangle wave generation circuit generating a triangle wave signal to oscillate between an upper limit voltage and a lower limit voltage. The upper limit voltage and the lower limit voltage are adjustable in response to changes in the power supply voltage. A pulse generation circuit is coupled to the triangle wave generation circuit and a minimum duty cycle setting voltage, and is configured to generate a PWM pulse signal with a minimum duty cycle determined by the relative magnitude of the triangle wave signal and the minimum duty cycle reference voltage. In an embodiment, the minimum duty cycle is increased when the power supply voltage is lower than a predetermined reference voltage.

Abstract: A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

Abstract: Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

Abstract: A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.

Abstract: A semiconductor device which has a duty detection circuit that detects a duty error in an internal clock synchronized with an external clock and is capable of performing accurate duty measurement. A first capacitor is coupled to a first node and a first current source coupled to a second node. A first switch is coupled between the first and second nodes. A second switch is coupled between a voltage line and the first node and a third switch is coupled between the voltage line and the second node, the third switch being rendered conductive while the second switch is in a conductive state. A second current source is coupled to a third node, with a fourth switch coupled between the first and the third nodes. A fifth switch is coupled between the voltage line and the third node, the fifth switch being rendered conductive while the second switch is in the conductive state.

Abstract: A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data signal, and a duty comparator that generates the correction signal based on the third clock signal.

Abstract: In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.

Abstract: A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code.

Abstract: A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.

Abstract: Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.

Abstract: A CMOS phase interpolation system comprises a capacitive integration unit coupled to a charge node and a plurality of selectively enabled current source units operably coupled to the charge node. The current source units each include: a charging segment; a discharging segment; and, a switching segment operable responsive to at least one periodic reference signal to selectively couple the charging and discharging segments to the charge node for alternatively charging and discharging the capacitive integration unit therethrough. The current source units are selectively enabled in predetermined combinations to uniquely define an output waveform at the charge node. An output conditioning unit coupled to the charge node generates a recovered periodic signal based on the output waveform. In certain applications, a duty cycle correction unit coupled to feed back from the output node adaptively biases a charging segment current of each enabled current source unit, responsive to the recovered periodic signal.

Abstract: Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

Abstract: The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

Abstract: A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

Abstract: A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: A clock adjustment circuit includes: first and third switching elements to be in a conductive state when in-phase and reverse-phase clock signals in a high level are applied to input terminals, respectively; second and fourth switching elements whose input terminals are connected to output terminals of the first and third switching elements, respectively, which become in the conductive state when the in-phase and reverse-phase clock signals in a low level are applied to output terminal, respectively; first and second capacitor elements whose one terminal is connected to an output terminal of the first and third switching element, respectively; and a shift detection unit detecting potential difference between the output terminals of the first and third switching elements and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.

Abstract: A PWM controller applied to switch-type voltage regulator includes an error amplifier, a soft-start control circuit, a compensating load and a comparator. The error amplifier receives a reference voltage signal and a feedback voltage signal and outputs an error current signal according to the received feedback voltage signal and the reference voltage signal. The soft-start control circuit outputs a compensating current signal according to at least one soft-start control signal. The compensating load receives the error current signal and the compensating current signal, and outputs a compensating signal. The comparator receives a ramp signal and the compensating signal, and outputs a pulse width modulated (PWM) signal. When a supply voltage rises, the error amplifier is compensated with a preset soft-start compensating current to a circuit common ground VSS, so that the error signal slowly rises during the soft-start control process. Therefore, the function of soft-starting is effectuated.

Abstract: A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: A digital pulse width modulation device includes a counter, a first comparator and a second comparator, wherein the first and second comparators are connected in parallel with each other and in series with the counter. The counter is capable of sending a count signal to the first and second comparators simultaneously, starting a count when the counter receives a clock signal, and transmitting the count signal to the first and second comparators. If the first comparator receives a pulse duty width signal, the count of the count signal will generate a pulse output of the corresponding duty cycle. If the second comparator receives a total pulse duty length signal and the count of the count signal reaches a number of the total length, a clear signal will be outputted to the counter to reset the counter to zero, so as to achieve the effect of correcting the output pulse.

Abstract: A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.

Abstract: Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.

Abstract: A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.

Abstract: A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.

Abstract: A power converter control method and apparatus is disclosed. An example control circuit includes a clock signal generator coupled to generate a clock signal to control switching of a power switch to be coupled to the control circuit. A feedback circuit is coupled to receive a feedback signal which is representative of an output of a power converter during a duration of a feedback portion of an off time of the power switch. The feedback circuit is coupled to respond to the feedback signal to control the clock signal generator to regulate a ratio of the duration of the feedback portion of the off time of the power switch divided by a duration of a total power switch switching cycle period.