Abstract: Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

Abstract: A duty cycle correcting circuit includes a first duty ratio correcting unit that widens a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock. A second duty ratio correcting unit narrows the high-level period of the input clock in response to the detection signal, thereby correcting the duty ratio of the input clock to output a second corrected clock. A clock selecting unit selectively outputs the first corrected clock or the second corrected clock as an output clock in response to the detection signal. A duty ratio detecting unit detects a duty ratio of the output clock, thereby generating the detection signal.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: A circuit for outputting an amplified clock signal is disclosed. The circuit includes a first input terminal for inputting a first clock signal, a second input terminal for inputting a second clock signal, a first amplifier circuit for amplifying the first clock signal and outputting a first amplified clock signal at a first output terminal, and a second amplifier circuit for amplifying the second clock signal and outputting a second amplified clock signal at a second output terminal. The circuit additionally includes a level maintenance circuit connected to the first output terminal and the second output terminal. The circuit further includes an output circuit connected to the first output terminal and the second output terminal and configured to output a further amplified clock signal based on the first amplified clock signal and the second amplified clock signal. The level maintenance circuit is configured to reduce duty distortion in the further amplified clock signal.

Abstract: The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may be efficiently controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Abstract: Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: A digital electronic device is provided which comprises a digital clock deviation detecting means and a digital clock correcting means. The clock deviation detecting means is used to detect a deviation of a first clock signal of the electronic device and/or the duty cycle of the first clock signal. The clock correcting means is used to correct the first clock signal and/or the duty cycle of the first clock signal if the clock deviation detecting means has detected a deviation of the first clock signal and/or the duty cycle of the first clock signal. The clock correcting means comprises at least a first and second compensation path (P1, P2) for compensating deviations in the first clock signal and/or the duty cycle thereof, when the first clock signal passes through the first or second path. The first path (P1) does not induce a compensation and is selected if the clock deviation detecting means has not detected a deviation in the first clock signal.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal.

Abstract: There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.

Abstract: The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the state for a long time.

Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process that generates a series of groups of PWM cycles that gradually transition from the original duty to the new duty. Each group includes a corresponding set of a predetermined number of PWM cycles that is repeated one or more times over a predetermined duration for the group. Each set has a certain proportion of PWM cycles having the new duty to PWM cycles having the original duty, whereby the proportion increases for each successive group of the series. This gradual transition in the PWM signal from the original duty to the new duty effectively provides an effective higher duty resolution for the PWM signal generator during the duty transition.

Abstract: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.

Abstract: A duty cycle corrector includes a delay unit configured to adjust an input clock and an inverted input clock with a delay value controlled in response to one or more control signals and to generate a positive clock and a negative clock, and a duty detector configured to receive the positive clock and the negative clock, to detect duty ratios of the positive clock and the negative clock and to generate the one or more control signals.

Abstract: A duty correction circuit includes: a C-element including a first input and a second input; and an inverter connected to the second input of the C-element, wherein the C-element obtains an output of a logic “1” when both inputs are the logic “1”, obtains an output of a logic “0” when both inputs are the logic “0”, and maintains the output to a previous state in other conditions, and complementary clocks having a phase difference of an approximately half cycle are inputted to the first input of the C-element and the inverter respectively.

Abstract: A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output.

Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.

Abstract: An electroactive lens driver generates a variable root-mean-square drive voltage for controlling an electroactive lens by controlling the duty cycle of a modified square wave.

Abstract: A circuit for reducing popping sound comprises a waveform generator, a voltage accumulator, and a comparator. The waveform generator is configured for generating a periodic waveform, and the voltage accumulator is configured for generating an increased voltage. The comparator is configured for comparing the periodic waveform with the increased voltage for generating a successive pulse signal. A percentage of a duty cycle in the successive pulse signal is increased gradually.

Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: A duty correction circuit is provided which includes a level shifter receives complementary differential input signals having a duty ratio and controls levels of the differential input signals; a TrTf control circuit receives output signals of the level shifter and controls edge angles of the output signals; a waveform shaping circuit receives output signals of the TrTf control circuit and shapes waveforms of the output signals; a first common mode comparator extracts common modes of the output signals of the TrTf control circuit and compares the common modes; and a second common mode comparator extracts common modes of output signals of the waveform shaping circuit and compares the common modes. The level shifter controls the levels based on outputs of the first common mode comparator and the TrTf control circuit controls the edge angles based on outputs of the second common mode comparator.

Abstract: Provided are a duty cycle correction circuit and method for correcting a duty cycle, and a semiconductor device including the duty cycle correction circuit. The duty cycle correction circuit includes a code generator configured to generate a first and a second duty code for adjusting the duty cycle of a clock to a target duty cycle, and a duty cycle corrector including a plurality of inverter circuits connected in series and whose driving capabilities are adjusted in response to the first and second duty code, wherein the duty cycle corrector is configured to correct the duty cycle of the clock based on the driving capabilities of the inverter circuits and to output a corrected clock.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier.

Abstract: A pulse width modulated (PWM) controller has an input terminal for receiving a pulsed input signal having a first duty cycle, a power supply terminal for receiving a power supply voltage. a minimum duty cycle reference voltage signal, and a control circuit for providing a pulse-width-modulated (PWM) output signal having a second duty cycle related to the first duty cycle of the pulsed input signal. The PWM output control signal having a minimum duty cycle that is adjustable in response to a change in the power supply voltage. In an embodiment, the second duty cycle and the first duty cycle are correlated in a substantially linear relationship. In an embodiment, the PWM control circuit also has a triangle wave generation circuit for generating a triangle wave signal configured to oscillate between an upper limit voltage and a lower limit voltage, which are adjustable in response to a change in the power supply voltage.

Abstract: A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. One of several algorithms produce a specific predetermined sequence of pulses of varying width such that the voltage maintains maximally flat characteristics while the current delivered to the load from the system plant varies within a range bounded only by inductive element continuous conduction at the low power extreme and non-saturation of the inductor core at the high power extreme.

Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

Abstract: A signal processing device includes a correction circuit configured to correct the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1.

Abstract: A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.

Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and decreasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.

Abstract: A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

Abstract: The present invention intends to provide a semiconductor memory device including a delay locked loop (DLL) circuit capable of generating a duty-corrected delay locked clock. A semiconductor memory device includes: a DLL circuit for generating a delay locked clock through a delay locked operation; and a duty-correction circuit for correcting a duty ratio of the delay locked clock by using the delay locked clock and a divided clock generated by dividing the delay locked clock by an even value.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output.

Abstract: There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: Techniques and an apparatus for producing pulse width modulation (PWM) edges are described. A PWM controller circuit with a polyphase counter is described. The polyphase counter may comprise a plurality of counters. Each of the counters may be set to a specific initial count value. A polyphase decoder block with a plurality of sets of high/low decoders are coupled to outputs from the polyphase counter. A set/reset block with a plurality of set/reset logic elements is coupled to outputs from the polyphase decoder block. A serializer is coupled to outputs from the plurality of set/reset blocks to generate PWM edges. Multiple parallel phases of a PWM pulse may be created with the circuit. Using a polyphase counter and comparator to create multiple parallel phases may speed up the controller circuit and provide a finer tuning resolution.

Abstract: Closed-loop techniques for adjusting the duty cycle of a cyclical signal, e.g., a clock signal, to approach a target value. In an exemplary embodiment, a charge pump is coupled to a charge and sample module, which drives a de-skew circuit in a negative feedback loop. The charge and sample module couples the charge pump to the integration capacitor during two of four successive phases, and also couples the integration capacitor to sampling capacitors during the other two of the four successive phases. The voltages across the sampling capacitors may be used to control the de-skew circuit, which adjusts the duty cycle of a cyclical signal to be adjusted.

Abstract: An apparatus and method of providing a pulse width modulated signal that is responsive to a current are disclosed. A circuit according to aspects of the present invention includes a capacitor to convert a first current to a first voltage on the capacitor during a first time duration and to discharge a second current from the capacitor to change the first voltage to a second voltage during a second time duration. A comparator is also included and is coupled to an output of the capacitor to compare a voltage on the capacitor to a reference voltage during the second time duration to change a pulse width of a periodic output signal in response to an input current.

Abstract: A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: There is provided an apparatus for duty cycle correction. The apparatus for duty cycle correction comprises a moving sum unit performing a moving sum calculation with respect to the square-wave signal and outputting the moving sum signal subjected to moving sum calculation, a comparison unit comparing the moving sum signal with a predetermined threshold voltage, outputting a high signal or low signal, a mean value calculation unit calculating the mean value of an output signal outputted from the comparison unit, the output signal being included in a section having a period integer times greater than that of the square-wave signal, and a threshold voltage control unit comparing the mean value with a middle value, increasing the threshold voltage when the mean value is greater than the middle value, and decreasing the threshold voltage when the mean value is less than the middle value.

Abstract: A delay circuit with a delay equal to the percentage of the input pulse width is described. In one embodiment, the ratio of the discharge current to the charge-up current of a timing capacitor is used to determine the percentage of the input pulse width used for the output delay. In a first timing phase, the input pulse width is stored as a voltage on the timing capacitor. In a second timing phase, the output is delayed by a percentage of the input pulse width. In a third timing phase, the circuit is restored to the trip point to remove sensitivity to process variation or applied conditions variation such as voltage or temperature (P-V-T variation), and be ready for the next timing cycle.

Abstract: An open-loop switching amplifier achieves synchronous operation using a ring oscillator based upon a tapped delay line. A counter is clocked from the ring oscillator, periodically comparing incoming more significant data to the value of the counter to form a pulsewidth modulated output waveform. Modulating the effective width of the output waveform in incremental delay line taps is equivalent to incoming less significant data. This technique then effects time-period summation of coarse and fine resolution clocked data.