Abstract: Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: A switched mode power supply (SMPS) comprising a feedback unit, voltage feed forward (VFF) compensation signal generator and a transient detector. A VFF compensation signal is only applied to the output of the feedback unit when a transient is detected by the transient detector on the input voltage of the SMPS, thereby saving power and computation time.

Abstract: A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: A method for outputting an analog value at a PWM output of a driver for a power semiconductor. The method comprises converting the analog value to a PWM signal which has two signal levels and which is at a fixed PWM frequency. For an inactive state of a binary supplementary value the PWM signal is output at the PWM output. For an active value of the supplementary value the PWM signal is output together with a supplementary signal at the PWM output. The current signal level of the PWM signal and the respective other signal level are output alternately as a supplementary signal at a signal frequency greater than the PWM frequency.

Abstract: A circuit for correcting a duty-cycle comprises a duty-cycle adjuster for changing a duty-rate of an input clock signal according to a duty control signal; a duty-cycle detector for detecting a duty-rate of an output clock signal based on the input clock signal and the output clock signal from the duty-cycle adjuster; and an algorithm-based digital controller for performing an algorithm according to a duty-rate detection signal outputted from the duty-cycle detector to generate the duty control signal.

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract: Methods and apparatuses are provided for duty cycle correction of high-speed clock circuits. The apparatus includes a duty cycle interpolator receiving a clock source for providing a duty cycle corrected clock signal. The duty cycle corrected clock signal is filtered and compared to a reference signal, the result of which is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to the duty cycle interpolator for adjusting the duty cycle of the clock signal to provide the duty cycle corrected clock signal. The method includes filtering a duty cycle corrected clock signal to provide a filtered signal and comparing the filtered signal to a reference signal, the result of is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to a duty cycle interpolator for adjusting the duty cycle of a clock signal.

Abstract: A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal.

Abstract: An A/D converter circuit includes first to fourth pulse circulation circuits and first and second counters and configured to provide high conversion accuracy irrespective of a temperature change. The first pulse circulation circuit operates with a difference voltage of a specified voltage and an analog input voltage. The first counter outputs a difference of the number of pulse circulation in the first and the second pulse circulation circuits. The third pulse circulation circuit operates with a difference voltage of the specified voltage and a set voltage. The fourth pulse circulation circuit operates with the set voltage. The second counter outputs a difference of the number of pulse circulation in the third and the fourth pulse circulation circuits. When an output value of the second counter reaches a specified value, an output value of the first counter at that time is outputted as A/D conversion data.

Abstract: Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed.

Abstract: A pulse width modulation signal controlling apparatus including a signal pin, a core circuit, a setting judging circuit, a signal adjusting and selecting circuit, and a timer circuit is disclosed. The signal pin is connected to a setting device for receiving an external input signal. The setting judging circuit receives and compares a setting signal with a reference value to generate a setting judgment result. The signal adjusting and selecting circuit couples the signal pin to the setting judging circuit and adjusts the external input signal into the setting signal according to the setting device in a first state, and couples the signal pin to the core circuit in a second state. The timer circuit controls the state of the signal adjusting and selecting circuit, wherein the timer circuit sets the signal adjusting and selecting circuit in the first state during a predetermined time period.

Abstract: A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay.

Abstract: Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

Abstract: A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path.

Abstract: A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle.

Abstract: A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses.

Abstract: A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.

Abstract: A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.

Abstract: A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

Abstract: A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle.

Abstract: Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

Abstract: A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.

Abstract: A signal control device controls the period of a three-phase signal used to control a three-phase high-voltage converter. An arithmetic unit of the signal control device determines a timing for changing the period for each phase so that the period of the signal for a V phase or a W phase is changed at the point when the phase difference between a U phase and the V or W phase reaches a prescribed phase difference after the period of the signal for the U phase has been changed. A control unit performs control such that the signal period for each phase is changed at the timing determined by the arithmetic unit.

Abstract: A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

Abstract: Closed-loop techniques for adjusting the duty cycle of a cyclical signal, e.g., a clock signal, to approach a target value. In an exemplary embodiment, a charge pump is coupled to a charge and sample module, which drives a de-skew circuit in a negative feedback loop. The charge and sample module couples the charge pump to the integration capacitor during two of four successive phases, and also couples the integration capacitor to sampling capacitors during the other two of the four successive phases. The voltages across the sampling capacitors may be used to control the de-skew circuit, which adjusts the duty cycle of a cyclical signal to be adjusted.

Abstract: Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before-and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.

Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.

Abstract: An example controller for use in a power supply in accordance with the present teachings includes a drive signal generator, a jitter signal generator and a compensator signal generator. The drive signal generator is coupled to output a drive signal having a switching period and a duty ratio to control switching of a switch that is to be coupled to the controller. The jitter signal generator is coupled to provide a jitter signal, where the switching period of the drive signal varies in response to the jitter signal. The compensator signal generator is coupled to provide a compensator signal responsive to the jitter signal, where the duty ratio of the drive signal is varied in response to the compensator signal.

Abstract: A “quasi-master-time-base” circuit is used to periodically resynchronize the individual PWM generators to a know reference signal. This quasi-master-time-base will be at the lowest frequency relative to all of the PWM output frequencies, wherein all of the PWM output frequencies are at the same frequency or at an integer multiple frequency(ies) of the quasi-master frequency. This “quasi-master-time-base” circuit allows for minor timing errors due to user PWM configuration errors and/or update errors, and still yields stable PWM signal outputs that remain synchronized to each other.

Abstract: A clock adjustment circuit includes: first and third switching elements to be in a conductive state when in-phase and reverse-phase clock signals in a high level are applied to input terminals, respectively; second and fourth switching elements whose input terminals are connected to output terminals of the first and third switching elements, respectively, which become in the conductive state when the in-phase and reverse-phase clock signals in a low level are applied to output terminal, respectively; first and second capacitor elements whose one terminal is connected to an output terminal of the first and third switching element, respectively; and a shift detection unit detecting potential difference between the output terminals of the first and third switching elements and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.

Abstract: A buffer circuit includes an amplifier circuit amplifying a difference between an input signal and a reference signal, providing a branch current that varies with a duty cycle of the input signal, and outputting a preliminary output signal on the basis of the amplified difference. The buffer circuit also includes a charge pump circuit charging/discharging a control node in response to the branch current to provide a control signal. The buffer circuit also includes a driver circuit configured to control pull-up strength and pull-down strength for the preliminary output signal based on control signal to thereby correct the duty cycle of the preliminary output signal in relation to a target duty cycle.

Abstract: A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that i s connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

Abstract: A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: A control circuit includes a triangular wave generating circuit, a temperature sensing circuit, a first comparator, and a switching circuit. The triangular wave generating circuit outputs a triangular wave signal. The temperature sensing circuit senses a temperature surrounding a fan and outputs a temperature signal. A non-inverting terminal of the first comparator is connected to the triangular wave generating circuit. An inverting terminal of the first comparator is connected to the temperature sensing circuit. The first comparator compares the triangular wave signal with the temperature signal to output a control signal. The switching circuit is connected between a power supply and the fan. The switching circuit turns on or off according to the control signal.

Abstract: A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.

Abstract: Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

Abstract: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.

Abstract: A system and method for controlling an AC motor drive includes a control system programmed with an energy algorithm configured to optimize operation of the motor drive. Specifically, the control system receives input of an initial voltage-frequency command to the AC motor drive, receives a real-time output of the AC motor drive generated according to the initial voltage-frequency command, and determines a real-time value of a motor parameter based on the real-time output of the AC motor drive. The control system also inputs a plurality of modified voltage-frequency commands to the AC motor drive, determines the real-time value of the motor parameter corresponding to each of the plurality of modified voltage-frequency commands, and identifies an optimal value of the motor parameter based on the real-time values of the motor parameter.