Abstract: A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.

Abstract: Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

Abstract: A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.

Abstract: A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock.

Abstract: An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Abstract: A resistive divider circuit may be operatively coupled with a modulated resistor circuit, wherein the resistive divider circuit and the modulated resistor circuit for an effective resistor circuit providing an effective attenuation. A variable duty cycle signal modulates the modulated resistor circuit to control the effective attenuation.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

Abstract: Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

Abstract: A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

Abstract: In some embodiments, a differential amplifier with duty cycle correction is provided.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: A pulse width modulation circuit of the present invention changes a voltage of a charging circuit based on an input signal voltage and in synchronization with a first switching signal; changes, during a predetermined second period following a first period during which the voltage of the charging unit is changed, the voltage of the charging unit in an opposite direction to a direction in which the voltage is changed during the first period, based on a constant bias current; detects time starting from when the second period starts to when the voltage of the charging unit reaches a predetermined reference voltage; and generates, based on the detected time which is repeatedly output each time the first switching signal is output, a pulse signal having a pulse width of the time.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: A duty cycle generator for generating a duty cycle signal to a power converter is disclosed. The duty cycle generator includes a first inverter, a second inverter, a signal protection unit including an input terminal coupled to the duty cycle signal for generating a break pulse to generate a protected duty cycle signal, a comparator for comparing a triangle-wave signal with a comparison signal to generate a comparison result, a NOR gate for generating a reset signal according to the comparison result and the protected duty cycle signal, an SR-latch for outputting a turn-on signal according to the clock signal and the reset signal, and an AND gate for generating the duty cycle signal according to the inverted clock signal and the turn-on signal.

Abstract: A data channel circuit including an analog to digital converter, a timing loop control circuit, an interpolator circuit, and a deglitch circuit. The analog to digital converter is configured to convert an analog input signal into a corresponding digital signal in accordance with a reference clock signal received from a timing loop. The timing loop control circuit is configured to receive the digital signal from the analog to digital converter, and generate a first clock signal based on the digital signal. The interpolator circuit is configured to receive the first clock signal, and generate a second clock signal based on the first clock signal, and the first clock signal delayed by a predetermined phase delay. The second clock signal has first glitches. The deglitch circuit is configured to, based on the second clock signal, generate the reference clock signal. The reference clock signal does not include the first glitches.

Abstract: Multiple pulse width modulation (PWM) generators each have a separate phase offset counter creating a phase shift. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. A master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. Then, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals.

Abstract: A method and circuit for implementing low duty cycle distortion and low power differential to single ended level shifter, and a design structure on which the subject circuit resides are provided. The circuit includes an input differential amplifier providing positive and negative differential amplifier output signals coupled to an output amplifier providing a single ended output signal. The output amplifier amplifies and inverts the negative differential amplifier output signal. The output amplifier amplifies and superimposes the positive differential amplifier output signal with the amplified and inverted negative differential amplifier output signal, providing the single ended output signal with low duty cycle distortion.

Abstract: An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

Abstract: The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay.

Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Abstract: A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.

Abstract: A circuit is provided that includes summing circuit for comparing the PWM output signal to the PWM input signal and producing an increment signal if a value of the PWM input signal exceeds a corresponding value of the PWM output signal and producing a decrement signal if a value of the PWM input signal is less than a corresponding value of the PWM output signal. An integrator produces a duty cycle signal by producing an increase in value of the duty cycle signal in response to each increment signal and a decrease in value of the duty cycle signal in response to each decrement signal. A PWM generator produces the PWM output signal in response to the duty cycle signal to cause the duty cycle of the PWM output signal to equal the duty cycle of the PWM input signal with no loss of duty cycle resolution.

Abstract: Disclosed herein are a correction circuit for output duty of a Hall element, a Hall sensor, and a method of correcting the output duty of the Hall element. According to an exemplary embodiment of the present invention, the correction circuit includes an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal; a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; and a duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio.

Abstract: The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

Abstract: Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.

Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.

Abstract: A PWM duty cycle converter includes a PWM signal generator, a timing signal generator, a limit signal generator, and a duty cycle limiter. The PWM signal generator generates a first PWM signal by comparing a triangular carrier wave with a duty command from a signal source. The timing signal generator generates a timing signal synchronously with at least one of a maximum value and a minimum value of the amplitude of the carrier wave. The limit signal generator generates a limit signal in response to the timing signal. The limit signal sets at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal. The duty cycle limiter combines the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle.

Abstract: A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal.

Abstract: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

Abstract: Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.

Abstract: A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.

Abstract: A PWM signal for driving power transistors of a half-bridge of a converter is generated with the aid of a digital circuit, in which an internal reference value is compared to the counter content of a counting ramp. In this context, a logic state of the PWM signal depends upon whether the internal reference value is greater than the counter content of the counting ramp. After each comparison between the internal reference value and the counter content, an n-bit long data word dependent on the result of this comparison is output serially as PWM signal, n being greater than or equal to 2. The resolution of the PWM signal is thereby improved by the factor n in comparison to conventional systems, without markedly increasing the circuit expenditure.

Abstract: A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions.

Abstract: Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.

Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.

Abstract: A circuit for correcting a duty-cycle comprises a duty-cycle adjuster for changing a duty-rate of an input clock signal according to a duty control signal; a duty-cycle detector for detecting a duty-rate of an output clock signal based on the input clock signal and the output clock signal from the duty-cycle adjuster; and an algorithm-based digital controller for performing an algorithm according to a duty-rate detection signal outputted from the duty-cycle detector to generate the duty control signal.

Abstract: A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal.

Abstract: Systems and methods for improving the timing alignment of 25% duty cycle non-overlapping waveforms are provided. A representative system includes a waveform synthesizer that generates a plurality of 25% duty cycle input waveforms and inverters that receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates that receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates responsive to three inverted waveforms of the plurality of inverted waveforms being at logic “0”; and mixers having inputs that receive the pass-through waveform and a first radio frequency (RF) signal, wherein the mixers combine the pass-through waveform and the RF signal into an output signal.

Abstract: A controller for a switch and a method of operating the same. In one embodiment, the controller is configured to measure a voltage of a control terminal of the switch and select a first mode of operation if the voltage of the control terminal is greater than a threshold voltage, and a second mode of operation if the voltage of the control terminal is less than the threshold voltage.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.

Abstract: A delay circuit generates an internal clock signal or a second clock signal by delaying an external clock signal. A detection-potential generation circuit included in a phase-difference determination circuit generates a detection potential corresponding to a difference between a timing of an active edge of an internal clock signal or a third clock signal and a timing of the target external clock signal in a first node. A reference-potential generation circuit included in the phase-difference determination circuit generates a reference potential in a second node. A phase control circuit delays the second clock signal according to the detection potential. At this time, when the detection potential is higher than the reference potential, an adjustment amount of the second clock signal per adjustment changes.

Abstract: The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

Abstract: The present invention provides a switching device and a method for preventing malfunction of the same. The switching device includes: a controller for outputting a plurality of digital control signals; a protecting unit connected to the controller for protecting all signals when the plurality of digital control signals outputted from the controller are simultaneously received at a state of ON; a gate driver connected to the protecting unit for generating a switch control signal by converting the control signal passed through the protecting unit; and a plurality of switches connected to the gate driver for individually performing ON•OFF operations according to each of the switching control signals.

Abstract: A duty cycle controlling circuit for adjusting duty cycle of a target clock signal to a desired value, comprises: a first duty cycle adjusting cell, for receiving a first duty cycle control signal to adjust duty cycle of an input clock signal to generate a first output clock signal as the target clock signal; and a duty cycle detecting module, for generating the first duty cycle control signal according to the first output clock signal.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: Extending pulse width modulation phase offset when generating phase shifted groups of pulse width modulation (PWM) signals is accomplished with a separate phase counter that is independent of the time-base counters used in traditional PWM generation circuits and that is prevented from being retriggered until an existing duty cycle has completed. This is accomplished with a phase offset counter, a phase comparator and a circuit that is triggered via a master time base for overall synchronization of the multi-phase PWM signal generation.