Abstract: An internal clock signal generator of a synchronous memory device is provided. The internal clock signal generator includes first and second inverting portions, a delay portion, first and second switching portions, and first and second logic portions also called input and output logic circuits, respectively. The first inverting portion inverts an external clock signal. The second inverting portion inverts an output signal of the first inverting portion. The delay portion delays an output signal of the second inverting portion. The first switching portion gates an output signal of the delay portion in response to a first control signal. The second switching portion gates the output signal of the second inverting portion in response to a second control signal. The first or input logic portion performs a logic operation with respect to signals input from an external source and outputting the first and second control signals.

Abstract: An output circuit according to the present invention is provided with a delay circuit for delaying an enable control signal by a predetermined period td and an output means capable of controlling the output state in either an enable or a disable state, wherein the output state of the first output means so controlled as to be switched from the disable to the enable in accordance with the enable control signal and to be switched from the enable to the disable state gradually in accordance with the signal supplied from the first delay circuit.

Abstract: In order to use a digital oscillator to generate a target frequency ZT with a "high" or "low" level constant in time from a working clock by variable division by a first division factor, two divider circuits which can be respectively triggered by the positive or the negative edges of a working clock, and to which a control word can be directed alternately by means of a first controlled switch, and which are connected on their output sides to a second controlled switch to obtain a clock pulse. To that end each divider circuit has a logic module which detects the occurrence of the edge of the control word and stores this event, with this event triggering a division by a second division factor.

Abstract: A new nonlinear control technique that has one cycle response, does not need a resettable integrator in the control path, and has nearly constant switching frequency. It obtains one cycle response by forcing the error between the switched-variable and the control reference to zero each cycle, while the on-pulse of the controller is adjusted each cycle to ensure near constant switching frequency. The small switching frequency variation due to variations in the reference signal and supply voltage and delays in the circuit are quantified. Using double-edge modulation, the switching frequency variation is further reduced, thus the associated signal distortion is minimized. An experimental 0-20 kHz bandwidth, 95 Watt RMS power audio amplifier using the control method demonstrates the applicability of this control technique for high fidelity audio applications. The amplifier has a power supply ripple rejection (PSRR) of 63 dB at 120 Hz.

Abstract: A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

Abstract: A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.

Abstract: A compact structure of a pulse-width modulator is provided which includes a clock generator, a counter, a D/A converter, a comparator, and a latching circuit. The clock generator generates clock signals. The counter counts the clock signals and provides a count signal indicative thereof in a digital form. The D/A converter converts the count signal into an analog signal. The comparator compares the analog signal converted by said D/A converter with an input signal to be pulse-width modulated to provide an output indicative thereof. The latching circuit latches the output of the comparator in response to a latch signal shifted from a change in level of the count signal to provide a pulse-width modulated signal.

Abstract: A device includes a pulse-width-detection unit which detects pulse widths of an input signal supplied to the device, a pulse-width-information storing unit which stores the pulse widths detected by the pulse-width-detection unit, an operation unit which obtains indication information from the pulse widths stored in the pulse-width-information storing unit, and a pulse-generation unit which generates a pulse signal by delaying the input signal by a delay amount commensurate with the indication information, the pulse signal being supplied to an exterior of the device.

Abstract: A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed.

Abstract: An apparatus having an input node and an output node for generating a timing signal. The apparatus includes an enabling circuit, one or more inverters, and one or more capacitive elements. The enabling circuit generates a signal of a first state when one or both of the input node and the output node are of a second state, and generates a signal of the second state when both of the input node and the output node are of the first state. The first state and the second state represent two opposite logic states. The inverters generate opposite state outputs in responsive with their inputs. The inverters are connected in series with a first inverter being responsive to the enabling circuit and a last inverter for generating a signal for the output node. The capacitive elements are connected between a voltage source and one of the inputs of the inverters.

Abstract: A pulse generating circuit which has a first and a second delay circuit selectively operable as a delay circuit or a resetting circuit. The delay circuits each has a discharge transistor and a charge transistor in order to fix the potential on its associated node rapidly when operating as a resetting circuit. Even when short pulses are continuously input as an input signal by accident, the circuitry surely outputs a single pulse transitioning at the same time as the first change in the input signal and having a desired duration since the last change in the input signal.

Abstract: A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.

Abstract: A circuit and method for producing a train of pulse width modulated pulses (FIG. 2), the circuit comprising: pulse producing means (11-16) for receiving sample values at an update rate and for producing therefrom pulses whose widths are representative of the sample values, and repeater means (15) for causing the pulse producing means to produce a predetermined plurality of pulses, at an output rate which is an integral multiple of the update rate, for each said sample value, whereby the pulse train output frequency is greater than the sample value update frequency.

Abstract: A pulse width control IC circuit that greatly reduces price, increases packaging density,and improves reliability for switching power supply units, wherein the IC circuit is on a single chip and includes a main converter control section that controls the ON and OFF actions of a main switch outside the IC, an output MOSFET, and an auxiliary converter control section that controls the ON and OFF actions of the output MOSFET.

Abstract: The present invention provides a timing circuit for outputting a signal having an amplified pulse width when a signal having a normal pulse width is inputted thereto, characterized in that when glitch noise whose pulse width is small, is inputted to the timing circuit, a signal having a waveform corresponding to the pulse width thereof is outputted from the timing circuit. The timing circuit comprises a first delay circuit whose input is connected to an input terminal, a first NAND circuit having a first input terminal connected to the first delay circuit and a second input terminal connected to the input terminal, a second delay circuit whose input is connected to the output of the NAND circuit, an inverter whose input is connected to the input terminal, and a second NAND circuit having a first input terminal connected to the output of the second delay circuit and a second input terminal connected to the output of the inverter.

Abstract: An output buffer circuit for transferring a high speed signal between large scale integrated circuits includes a first inverter with first and second transistors of opposite conductivity type, a second inverter with third and fourth transistors of opposite conductivity type, and a switch circuit for controlling the gates of the first and second transistors in accordance with a test control signal so as to change a dividing power. The respective outputs of the first and second inverters are connected in common to an output signal having a predetermined signal level related to an input signal.

Abstract: An improved circuit for producing a pulse having a predetermined pulse width. The pulse width forming circuit includes a first delay element for receiving an input pulse and delaying the input pulse by a first delay time, an OR gate for receiving the input pulse at an input terminal and a first delayed pulse signal from the first delay element at another input terminal and adding the first delay time to a pulse width of the input pulse, a second delay element for receiving an output pulse of the OR gate and delaying the output pulse by a second delay time, and an AND gate for receiving the input pulse and a second delayed pulse signal from the second delay element for producing a pulse waveform having a predetermined pulse width whose starting edge corresponds to an end timing of the input pulse and whose stop edge corresponds to an end timing of the second delayed pulse signal.

Abstract: In a double-sided pulse width modulator, an amplifier has a first input connected to a first reference potential, a second input, and an output. A first bank of storage elements have a first terminal connected to the second input of the amplifier, and a second terminal. A first bank of switches have an output terminal connected to a second terminal of the storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of the modulator and a polarity control bit for a first value to be input into the input terminals. A feedback storage element is connected in parallel with a first timing switch between the second input of the amplifier and the output of the amplifier. A comparator has a first input connected to a second reference potential, a second input, a timing enable input, and an output. A second bank of storage elements have a first terminal connected to the second input of the comparator, and a second terminal.

Abstract: A clock generating circuit includes a clock generator and a cycle controller. The clock generator is coupled to receive a reference oscillating signal. The clock generator provides a clock signal responsive to the reference oscillating signal. The cycle controller is coupled to provide a cycle control signal to the clock generator. The clock generator stretches a cycle of the clock signal responsive to a first value of the cycle control signal.

Abstract: A pulse-width modulation signal generator having a pre-phase converter which includes N pre-delay circuits connected in cascade, and N main phase converters each of which includes M main delay circuits, where N and M are natural numbers greater than one, and N>M. The output of each of the N pre-phase circuits is supplied to one of the N main phase converters to generate phase converted clock signals used for generating a pulse-width modulation signal.

Abstract: A controllable one-shot circuit for use in a control unit of a memory circuit, for asserting a control signal with variable (and controllable) duration in response to a trigger signal, and a state machine for controlling memory operations of a memory circuit which includes such a controllable one-shot circuit. In preferred embodiments, the one-shot and the state machine of which it is a part are implemented as parts of a single memory chip (preferably, a nonvolatile memory chip such as an integrated flash memory circuit). Other aspects of the invention are methods of operating a state machine of a memory circuit to generate control signals for use in controlling memory operations performed by the memory circuit.

Abstract: A pulse generator comprising a delay circuit uses a series of "n" delay stages to generate pulses that do not have distorted duty cycles. The output of the delay stage "n" feeds back to reset the delay stage "n-2". The output of each of the delay stages initially changes from a first logic state to a second logic stage at the leading edge of a pulse. The output of each delay stage switches back to the first logic state, or the trailing edge of the pulse, upon receipt of the feedback signal from a subsequent delay stage. The wave characteristics depend only on the rising edge of the pulse because the rising edge of the pulse of a future stage generates the falling edge of the current stage.

Abstract: According to the present invention, clock control logic circuitry of a clocked memory device using precharged data path techniques generates a self-timed pulse. The self-timed pulse is representative of a pulsed path active strobe or a reset strobe of the clocked memory device. The clock control logic circuitry of the present invention is characterized as having at least a first delay timing chain, a second delay timing chain, and means for selectively changing the width of a self-timed pulse generated by the clock control logic circuitry. Selectively changing the width of the self-timed pulse is accomplished by selectively adding the delay of the first delay timing chain to the delay of the second delay timing chain during a special mode of operation of the clocked memory device.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: A ring oscillator includes a set of metal-oxide-semiconductor (MOS) complementary, inverting stages, wherein each stage includes a pair of cross-coupled CMOS NAND or NOR gates. The first and last stages are also cross-coupled, such that positive and negative output signals of the last stage are connected respectively to negative and positive input signals of the first stage.

Abstract: A circuit for producing multiple pulse width modulated outputs. The circuit includes a logic device for each pulse width modulated output. Each of the logic devices includes a first input, a second input, and a clock input, and each of logic device produces a logical high output in response to a logical high at its first input in coincidence with a clock signal at its clock input. The logical high output of the logic device remains high until a logical high is applied at its second input in coincidence with a clock signal at the clock input, whereupon the logic device produces a logical low output. The logical low output of the logic device remains low until a logical high is again applied at its first input in coincidence with a clock signal at the clock input. The circuit includes programmable circuitry for selectively applying logical high and low signals to the first and second inputs of the logic devices.

Abstract: A one-shot structure for controlling pulse widths on integrated circuit chips by using a reference oscillator to compensate the rate at which a capacitor is discharged through a transistor in a reference pulse generator. Compensation is accomplished by using a feedback circuit to control the voltage applied to the transistor in the reference pulse generator. The reference oscillator is used with the reference pulse generator to generate a control voltage which matches the reference pulse to the reference oscillator. The same control voltage is then applied to a desired pulse generator. The desired pulse generator has the same one-shot structure as the reference pulse generator, namely a capacitor and a discharge transistor. The pulse width of the desired pulse generator is determined by scaling the geometry of the capacitor and the discharge transistor in the desired pulse generator relative to the geometry of the corresponding components in the reference pulse generator.

Abstract: A phase-frequency detector (12) is configured for operating at a high frequency. A transition of a clock signal (REF CLK) is detected by a first latch (52) and a signal UP is generated. A transition of a feedback signal (FBK) is detected by a second latch (56) and a signal DOWN is generated. An logic circuit (64) detects the signals UP and the DOWN and generates a reset signal (RESET). A pulse-width of the reset signal (RESET) is controlled and limited by the logic circuit (64) to provide a faster response time for setting the first and second latches (52 and 56) to a state that allows detection of the phase and frequency differences between the clock signal (REF CLK) and the feedback signal (FBK).

Abstract: To produce pulses in a cyclically repetitive mode while modifying the production frequency, a counter looped on itself is used. The outputs of this counter are connected to the address inputs of a memory. The signals read in the memory represent pulses to be produced. When it is sought to increase the period of reading the totality of the memory gradually, some of the words of this memory are read for a greater period of time. In the invention, words are chosen for which this addressing will be maintained by comparing the reverse of the reading address with a given value and by deciding, as a function of the result of this comparison, whether the word read at this address must be read for a longer duration or not. It is shown that this circuit is very easy to make and requires but few components. The circuit made can be used particularly in the field of the control of three-phase synchronous motors.

Abstract: A constant frequency pulse-width modulator that realizes various control schemes with trailing-edge, leading-edge or double-edge modulation is disclosed. This PWM modulator, which employs one or more integrator with reset stages, can be generally applied to implement feed-forward control of a family of converters, current mode control with linear or non linear compensating slope, and a family of unity-power-factor rectifiers at continuous or discontinuous conduction mode.

Abstract: To use a high performance central processing unit (CPU)(e.g., operating with high frequency), a memory system includes a memory cell array having a plurality of word lines connected to memory cells, a latch circuit for receiving and latching a first control signal in response to a first clock signal and for outputting a second control signal, and a decoder for selecting one word line among the word lines in response to an address signal when the decoder receives the second control signal. The latch circuit includes a first latch portion for latching the first control signal during a first cycle of the first clock signal, and a second latch portion for latching the first control signal during a second cycle of the first clock signal.

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Abstract: A duration and frequency programmable electronic integrated pulse generator comprises an initialization circuit driven by a reference clock signal and an initialization/comparison signal and producing m initialization values, and a periodic count value coded on n bits. An address decoder module produces write-control bits, while a bits comparison matrix including n.times.m comparison cells each including a RAM and CAM memory cell write-addressable by the write-control bits. Each CAM cell stores a bit CAM.sub.ij of an initialization value and produces a complemented value CAM.sub.ij .sym.BL.sub.i , each RAM memory cell of address i, j produces a masking value M.sub.ij, and each comparison cell produces a value HIT.sub.ij =(CAM.sub.ij .sym.BL.sub.i)+M.sub.ij. All the cells of the same line of rank j are coupled by an OR function and produce, each output S.sub.j, a programmed pulse represented by the equation: ##EQU1## according to a harmonic periodic signal of the periodic count value.

Abstract: A tunable phase generator is disclosed suitable for use in integrated circuits. The phase generator includes a delay element wherein passive resistors and conductors are employed to provide relatively constant delays despite changes in operating temperatures and voltages. The phase generator is driven by a clock signal and generates therefrom a self-resettable output signal pulse with a selectable pulse width no longer than the width of the clock signal. The variable widths are provided by varying the delays of the delay elements and adding combinational logic between respective delay elements and at the input and output of the phase generator that ensure that, in most situations, the output signal pulse is reset after a delay that is independent of the pulse width of the clock signal. Delays are lengthened by decreasing the current available to a delay element for charging the capacitors.

Abstract: In order to generate a non-disturbed binary output signal from a disturbed input signal, notably if the latter is periodic in the non-disturbed state, the invention proposes a circuit arrangement which includes two circuit branches which respond to different edge directions of the input signal. Each branch includes two series-connected flipflops and there is also provided a timing member which is common to the two circuit branches. As a result of a coupling of the two circuit branches to one another it is achieved that, after the triggering of one circuit branch, the other branch is blocked. Triggering of the other circuit branch is possible only after the delay time of the timing member has elapsed. It is thus achieved that the edges of the binary output signal have a minimum temporal spacing or that the binary output signal does not exceed a maximum frequency. Furthermore, a transition of the input signal is evaluated also if it occurs prior to the elapsing of the delay time.

Abstract: A variable delay circuit including an input terminal to which a signal to be delayed is input, a delay gate connected to the input terminal, a logical gate to which an input to the delay gate and an output from the delay gate are input and which forms a delayed signal, and an output terminal outputting the delayed signal formed by the logical gate. A control signal for controlling the delay gate is input to the delay gate.

Abstract: A pulse signal shaper supplying a pulse signal having a stable pulse width, including an input circuit that produces a first pulse signal in response to an input signal, a delay circuit that produces a second pulse signal obtained by delaying the first pulse signal by a predetermined time, and a signal mixing circuit that is connected to the input circuit and the delay circuit. The mixing circuit combines the first pulse signal and the second pulse signal to produce a third pulse signal having a pulse width equal to or greater than a delay time provided by the delay circuit, and supplies the third pulse signal as an output signal from the pulse signal shaper. In a preferred embodiment, the input circuit includes an oscillator responsive to the input signal. When the input signal has a higher frequency than a predetermined frequency, the input signal is supplied as the first pulse signal at a frequency equal to te frequency of the input signal.

Abstract: A circuit for use with a data processing circuit having a transport chip for routing data is provided. The circuit includes a discrete digital logic circuit for sampling digital input signals and for generating a digital output timing signal based on the state of the digital input signals at any given point in time. The circuit minimizes default timing conditions in the transport chip.

Abstract: A pulse width modulation (PWM) circuit is disclosed for multiple channels. The circuit allows output pulses of a PWM signal for each channel to be distributed not simultaneously but with a time difference so that the power consumption is temporally distributed.

Abstract: The present invention relates to a method and device for symmetrizing a clock signal. The leading or trailing edge of each pulse of the clock signal (F.sub.in) to be symmetrized is used for forming the first edge of the pulse of the corresponding symmetrized clock signal (F.sub.out). The pulse ratio of the symmetrized clock signal is measured; and on the basis of the measured pulse ratio, the time constant circuit (R1, C1), determining the location of the second edge of the pulse of the symmetrized clock signal, is adjusted by means of a control loop (R6, C2, A) in such a manner that the second edge of the pulse of the symmetrized clock signal (F.sub.out) settles in a desired position in the symmetrized clock signal. (FIG.

Abstract: In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means.

Abstract: A write-control circuit including a pulse processor and a waveform shifter is disclosed. The pulse processor is provided for processing a first waveform. When the first waveform has a bandwidth wider than a first delay, the waveform goes through the pulse processor without change. Otherwise, a second delay is added to trailing edge of the first waveform. The waveform shifter is provided for shifting the output waveform of the pulse processor as a second waveform. The pulse processor consists of a pulse generator, a trailing edge delay circuit, a NOR gate and an inverter. The pulse generator, which generates a finite-length pulse by the first waveform, includes a delay chain and a NAND gate. The delay chain may consist of an odd number of delay units. The trailing edge delay circuit includes an even number of delay units and a NAND gate for adding the second time delay to the trailing edge of the finite-length pulses.

Abstract: A duty ratio-guaranteed reference clock signal and a duty ratio-unguaranteed drive clock signal serve as input to a clock signal waveform-correcting system in accordance with this invention. The system thereafter puts out a post-correction drive clock signal that is duty ratio-guaranteed. The system has a phase comparator and a switch circuit. The phase comparator puts out a HIGH signal as long as the reference clock signal and the drive clock signal disagree in logical level. The switch circuit transmits an inverted signal as a result of inverting the drive clock signal, to an output signal of a first buffer to which the drive clock signal is applied. A second buffer takes in the output signal and puts out a post-correction drive clock signal.

Abstract: An improved address transition detection circuit prevents malfunctions of a memory by generating an address transition detection signal having a certain pulse width regardless of the width of a pulse of an address signal inputted to a memory. The circuit includes a NOR-gate for NORing an address signal and a chip selection signal, which are externally applied thereto. A level maintaining unit maintains a level of a signal outputted from the NOR-gate for a predetermined time, in accordance with first and second latch signals and first and second delay signals, to output first and second level maintaining signals of different levels. A latch latches the first and second level maintaining signals outputted from the level maintaining unit and outputs first and second latch signals. First and second signal delay units delay first and second latch signals outputted from the latch for a predetermined time and output first and second delay signals.

Abstract: A controllable one-shot circuit for use in a control unit of a memory circuit, for asserting a control signal with variable (and controllable) duration in response to a trigger signal, and a state machine for controlling memory operations of a memory circuit which includes such a controllable one-shot circuit. In preferred embodiments, the one-shot and the state machine of which it is a part are implemented as parts of a single memory chip (preferably, a nonvolatile memory chip such as an integrated flash memory circuit). Other aspects of the invention are methods of operating a state machine of a memory circuit to generate control signals for use in controlling memory operations performed by the memory circuit.

Abstract: A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal.

Abstract: A pulse generating circuit for use in a semiconductor memory device is triggered by a transition of an input logic signal, to provide an output pulse having a predetermined pulse width or period. Feedback from the output pulse is used to isolate the input signal once the output pulse has begun, so as to prevent premature truncation of the output pulse if the input signal changes state during the output pulse period. This pulse generator is particularly advantageous in high-speed semiconductor memory integrated circuits where the input pulse may be relatively brief.

Abstract: An address transition detection circuit for driving an internal circuit of a memory device, includes an address input circuit for generating an input logic operation signal by a logic operation of a chip select signal and an address signal, a latch circuit for generating first and second latch signals, a feedback circuit for generating a feedback signal, first and second delay circuits for generating first and second delay signals by delaying the first and second latch signals for a prescribed delay time, and an address transition detection signal output circuit for receiving the first and second latch signals and the first and second delay signals, and generating an address transition detection signal having a pulse width longer than at least the twice the prescribed delay time of the first or second delay circuit when the address signal changes, thereby preventing malfunction of the memory device.

Abstract: A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.

Abstract: A pulse generator for use in generating pulses at different locations within a circuit has a first circuit 501 for a time dependent operation after receipt of a first input pulse and a second circuit 502 for carrying out a time dependent operation after receipt of a second input pulse after the first input pulse. A third circuit 503 is responsive to each of the first and second circuits 501,502 reaching respective predetermined conditions so that an output pulse is produced by the third circuit 503 at a time dependent on the average durations of operation of the first and second circuits 501 and 502.