Abstract: A pulse extending circuit includes a pulse extension inverting device for extending an input pulse signal by a predetermined width; and a delay device for extending the signal output from the pulse extension inverting device; thereby increasing a delay effect.

Abstract: In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, a data signal input terminal; a first signal input terminal to which a low-level signal of a logic gate is applied; n selector circuits (n=integer larger than 0) selecting either the signal at the data signal input terminal or the signal at the first signal input terminal in response to signals applied to first selector signal input terminals; and an (n+1)-input NOR circuit to which the signal at the data signal input terminal and output signals from the selector circuits are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled using only digital circuits.

Abstract: An edge-trigger pulse generator that is suitable for use in a signal generator is disclosed, including positive and negative logic embodiments. The positive logic embodiment includes: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate for receiving outputs of the first time-delay circuit and the second time-delay circuit, and performing a NAND logical operation for the outputs; and an inverter for receiving and inverting output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width. The negative logic embodiment replaces the NAND gate with NOR gate and has a second time-delay circuit that is different from the second time-delay circuit of the first embodiment.

Abstract: A pulse-width-extension circuit for producing an output pulse signal whose pulse width is extended as compared with a pulse width of an input pulse signal when the pulse width of the input pulse signal is equal to or longer than a given width. The pulse-width-extension circuit produces no output pulse signal when the pulse width of the input pulse signal is shorter than the given width.

Abstract: A variable pulse width generator comprised of apparatus for receiving a clock signal, apparatus for terminating an output pulse from a leading edge of the clock signal, and apparatus for initiating another output pulse following the terminated output pulse from the leading edge of the clock signal and after a first delay, whereby successive output pulses are initiated and terminated that are related to the leading edge of the clock signal, and thus are related to the frequency but not the pulse Width of the clock signal.

Abstract: A triangular wave generator circuit having a triangular wave generator unit for generating a triangular wave signal, and a comparator for comparing the generated triangular wave signal with a predetermined level. The triangular wave generator unit controls the generated triangular wave signal in accordance with the comparison result by the comparator.

Abstract: A pulse width modulation circuit comprises a data register for separating a data pulse signal into a first selection signal and a second selection signal, a delay signal generator for processing the first selection signal and a clock signal to generate a delay signal, and a logic gate circuit for processing the second selection signal, the clock signal, and the clock signal to generate a pulse width modulation data signal.

Abstract: An adjustable duty cycle clock generator has first and second delay lines coupled to receive an input clock and cascaded to first and second edge detectors, respectively. The second delay line has a programmable delay and the first and second edge detectors are further coupled to set and reset inputs on an S-R latch to generate an adjustable duty cycle clock with independently adjustable high and low times proportional to the induced delays of the first and second delay lines.

Abstract: An address transition detection circuit for a memory device, by which an address transition detect signal having a pulse width required for operating the memory device is outputted regardless of a pulse width of an address signal inputted to the memory device to thereby prevent any malfunction of the memory device, includes a NOR gate for NORing the inputted address signal and a chip select signal; a latch for latching an output signal of the NOR gate by first to third input delay signals to output first and second latch signals; first and second signal delays for respectively delaying the first and second latch signals provided from the latch for a predetermined time to respectively output first and second delay signals; and a signal output unit for outputting the address transition detect signal in accordance with the first and second latch signals respectively provided from the latch and the first and second delay signals respectively provided from the first and second signal delays.

Abstract: A demodulator circuit which demodulates pulse-width modulated signals used for data transfer within a semiconductor integrated circuit, including a sampling signal generator that generates a plurality of sampling signals after respective different predetermined times have elapsed since receipt of a leading edge of a pulse signal, and a plurality of sampling circuits provided in corresponding relation to the plurality of sampling signals which receive the pulse signal and the sampling signals associated therewith. The plurality of sampling circuits are rendered operable after receipt of the leading edge of the pulse signal and output a detection signal indicating whether or not a trailing edge of the pulse signal is received prior to receipt of the sampling signals. An encoder then generates data depending on which sampling circuit judges that the trailing edge of the pulse signal is received prior to receipt of the sample signals.

Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.

Abstract: A transition detection device, generating a variable-duration pulse, such as an enable signal for the input circuits of a CMOS static memory circuit, receiving an input signal that includes a delay circuit of determined delay value, making it possible to generate a delayed enable signal, with a safety margin of duration equal to the delay value. A calibration circuit is provided, which includes an exclusive-OR circuit receiving the input signal on a first input. A controlled delay circuit is provided to deliver an input signal delayed by a second delay value to a second input of the exclusive-OR circuit, which, upon access by the CEB signal, delivers a calibrated output pulse of duration equal to the second delay value, and truncated pulses for any transition occurring on the other inputs of the circuit, in the presence of address transitions or of other, not strictly simultaneous, inputs.

Abstract: In an address transition detection summing circuit, the varying address signal pulse widths can result in output signals from the address transition detection summing circuit which can compromise the performance of the associated memory circuitry. A parallel signal delay path, activated by the leading edge of the address signal, is incorporated in the address transition detection summing circuit and a logic ANDing element so that not only is the signal resulting from the trailing edge of the address signal applied to the logic ANDing element, but the trailing edge signal from the parallel signal delay path must be applied to the logic ANDing element before the trailing edge of the output pulse from the address transition detection summing circuit is generated. In the manner, an address transition always results in an output signal pulse having a preselected minimum width.

Abstract: A NAPNOP circuit for decreasing energy consumption of all or a portion of a microprocessor based system which includes a delay circuit for inhibiting or slowing the output of the system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a positive integer. The NAPNOP circuit has an input element for inputting a STARTNAP signal which begins a nap period during which the system clock pulses are inhibited or slowed, a clock input device for providing a plurality of selectable clock pulses as inputs to the delay circuit for controlling the operation of the computer system, and a gate element for terminating the nap period.

Abstract: A pulse generator comprises a transistor, a feed-back circuit and a second logic gate. The feed-back circuit includes a first logic gate coupled to at least one inverter, which is connected to a transmission gate. The first logic gate has a first terminal to receive a first input signal and a second terminal to receive an output of the transmission gate. The second logic gate receives an output of the feed-back circuit and a second input signal to generate an output signal. The feed-back circuit feeds back the first input signal through the first logic gate, at least one inverter and transmission gate to the second terminal of the logic gate for a prescribed period of time to change a pulse length of the first input signal.

Abstract: A first basic clock supplied from outside is delayed by a first delay circuit to generate a second basic clock which is fed to a frequency divider to generate a group of multi-phase clocks, each of which has a clock width equal to an integer number multiple of the clock width of the second basic clock and has a phase delay sequentially by a value equal to an integer number multiple of the clock period of the second basic clock, wherein the (n-1)th multi-phase clock and a nth multi-phase clock neighboring to each other in the phase sequence, and the first basic clock, are fed to a delay generating circuit as inputs, which comprises a second delay circuit for delaying the (n-1)th clock in the phase sequence, and a circuit arrangement for generating an output clock phase having a delay time relative to the nth clock, being equal to an smaller value of one half clock width of the first basic clock minus a delay time of the first delay circuit and a delay time of the second delay circuit.

Abstract: A transition detector circuit produces an output pulse upon detection of a transition at any one of several input nodes using a single delay path so all input transitions produce the same output pulse width and with only one gate delay in the circuit. The circuit includes precharging means, coupled between the plurality of transitioning inputs and the output node, for charging the output node high. The precharging means comprises stacked field effect transistor (FET) devices, each having a gate connected to a respective one of the transitioning inputs. A first charging device for charging the output node high is coupled to the output node. A second charging device for discharging the output node low is coupled to the output node. A single delay means, coupled between the plurality of transitioning inputs and both the first and second charging devices, both turns off the first charging device and turns on the second charging device.

Abstract: A circuit configuration generates an even-numbered duty factor with an odd-numbered division n of a symmetrical clock signal. A first device generates a first output signal from the symmetrical clock signal. The first output signal begins upon each n.sup.th edge of one type, of a symmetrical clock signal and remains active for a length of N-1/2 periods of the symmetrical clock signal. A second device generates a second output signal from the symmetrical clock signal. The second output signal begins upon each n.sup.th edge of another type, of the symmetrical clock signal and remains active for the length of N-1/2 periods of the symmetrical clock signal. A logic linkage is connected to the first and second devices for linking the two output signals to form one symmetrical output signal.

Abstract: A rate generating portion generates a second rate signal comprising a desired first rate signal having arbitrary time intervals preceded by a preceding rate signal composed of (N+1) pulses, a data row generating portion composed of N logic circuits and N D-type flip-flops generates an arbitrary data row with the second rate signal as a synchronizing clock, a preceding rate masking circuit masks the preceding rate signal in the second rate signal to output the first rate signal and a D-type flip-flop receives the output of the data row generating portion at the data input terminal thereof and the output of the preceding rate masking circuit at the clock input terminal thereof to generate a data row in synchronism with the first rate signal. As a result, it is possible to provide a synchronous data row generating circuit which operates stably without using the conventional delay elements for adjustment since the data row generating portion therein is composed of synchronous circuits.

Abstract: The present invention is a digital electronics system for generating multiple pulses within a predefined pixel clock period in a digital output device, where both a leading edge delay and a trailing edge delay are specified for a first pulse to be generated during the predetermined clock period. Pulse forming circuitry generates the first pulse during the portion of the clock period between the leading edge delay and the trailing edge delay, and an inverting circuit, selectable on a clock period basis, is activated to produce complimentary pulses within the selected clock period. The system is depicted as a two phase embodiment which enables high-speed operation.

Abstract: An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Abstract: A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch.

Abstract: A transition detection circuit is provided comprising input means receiving the signal to be monitored for generating a first pulse having a first predetermined pulsewidth when a transition occurs in the signal being monitored; and output means responsive to the first pulse from the input means for generating a second pulse having a second predetermined pulsewidth which is less than the first predetermined pulsewidth. The present invention permits a large number of signals to be monitored for transition yet provide a highly precise output pulsewidth, all with a minimum of circuitry. Preferably the input means include a plurality of input channels, each channel being assigned to a different signal being monitored and each channel providing the first predetermined pulsewidth using simple, non-precision time delay circuits. The output state employs a single, high precision time delay circuit to provide the second predetermined pulsewidth.

Abstract: A duty cycle control circuit, and an associated method, generates an output clock signal having a duty cycle which differs by a desired amount with the duty cycle of an input clock signal. Offset bias signal circuitry generates an offset bias signal which offsets a copy clock signal and an inverted copy clock signal relative to one another by a selected offset bias. The duty cycle of the output clock signal differs with the duty cycle of the input clock signal by an amount which is related to the amplitude of the offset bias signal.

Abstract: Noise on address lines is prevented from causing incomplete preparation for reading data after an address transition is detected. One ensures that a flash memory device reads correct data by guaranteeing that each address transition detection, including false address transition detections caused by noise, permits sufficient preparation to read data reliably. An address detected pulse is generated whenever at least one bit of an address changes. If noise causes an invalid address transition detected pulse that is too short to occur, the short pulse will be extended to permit preparation for the memory to be read. Input summation circuitry receives an input pulse and combines the input pulse with a feedback signal to form an input sum signal. Feedback circuitry receives the input sum signal and outputs the feedback signal to the input summation circuitry. The feedback signal holds the input sum signal until the feedback circuit is reset.

Abstract: A circuit for generating a sub-step pulse control signal using a step pulse in a step pulse generating circuit of a floppy disk driver included in a system such a personal computer. The sub-step pulse control signal generating circuit receives a step pulse and a step pulse enable signal and checks the period of the step pulse. When the period of the step pulse is shorter than a set time of a timer, the sub-step pulse control signal generating circuit produces a sub-step pulse having a fast generating time, and when the period of the step pulse is longer than the set time, a sub-step pulse having a slow generating time is produced. Thus, the generating time of the sub-step pulse is automatically adjusted.

Abstract: A pulse generator has a presetting clock synchronous counter having a count enable terminal, the counter which counts up input data using a clock signal whose basic unit of time width corresponds to its one period. The output from said counter is decoded to produce a first state signal. A second state signal is produced from said clock signal and a count enable signal for said counter. An output pulse having a desired pulse width is obtained by calculating the logical product of said first and second state signals.

Abstract: A pulse width modulation circuit apparatus comprises delay gates, delay circuits and an A/D converter. The delay gates are connected in cascade fashion and delay an input clock signal by the same delay time with each delay gate. The delay circuits are furnished interposingly between the delay gates and derive as their common output the delayed clock signal from the delay gates. Because the number of delay gates through which the input clock signal passes is proportional to the delay time acquired, these components constitute a delay circuit arrangement that offers high levels of linearity. With the delay circuit arrangement in use, any one of the delay circuits constituting part of that arrangement is supplied selectively with an operating current as per the digital output from the A/D converter. This provides a delayed clock signal whose delay time matches the level of the input analog signal.

Abstract: A basic clock signal generating circuit for use in a single chip microcomputer includes a frequency divider receiving an external clock signal for generating a frequency-divided clock signal, and a waveform shaping circuit receiving the frequency-divided clock signal output so as to generate a waveform-shaped frequency-divided clock as a basic clock of single chip microcomputer. An original oscillation clock generation circuit receives the external clock signal and generates an original oscillation clock having a frequency which is a-double of that of the basic clock. The basic clock and the original oscillation clock can be supplied to a peripheral circuit so that either the basic clock or the original oscillation clock can be selectively used in an internal circuit of the peripheral circuit.