With Clock Input Patents (Class 327/211)
  • Patent number: 10686431
    Abstract: A clocked comparator includes a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock; a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock; a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 16, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10454457
    Abstract: A self-gating flip-flop circuit includes a flip-flop circuit and a clock circuit. The flip-flop circuit includes a clock input. The clock circuit is coupled to the clock input. The clock circuit includes a latch circuit, a reset circuit, and a gate circuit. The reset circuit is coupled to the latch circuit. The gate circuit is coupled to the latch circuit and the clock input.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Priyankar Mathuria
  • Patent number: 10439625
    Abstract: A dynamic current correlating circuit is disclosed. The current correlating circuit includes a reset circuit, a first current generating circuit and a second current generating circuit. The reset circuit executes a discharging procedure during a first time interval and executes a charging procedure during a second time interval. The first current generating circuit is electrically connected to the reset circuit. The first current generating circuit generates a first sub-current and a second sub-current during a third time interval according to a first input voltage and a second input voltage and generates a first current after the third time interval. The second current generating circuit is electrically connected to the reset circuit. The second current generating circuit generates a second current according to the first input voltage and the second input voltage after the third time interval.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: October 8, 2019
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Sheng-Yu Peng, Hao-Yu Li, Tzu-Yun Wang, Yang-Jing Huang, Zong-Yu Ma, Shih-An Yu
  • Patent number: 10331196
    Abstract: A system and method for providing efficient clock gating capability for functional units are described. A functional unit uses a clock gating circuit for power management. A setup time of a single device propagation delay is provided for a received enable signal. When each of a clock signal, the enable signal and a delayed clock signal is asserted, an evaluate node of the clock gating circuit is discharged. When each of the clock signal and a second clock signal is asserted and the enable signal is negated, the evaluate node is left floating for a duration equal to the hold time. Afterward, the devices in a delayed onset keeper are turned on and the evaluate node has a path to the power supply. When the clock signal is negated, the evaluate node is precharged.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 25, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Russell Schreiber
  • Patent number: 10243567
    Abstract: A flip-flop includes a conditional boosting stage, a pulse generator and a latch. The conditional boosting stage includes a boosting capacitor, and is configured to pre-charge the boosting capacitor in accordance with a previous output signal and boost a node connected to the boosting capacitor upon a level the previous output signal being different from a level of a current input signal. The pulse generator is configured to generate a pulsed signal in accordance with transitions of a clock signal. The latch configured is to latch the current input signal to a current output signal in accordance with the pulsed signal.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 26, 2019
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Bai Sun Kong, Ji Hoon Park
  • Patent number: 10126621
    Abstract: The present disclosure proposes a GOA circuit based on LTPS TFTs. A ninth TFT is introduced to adjust the high and low voltage levels imposed on the second node P(n). The ninth TFT includes a gate and a source both electrically connected to the second node P(n) and a drain electrically connected to a second clock signal. Such designs make it possible that the level of the second node P(n) is pulled down according to a certain frequency when an output terminal G(n) keeps the low voltage level. So the second node P(n) does not need to keep the high voltage level all the time in the present invention. Also, the fourth and the seventh transistors T4 and T7 do not have the problem of a threshold voltage shift due to a long working time.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 13, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yafeng Li
  • Patent number: 9846568
    Abstract: A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: December 19, 2017
    Assignee: Synopsys, Inc.
    Inventors: Neil Farquhar Hamilton, Scott Andrew Hamilton, Michael Borza
  • Patent number: 9276594
    Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 1, 2016
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Cory Jay Peterson, Bhoodev Kumar, Daniel John Allen, Jeffrey D. Alderson
  • Patent number: 9197397
    Abstract: A clock deskew circuit for transferring data from a first clock domain to a second clock domain. This circuit includes a data path, which has: a transmitter latch controlled by a transmitter clock in a first clock domain; a receiver latch controlled by a receiver clock in a second clock domain; and an intermediate latch coupled between the transmitter latch and the receiver latch. The transmitter clock and the receiver clock have an unknown phase offset. The circuit additionally includes a control circuit coupled between the transmitter clock and the receiver clock, and generates a control clock for the immediate latch based on the transmitter clock and the receiver clock. The control circuit selects between a first operation mode and a second operation mode for the data path circuit based at least on the phase relationship of the control clock with respect to the transmitter clock and the receiver clock.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 24, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Tarik Ono, Suwen Yang, Mark R. Greenstreet
  • Patent number: 9076529
    Abstract: A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an NMOS transistor having a drain electrode and a source electrode coupled to a ground, wherein the NMOS transistor turns on in response to the input data signal with a high level.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 7, 2015
    Assignee: POWERCHIP TECHNOLOGY CORP.
    Inventor: Akira Ogawa
  • Patent number: 9058892
    Abstract: Data can be stored even when the supply of a power source voltage is stopped. A semiconductor device includes a logic circuit to which a data signal is input through an input terminal; a capacitor having a pair of electrodes, one of which is supplied with a high power source potential or a low power source potential and the other of which is supplied with a potential of the input terminal of the logic circuit, so that data of the data signal is written as stored data to the capacitor; and a transistor for controlling conduction between the input terminal of the logic circuit and the other of the pair of electrodes of the capacitor, thereby controlling rewriting, storing, and reading of the stored data. The off-state current per micrometer of channel width of the transistor is lower than or equal to 100 zA.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9007113
    Abstract: According to one aspect of the present disclosure, there is provided a flip flop circuit, comprising a first input circuit configured to receive a clock input signal and input data and comprising a first node. The flip-clop circuit further comprises a second input circuit configured to receive the input data and an inverse of the clock signal and comprising a second node. The first and second input circuits are configured such that the first node and the second node are pre-charged to respective complementary states when the clock signal is at a first level and, dependent on a value of the input data, one of said first and second nodes changes state to a state complementary to its pre-charged state when the clock signal transitions from the first level to a second level.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventors: Stephen Felix, Stéphane Badel
  • Patent number: 8957716
    Abstract: An integrated circuit cell includes a set of circuit elements associated with a logic function along a logical path between an input and an output of the integrated circuit cell. The set of circuit elements includes a first subset of circuit elements having a first width size and a first threshold voltage and configured to operate within a cycle of time. The set of circuit elements also includes a second subset of circuit elements having a second width size and a second threshold voltage and configured to operate within the cycle of time. The first subset and second subset of circuit elements are configured to toggle data between the input and the output. The second threshold voltage is less than the first threshold voltage when the second width size is less than the first width size.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8947146
    Abstract: A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a first clock signal and the second clock signal. The pulse-based flip-flop includes a pulse generator and a data latch. The pulse generator includes a first inverter and a signal delay circuit to receive the first clock signal and generate the second clock signal; the data latch includes a delivery circuit, a latch circuit and a control circuit. The data latch is used to latch the data input signal and output the data output signal in response to the first and the second clock signals.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: February 3, 2015
    Assignee: National Chiao Tung University
    Inventors: Chen-Yi Lee, Wei-Hao Sung, Ming-Che Lee
  • Patent number: 8917800
    Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Matsumoto, Naoki Mori, Takashi Yagi
  • Patent number: 8898502
    Abstract: A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: November 25, 2014
    Assignee: Psion Inc.
    Inventors: Steven William Maddigan, Dimitri Gabriel Epassa Habib
  • Patent number: 8860484
    Abstract: Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Oracle International Corporation
    Inventors: Ha M Pham, Jin-uk Shin
  • Patent number: 8842722
    Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Timothy O. Dickson, Rui Yan Matthew Loh
  • Publication number: 20140266369
    Abstract: Systems and methods for operating transistors near or in the sub-threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal to a flop via a clock path comprising a plurality of transistors, wherein the clock signal has a high state corresponding to a high voltage that is above threshold voltages of the transistors in the clock path. The method also comprises sending a data signal to the flop via a data path comprising a plurality of transistors, wherein the data signal has a high state corresponding to a low voltage that is below threshold voltages of the transistors in the data path. The method further comprises latching the data signal at the flop using the clock signal.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: QUALCOMM Incorporated
    Inventor: Michael Joseph Brunolli
  • Publication number: 20140218089
    Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: ARM LIMITED
    Inventors: Virgile JAVERLIAC, Yannick Marc NEVERS, Laurent Christian SIBUET, Selma LAABIDI
  • Patent number: 8786345
    Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, William J. Dally
  • Publication number: 20140152363
    Abstract: A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a first clock signal and the second clock signal. The pulse-based flip-flop includes a pulse generator and a data latch. The pulse generator includes a first inverter and a signal delay circuit to receive the first clock signal and generate the second clock signal; the data latch includes a delivery circuit, a latch circuit and a control circuit. The data latch is used to latch the data input signal and output the data output signal in response to the first and the second clock signals.
    Type: Application
    Filed: March 29, 2013
    Publication date: June 5, 2014
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chen-Yi LEE, Wei-Hao SUNG, Ming-Che LEE
  • Patent number: 8742804
    Abstract: A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Fujita, Yukio Maehashi
  • Patent number: 8736334
    Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Limited
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Patent number: 8730404
    Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Clayton Daigle, Abdulkerim L. Coban
  • Publication number: 20140132323
    Abstract: A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 15, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Ming Tsai, Bo-Jyun Kuo, Bo-Wei Chen
  • Publication number: 20140125392
    Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: ARM LIMITED
    Inventors: Virgile JAVERLIAC, Yannick Marc NEVERS, Laurent Christian SIBUET, Selma LAABIDI
  • Patent number: 8692581
    Abstract: A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 8, 2014
    Assignee: Agilent Technologies, Inc.
    Inventor: Minjae Lee
  • Patent number: 8674738
    Abstract: An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuji Nishijima
  • Patent number: 8674739
    Abstract: A single inversion pulse flop includes a critical evaluation path with a single inverter and a storage feedback loop arranged in parallel with the critical evaluation path. The single inversion pulse flop incurs a single inversion delay and does not require an output buffer.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: March 18, 2014
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Anand Dixit
  • Publication number: 20140070861
    Abstract: A flip-flop circuit consuming lower power than a conventional flip-flop circuit is provided. Further, a flip-flop circuit having a smaller number of transistors than a conventional flip-flop circuit to have a reduced footprint is provided. An n-channel transistor is used as a transistor which is to be turned on at a high level potential and a p-channel transistor is used as a transistor which is to be turned on at a low level potential, whereby the flip-flop circuit can operate only with a clock signal and without an inverted signal of the clock signal, and the number of transistors that operate only with a clock signal in the flip-flop circuit can be reduced.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 13, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masashi Fujita
  • Publication number: 20140015582
    Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Tsung-Ching HUANG, Derek C. TAO
  • Patent number: 8604855
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Ge Yang
  • Patent number: 8531208
    Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gun Ok Jung, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
  • Patent number: 8487681
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: July 16, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, G E (Francis) Yang
  • Patent number: 8466727
    Abstract: A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: June 18, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Frédéric Bancel, Philippe Roquelaure
  • Patent number: 8461891
    Abstract: A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: June 11, 2013
    Inventors: Robert Fu, Neal A. Osborn, James B. Burr
  • Patent number: 8451041
    Abstract: A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: May 28, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Jason T. Su, Winston Lee, Yuntian Chen
  • Publication number: 20130127507
    Abstract: A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Inventor: Jingcheng Zhuang
  • Patent number: 8436668
    Abstract: A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: May 7, 2013
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Jason M. Hart
  • Patent number: 8436669
    Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 7, 2013
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, William J. Dally
  • Patent number: 8421514
    Abstract: A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a D1 signal, an input to accept a clock signal, an input to accept an inverted shadow-D2 signal, and an output to supply a D2 signal. The master latch has an input to accept a shadow-D1 signal, an input to accept the clock signal, and an output to supply a shadow-D2 signal and the inverted shadow-D2 signal. The slave latch has an input to accept the D2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the D2 signal or the shadow-D2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 16, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Alfred Yeung, Hamid Partovi, Luca Ravezzi, John Ngai
  • Patent number: 8416002
    Abstract: A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Chung-Cheng Chou, Yi-Tzu Chen
  • Patent number: 8354858
    Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
  • Patent number: 8320195
    Abstract: A disclosed memory circuit includes first and second latch circuits, each writing a write data at a timing of a clock signal and retaining the write data, the write data having been input in each of the first and second latch circuits, a data input circuit supplying the write data to each of the first and second latch circuits when a write enable signal indicates a state allowing the write data to be written, a write back circuit supplying the write data retained in the second latch circuit to the first latch circuit when the write enable signal indicates a state preventing the write data from being written, wherein a robustness against noise in the second latch circuit is more improved than that in the first latch circuit.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Masao Ide, Tomohiro Tanaka
  • Patent number: 8233306
    Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Publication number: 20120169393
    Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Nitin Gupta, Nitin Jain
  • Patent number: 8207756
    Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: June 26, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hidetomo Kobayashi
  • Patent number: 8169246
    Abstract: A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: May 1, 2012
    Assignee: Apple Inc.
    Inventors: Khurram Z. Malik, Andrew L. Arengo
  • Publication number: 20120098582
    Abstract: A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Chung-Cheng Chou, Yi-Tzu Chen