Abstract: A semiconductor integrated circuit including: a first latch to pass or store a signal in accordance with a logic value of a first internal clock signal; a second latch connected in series to the first latch, to pass or store a signal in accordance with a logic value of a second internal clock signal, with inverted operational characteristics in regard to the first latch; comparators to compare signal logic values at signal-input and -output nodes of the first latch; and the second latch; a first clock controller to generate a signal having a specific logic value in dependence on whether nodes of the first latch have the same or different signal logic values, as the first internal clock signal, based on the output of the first comparator; and a second clock controller to generate a signal having a specific logic value in dependence on whether nodes of the second latch have different signal logic values, as the second internal clock signal, based on the output of the second comparator.

Abstract: A semiconductor holding device comprises a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source, and a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a clock signal being supplied to gates of the N type third and sixth transistors, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.

Abstract: A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29. Latch circuit 30 comprises an inverter 31 and a tristate NOR gate 32. When the CLK (clock input signal) and CLRZ (the inverse of the clear input signal) are both low, the output of the tristate NOR gate 32 is forced low. Thus the input of inverter 31 is low so that the output signal, Q, is forced low and the inverse output signal, QZ, is forced high. When CLK is high and CLRZ is low the output of tristate NAND gate 29 is forced high so that the input to inverter 28 is high and the input to inverter 31 is low, thereby forcing Q low and QZ high. Thus the outputs Q and QZ are forced low and high respectively when CLRZ is low, regardless of the state of the CLK input.

Abstract: A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.

Abstract: Low voltage latches are designed such that the latch components are comprised of low threshold transistors. To overcome the effects of leakage current and ensure proper latch operation, according to the invention, the channel widths of the low threshold transistors making up the feedback components of the latch are larger than the channel widths of the low threshold transistors making up the storage components of the latch. Using the method and structure of the invention, the voltage scalability of the latch is significantly increased. One embodiment of the invention allows for minimum supply voltages of around 120 millivolts, an improvement of over six hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: A data capture circuit includes a series channel sampling structure coupled to an evaluation element. The series channel sampling structure includes a plurality of series-connected transistor devices configured for operation under the control of at least one clock signal to connect an input signal, applied to an input of the series channel sampling structure, to an input of the evaluation element, and to subsequently disconnect the input signal from the input of the evaluation element. Advantageously, the series channel sampling structure can be configured and clocked in a manner that ensures that connection of the input signal to the input of the evaluation element occurs only at or near transitions of the clock signal, such that power dissipation in the data capture circuit is reduced and its speed of operation can be increased.

Abstract: It is intended to provide a dynamic flip flop that prevents a floating signal from maintaining a voltage below a substrate voltage level in a P-type semiconductor substrate and that prevents a floating signal from maintaining a voltage exceeding the substrate voltage level in an N-type semiconductor substrate. In the dynamic flip flop, an N-type MOSFET (5) controlled by an output signal MX from an inverter (2) and an N-type MOSFET (6) controlled by an output signal Q from an inverter (4) are provided as switches for short-circuiting a signal M and a signal QX to be brought into a floating state to a substrate.

Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.

Abstract: A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.

Abstract: A method and apparatus for storing data in a master flip flop, comprising in combination receiving a clock signal having a first and second state, storing a master data state in a master storage device having a master storage input and a master storage output, storing a master complement data state in a master complement storage device having a master complement storage input and a master storage complement output, receiving a data input signal by a transmission gate, receiving a complement data input signal by a complement transmission gate, overriding the master storage complement output with the data input signal when the clock is in the first state, overriding the master storage output with the complement data input signal when the clock is in the first state, disconnecting the master storage complement output from the data input signal when the clock is in the second state, and disconnecting the master storage output from the complement data input signal when the clock is in the second state.

Abstract: Latch circuitry has a data input stage for sampling a first input signal responsive to a first timing signal and generating a signal on an intermediate node in the latch circuitry. The latch circuitry also has a scan input stage for sampling a second input signal responsive to a second timing signal, and generating a signal on the intermediate node. The latch circuitry also has an output stage for generating an output signal on an output node of the latch circuitry responsive to the signal on the intermediate node and a third timing signal. The data input signal has a maximum voltage level and at least one stage of the latch circuitry is operable to effectively shift the voltage level so that the output signal has a higher maximum voltage level than that of the data input signal.

Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.

Abstract: A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal O1={overscore (I1+Clk)}. A second inverter has as inputs capacitively coupled the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((Clk×P)+O1)}.

Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.

Abstract: A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.

Abstract: The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Abstract: A flip-flop circuit comprises a master latch circuit (2), which receives an input signal (D), and, connected in series therewith, a slave latch circuit (3), the two latch circuits (2, 3) being actuated complementarily-to one another by a clock signal. The output signal value (Q,{overscore (Q)}) of the flip-flop circuit is emitted from the output of the slave latch circuit (3) not directly but via a non-differential output driver circuit (4), e.g. an inverter circuit.

Abstract: A flip-flop circuit comprising a first stage having a transmission gate to receive a data signal from an input node, and a second stage connected to the first stage, the second stage having another transmission gate to transfer the data signal to a memory unit, wherein the memory unit provides complementary output signals.

Abstract: Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: The complementary outputs of a master slave flip flop are made symmetric, with substantially zero timing skew over all process, voltage and temperature conditions. This is accomplished by utilizing a master latch and a pair of identical slave latches. Although the complementary outputs from the master latch have non-zero timing skew when the clock goes low, they have zero timing skew when the clock goes high. Thus the identical slave latches, whose outputs react to the master latch outputs only when the clock goes high, do not have any timing skew.

Abstract: The propagation delay time, power dissipation and silicon area of a double edge triggered flip flop are reduced by utilizing an inverter, a pair of latches, and a two-to-one multiplexer. A first latch outputs a first device signal in response to a first data signal when a clock signal is in a first logic state, and latches the logic state of the first device signal when the clock signal is in a second logic state. A second latch outputs a second device signal in response to a second data signal when the clock signal is in the second logic state, and latches the logic state of the second device signal when the clock signal is in the first logic state. The multiplexer controls the logic state of the flop output signal in response to the logic state of the first device signal when the clock signal is in the second logic state, and in response to the logic state of the second device signal when the clock signal is in the first logic state.

Abstract: An ultra high-speed clocked analog latch is revealed for use at clock speeds from 100 MHz to several GHz. The analog latch is used as a latching comparator for comparing a time-varying analog signal with an analog reference voltage. The latch uses CMOS manufacturing technology and a minimal amount of space for a two-stage amplifying and signal-generating device. The latch is useful in analog to digital converters (ADCs) in which high speed and high reliability are required, but only a small amount of space is available. The device is so small and economical that several may be used in series to avoid any meta-stability problems in high-speed read/write operations.

Abstract: A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic initialization circuitry.

Abstract: Flip-flop circuits having digital-to-time conversion latches therein include a pair of logic gates that each have first and second data inputs and an output. The first inputs are electrically connected together and are responsive to a latching signal. Each of the second data inputs is electrically connected to an output of the other logic gate in the pair. The pair of logic gates includes a first logic gate having first circuitry therein that, in response to a first control signal, adjusts a pull-down delay characteristic of the first logic gate. This pull-down delay characteristic is adjusted by reducing an effective on-state impedance of a first pull-down path within the first logic gate when an output of the first logic gate is being pulled from a logic 1 value to a logic 0 value by the first pull-down path.

Abstract: A storage element includes a forward inverter and a feedback inverter cross-coupled between a storage node and a feedback node. A capacitive load within the feedback inverter is coupled to the storage node when the storage element holds data and is not coupled to the storage node when the storage element is loading. The capacitive load reduces the storage element's susceptibility to soft errors when holding data, and does not appreciably slow the storage element when data is loading. The capacitive load is implemented using the gate capacitance of complementary transistors connected to stack nodes within the feedback inverter. A flip-flop includes cascaded latches, one or more of which have the internal capacitance.

Abstract: Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: A latch circuit having reduced propagation delay and set-up and hold times comprises at least one set of cross-coupled transistor devices arranged between an upper supply terminal of the circuit and a lower supply terminal of the circuit. A first input transistor device is coupled in parallel with a first one of the transistor devices of the set of cross-coupled transistor devices, and a second input transistor device is coupled in parallel with a second one of the transistor devices of the set of cross-coupled transistor devices. The first and second input transistor devices are adapted for application of respective uncomplemented and complemented inputs thereto during an initialization mode of the latch circuit. Uncomplemented and complemented output signals are generated at corresponding output terminals associated with the set of cross-coupled transistor devices during an evaluation mode of the latch circuit.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: A semiconductor holding device comprises a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source, and a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a clock signal being supplied to gates of the N type third and sixth transistors, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.

Abstract: A static, double-edge-triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loops share a forward path having a data-inverting circuit. In addition, each loop has a feedback path which contains only one element in the form of a switch. However, no data-inverting circuit is included in either of the feedback paths. Advantageously, all the elements of the flip-flop may be constructed using MOSFET transistors implemented according to any one of a variety of semiconductor technologies. In more than one particularly advantageous embodiments, the flip-flop is constructed using a total of twelve transistors.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of time after the start of the evaluation phase.

Abstract: Undersired glitches in output signals from TSPC-1 flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock transition) to a value desired at the output node during a period following the clock transition, and connecting the output node to the second node upon such clock transition. Corrective circuitry illustratively comprising two NMOS transistors added to the output stage and receiving an input reflecting the desired future output is active during a portion of the operating cycle when the output stage exhibits a high impedance tristate condition.

Abstract: A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic initialization circuitry.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: An edge-triggered latch having improved clock-to-output performance and greater efficiency. The edge-triggered latch of the present invention includes a data input and a clock input. Multiple source-to-drain connected pass-transistor logic (PTL) transistors are incorporated in the data path of the edge-triggered latch for converting a clock signal from the clock input into an edge-triggered data evaluation window. The PTL transistors propagate data from the data input into a storage node during the edge-triggered data evaluation window.

Abstract: An integrated circuit device for synchronization of data in a data path includes a driver and a storage element coupled to the driver for driving the storage element. The storage element is coupled to the data path outside the data path. The integrated circuit employs a method of operation including passing a time pulse, sampling data during the time pulse, passing the data to a computation logic along a data path, and storing the sampled data in a storage element connected to but outside the data path.

Abstract: A circuit including a data signal input to receive a data signal, a clock signal input to receive a clock signal, a clocking circuit to generate control clocks, and a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output. The circuit also includes at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter and at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter. A keeper circuit receives the output of the multiple input conditional inverter and a buffer circuit receives the output of the multiple input conditional inverter and generates the circuit output.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

Abstract: A tristable latch circuit fabricated utilizing standard MOS process technology includes a biasing element for identically biasing the MOS transistors in triode (as opposed to saturation) to implement a third stable operating point.

Abstract: A latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time. This is preferably accomplished by providing both a data input signal and a complement data input signal to the latch or flip-flop. The data input signal and the complement data input signal are selectively connected to opposite sides of a pair of cross-coupled gates via a switch or the like. The switch is preferably controlled by an enable signal, such as a clock. With the switch elements enabled, the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal. Because the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal, the clock-to-q time may be reduced.

Abstract: Register and latch circuits are disclosed that can have faster operating speeds. According to one embodiment, a register circuit (100) may include a master latch circuit (102) and a slave latch circuit (104). The slave latch circuit (104) may include an n-channel transistor M13 between an input of the slave latch circuit (104) and the gate of a p-channel driver transistor M11. A p-channel transistor M14 can be provided between the input of the slave latch circuit (104) and the gate of an n-channel driver transistor M12. The driver transistors M11 and M12 can be driven by way of the source-drain paths of transistors M13 and M14, respectively.

Abstract: A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.

Abstract: A static logic signal to dynamic logic interface that produces a monotonic output. An inverse of a dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and enable inputs. A delayed version of the inverse of the evaluate clock is generated by a delay element. The delayed inverse of the evaluate clock is fed to the enable input of the latch. The input to the latch comes from static logic and the output of the latch is fed to the dynamic logic. The net result is a latch that is open until the evaluate clock is instructing the dynamic logic to evaluate, and remains closed until a delay element delay time after the evaluate clock instructs the dynamic logic to reset.

Abstract: Complementary passive analog logic (CPAL) devices and circuits involve low power characteristics, and have high speed integrated circuit technology that is analog in design yet mimics the low power characteristics of complementary metal oxide (CMOS) logic designs. CPAL acts like CMOS in a high or low logic clock condition, but is analog in nature when clocked. CPAL is a distributed charge pump that super-positions an analog transient on a digital bias voltage. The two add vectorially on the positive going clock pulse. Nominal direct current (DC) power supply voltage is approximately equal to the threshold voltage of an N-channel transistor. CPAL is completely synchronous in operation, and a virtual open circuit in a non-clocked more. This pertains to reducing the noise found today in most integrated circuits. The latch design is for circuits of approximately 1.2 microns, and multiple flip-flops are provided to recapture most of the lost energy in existing integrated circuit designs.

Abstract: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Abstract: A flip-flop circuit comprises a pair of cross-coupled inverters, each of which has a respective FET connected in series between it and the reference terminal, each inverter driving a transistor of an output inverter.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.