Abstract: In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

Abstract: A latch circuit comprising a tristate driver and a storage feedback loop and having minimal circuit elements is disclosed. The tristate driver and feedback loop couple to internal nodes of a separate latch circuit to reduce total circuit element count by collapsing elements with common functionality into a single circuit element. The latch circuit presents only one transistor gate load to a clock signal, and the output of the separate latch is coupled to the input of the latch circuit to form a flip-flop. The flip-flop generates an output signal based on a received input signal when the clock signal is at second level and stores the received input signal when the clock signal is at first level. The flip-flop is fully static, contention-free, with near-zero setup time, with less circuit elements than prior arts, and can be configured to integrate multi-input logic functions.

Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.

Abstract: In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.

Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A first transistor has a source and a gate coupled to first and second voltage nodes respectively. A second transistor has a source and a gate coupled to third and second voltage nodes respectively. A third transistor is coupled between the first and second transistors. A fourth transistor has a source coupled to the first voltage node and a gate coupled to a first output node between the second and third transistors. A fifth transistor has a source coupled to the third voltage node, a gate coupled to the gate of the fourth transistor and a drain coupled to a drain of the fourth transistor. A sixth transistor has a gate supplied with a voltage output from a second output node between the fourth and fifth transistors and a source coupled to the first voltage node.

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

Abstract: Superconducting switching devices of electrically-polarizable ferroelectric materials and electrically conductive materials with control electrodes. Superconducting states of the superconducting switching devices are determined by polarization states of the electrically-polarizable ferroelectric materials and voltages applied to the control electrodes.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

Abstract: In one aspect, an integrated circuit (IC) includes a level shifter configured to generate a first output signal and a second output signal, and to receive an input voltage, a first supply voltage and a second supply voltage; and a state reinforcement circuit configured to maintain a logical state of the second output signal in response to the first supply voltage having a voltage below ground and the input voltage is logical high. If the input voltage is logical high, then the first output signal is logical low and the second output signal is logical high; and, if the input voltage is logical low, the first output signal is logical high and the second output signal is logical low.

Abstract: A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

Abstract: An apparatus is configured to receive a two-phase input clock and output a four-phase output clock. The apparatus includes a circuit configured in a ring topology comprising a first switch controlled by a first phase of the input clock, a first inverting amplifier, a second switch controlled by a second phase of the input clock, a second inverting amplifier, a third switch controlled by the first phase of the input clock, a third inverting amplifier, a fourth switch controlled by the second phase of the input clock, and a fourth inverting amplifier, wherein the first inverting amplifier and the third inverting amplifier share a first regenerative load that is reset upon the first phase of the input clock, and the second inverting amplifier and the fourth inverting amplifier share a second regenerative load that is reset upon the second phase of the input clock.

Abstract: A circuit for power supply protection comprising a first n-channel Metal Oxide Semiconductor Field Effect Transistor (nMOSFET) and a first p-channel Metal Oxide Semiconductor Field Effect Transistor (pMOSFET) each having a drain terminal coupled to an input voltage, a second nMOSFET and a second pMOSFET having drain terminals coupled to an output voltage and sources coupled to a sources of the first and second nMOSFET, respectively, and a control circuit. The control circuit turns the nMOSFETs off and the pMOSFETs on when the input voltage has a voltage value greater than zero and less than a predetermined positive limit, operates the nMOSFETs in a saturation mode and turns the pMOSFETs off when the input voltage has a voltage value greater than the predetermined positive limit, and turn the nMOSFETs and pMOSFETs off when the input voltage has a voltage value less than zero.

Abstract: A high voltage driver includes a high-side output transistor circuit, a differential to single-ended (D2SE) converter connected to a gate of the high-side output transistor circuit, wherein the D2SE is supplied by a first and a second supply voltage, and a high voltage translator connected to the D2SE converter. The D2SE converter and the translator circuit are used to clamp a voltage at the gate of the high-side transistor circuit to be the first supply voltage less the second supply voltage.

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

Abstract: Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell operates in either a test mode or a normal functional mode according to a scan enable signal. The scan cell comprises delay logic including a plurality of delay elements, e.g., a plurality of transistors. The delay logic activates the delay elements only when the scan cell operates in the test mode. The delay elements are activated to change a scan latency of the scan cell. The scan latency of the scan cell is increased to mitigate or prevent hold violations.

Abstract: An interface circuit includes at least one semiconductor logic gate and a latch circuit. The semiconductor logic gate configured to receive an input signal having a signal level changeable and outputs a logic gate signal which has a signal level becoming a low level when a signal level of the input signal is not less than a logic threshold value, alternatively has a signal level becoming a high level when a signal level of the input signal is less than the logic threshold value. The latch circuit fetches the logic gate signal as a first latch signal, while fetching a signal which is converted from the input signal and has a signal level varying between a second voltage and the ground potential, alternatively, the input signal as a second latch signal, to output the first interface output signal and the second interface output signal.

Abstract: Integrated circuits with clocked storage elements are provided. A clocked storage element such as a flip-flop circuit may include a master latch, a slave latch, and associated control circuitry. The master and slave latches may be implemented using dual-interlocked cell (DICE) latch configurations. The DICE latch may include at least four inverting circuits having two redundant node pairs and may exhibit immunity to soft error upset (SEU) events. Each of the master and slave latches may be separated into different portions so that the redundant nodes are physically separated by interposing circuitry. The redundant nodes may also be formed in separate wells to further minimize charge sharing. The different portions of the master and slave latch may be interleaved to minimize area.

Abstract: Systems and methods are provided for reading from a static random-access memory (SRAM). The systems and methods include activating a first bitline connected to a first transistor, wherein the first transistor provides access to a state stored by the SRAM. The systems and methods further include preventing a second bitline from being activated when the first bitline is activated, wherein the second bitline is connected to a second transistor that isolates the SRAM from a reference potential when the second bitline is activated, and reading the state stored by the SRAM by triggering a wordline connected to a gate of the first transistor.

Abstract: A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.

Abstract: A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the nonvolatile semiconductor storage device, the volatile storage device and the nonvolatile storage device are provided without separation. Specifically, in the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor.

Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

Abstract: Semiconductor devices are provided. The semiconductor device includes a charge controller, a delay unit and a discharger. The charge controller controls an amount of electric charges on a first node to output a drive signal through the first node. The delay unit includes a capacitor coupled to the first node and retards the drive signal to generate an output signal. A delay time of the drive signal is controlled according to an amount of electric charges of the first node. The discharger discharges the electric charges of the first node when the amount of electric charges of the first node is equal to a predetermined value.

Abstract: To reduce power consumption of a circuit (TEDC) which detects timing errors in a main flip-flop by determining whether or not output data signals of the main flip-flop and a shadow flip-flop correspond. The TEDC includes a power gating circuit (PGC) which performs power gating of the shadow FF and a reset circuit (RSTC) which resets an output signal of the shadow FF. The PGC makes the shadow FF in an active mode only when error detection needs to be performed; other than that, the PGC makes the shadow FF in a power saving mode. The RSTC supplies a certain voltage to an output terminal of the shadow FF in the power saving mode to suppress malfunction of the TEDC. A transistor using an oxide semiconductor is used to supply the voltage to the output terminal.

Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.

Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.

Abstract: In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

Abstract: An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.

Abstract: A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.

Abstract: A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal.

Abstract: A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.

Abstract: A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.

Abstract: A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period star

Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.