Cmos Patents (Class 327/210)
  • Patent number: 10979051
    Abstract: In one aspect, an integrated circuit (IC) includes a level shifter configured to generate a first output signal and a second output signal, and to receive an input voltage, a first supply voltage and a second supply voltage; and a state reinforcement circuit configured to maintain a logical state of the second output signal in response to the first supply voltage having a voltage below ground and the input voltage is logical high. If the input voltage is logical high, then the first output signal is logical low and the second output signal is logical high; and, if the input voltage is logical low, the first output signal is logical high and the second output signal is logical low.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: April 13, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Thomas Ross, James McIntosh
  • Patent number: 10944401
    Abstract: A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ahreum Kim
  • Patent number: 10613575
    Abstract: An apparatus is configured to receive a two-phase input clock and output a four-phase output clock. The apparatus includes a circuit configured in a ring topology comprising a first switch controlled by a first phase of the input clock, a first inverting amplifier, a second switch controlled by a second phase of the input clock, a second inverting amplifier, a third switch controlled by the first phase of the input clock, a third inverting amplifier, a fourth switch controlled by the second phase of the input clock, and a fourth inverting amplifier, wherein the first inverting amplifier and the third inverting amplifier share a first regenerative load that is reset upon the first phase of the input clock, and the second inverting amplifier and the fourth inverting amplifier share a second regenerative load that is reset upon the second phase of the input clock.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10574052
    Abstract: A circuit for power supply protection comprising a first n-channel Metal Oxide Semiconductor Field Effect Transistor (nMOSFET) and a first p-channel Metal Oxide Semiconductor Field Effect Transistor (pMOSFET) each having a drain terminal coupled to an input voltage, a second nMOSFET and a second pMOSFET having drain terminals coupled to an output voltage and sources coupled to a sources of the first and second nMOSFET, respectively, and a control circuit. The control circuit turns the nMOSFETs off and the pMOSFETs on when the input voltage has a voltage value greater than zero and less than a predetermined positive limit, operates the nMOSFETs in a saturation mode and turns the pMOSFETs off when the input voltage has a voltage value greater than the predetermined positive limit, and turn the nMOSFETs and pMOSFETs off when the input voltage has a voltage value less than zero.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: February 25, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: WeiMing Sun
  • Patent number: 10230356
    Abstract: A high voltage driver includes a high-side output transistor circuit, a differential to single-ended (D2SE) converter connected to a gate of the high-side output transistor circuit, wherein the D2SE is supplied by a first and a second supply voltage, and a high voltage translator connected to the D2SE converter. The D2SE converter and the translator circuit are used to clamp a voltage at the gate of the high-side transistor circuit to be the first supply voltage less the second supply voltage.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: March 12, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventor: Kenneth Snowdon
  • Patent number: 10177745
    Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Su Kim
  • Patent number: 10001523
    Abstract: Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell operates in either a test mode or a normal functional mode according to a scan enable signal. The scan cell comprises delay logic including a plurality of delay elements, e.g., a plurality of transistors. The delay logic activates the delay elements only when the scan cell operates in the test mode. The delay elements are activated to change a scan latency of the scan cell. The scan latency of the scan cell is increased to mitigate or prevent hold violations.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Raghu G. Gopalakrishnasetty, Mary P. Kusko
  • Patent number: 9755644
    Abstract: An interface circuit includes at least one semiconductor logic gate and a latch circuit. The semiconductor logic gate configured to receive an input signal having a signal level changeable and outputs a logic gate signal which has a signal level becoming a low level when a signal level of the input signal is not less than a logic threshold value, alternatively has a signal level becoming a high level when a signal level of the input signal is less than the logic threshold value. The latch circuit fetches the logic gate signal as a first latch signal, while fetching a signal which is converted from the input signal and has a signal level varying between a second voltage and the ground potential, alternatively, the input signal as a second latch signal, to output the first interface output signal and the second interface output signal.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 5, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takashi Yamada
  • Patent number: 9344067
    Abstract: Integrated circuits with clocked storage elements are provided. A clocked storage element such as a flip-flop circuit may include a master latch, a slave latch, and associated control circuitry. The master and slave latches may be implemented using dual-interlocked cell (DICE) latch configurations. The DICE latch may include at least four inverting circuits having two redundant node pairs and may exhibit immunity to soft error upset (SEU) events. Each of the master and slave latches may be separated into different portions so that the redundant nodes are physically separated by interposing circuitry. The redundant nodes may also be formed in separate wells to further minimize charge sharing. The different portions of the master and slave latch may be interleaved to minimize area.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: May 17, 2016
    Assignee: Altera Corporation
    Inventors: Wen Wu, Yanzhong Xu
  • Patent number: 9324417
    Abstract: Systems and methods are provided for reading from a static random-access memory (SRAM). The systems and methods include activating a first bitline connected to a first transistor, wherein the first transistor provides access to a state stored by the SRAM. The systems and methods further include preventing a second bitline from being activated when the first bitline is activated, wherein the second bitline is connected to a second transistor that isolates the SRAM from a reference potential when the second bitline is activated, and reading the state stored by the SRAM by triggering a wordline connected to a gate of the first transistor.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 26, 2016
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Peter Lee
  • Patent number: 9178499
    Abstract: A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 3, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahadevan Venkiteswaran, Rajavelu Thinakaran
  • Patent number: 9041449
    Abstract: A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the nonvolatile semiconductor storage device, the volatile storage device and the nonvolatile storage device are provided without separation. Specifically, in the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Hidetomo Kobayashi
  • Publication number: 20150123723
    Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.
    Type: Application
    Filed: April 29, 2014
    Publication date: May 7, 2015
    Applicant: NXP B.V.
    Inventors: Vibhu Sharma, Ajay Kapoor
  • Patent number: 9014326
    Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 21, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuhichiroh Murakami, Shige Furuta, Yasushi Sasaki, Makoto Yokoyama, Takahiro Yamaguchi
  • Publication number: 20150092504
    Abstract: Semiconductor devices are provided. The semiconductor device includes a charge controller, a delay unit and a discharger. The charge controller controls an amount of electric charges on a first node to output a drive signal through the first node. The delay unit includes a capacitor coupled to the first node and retards the drive signal to generate an output signal. A delay time of the drive signal is controlled according to an amount of electric charges of the first node. The discharger discharges the electric charges of the first node when the amount of electric charges of the first node is equal to a predetermined value.
    Type: Application
    Filed: February 28, 2014
    Publication date: April 2, 2015
    Applicant: SK Hynix Inc.
    Inventor: Hyun Chul LEE
  • Patent number: 8994430
    Abstract: To reduce power consumption of a circuit (TEDC) which detects timing errors in a main flip-flop by determining whether or not output data signals of the main flip-flop and a shadow flip-flop correspond. The TEDC includes a power gating circuit (PGC) which performs power gating of the shadow FF and a reset circuit (RSTC) which resets an output signal of the shadow FF. The PGC makes the shadow FF in an active mode only when error detection needs to be performed; other than that, the PGC makes the shadow FF in a power saving mode. The RSTC supplies a certain voltage to an output terminal of the shadow FF in the power saving mode to suppress malfunction of the TEDC. A transistor using an oxide semiconductor is used to supply the voltage to the output terminal.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Patent number: 8957718
    Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Muneaki Maeno
  • Patent number: 8952740
    Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Shien-Chun Luo
  • Patent number: 8941429
    Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Zhihong Cheng
  • Publication number: 20140375367
    Abstract: In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Wu-Hsin Chen, Li Liu, Jianyun Hu
  • Patent number: 8823435
    Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: September 2, 2014
    Assignee: Broadcom Corporation
    Inventor: Armond Hairapetian
  • Patent number: 8742811
    Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 8742813
    Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: June 3, 2014
    Assignees: Samsung Electro-Mechanics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Yu Sin Kim, Sang Hee Kim, Dong Hyun Baek, Sun Woo Yun, Sung Hwan Park
  • Patent number: 8736334
    Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Limited
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Publication number: 20140111262
    Abstract: An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.
    Type: Application
    Filed: December 9, 2013
    Publication date: April 24, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masato ISHII
  • Publication number: 20140098016
    Abstract: A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.
    Type: Application
    Filed: June 25, 2012
    Publication date: April 10, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Shige Furuta, Yuhichiroh Murakami, Makoto Yokoyama, Seijirou Gyouten
  • Patent number: 8618855
    Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 8604855
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Ge Yang
  • Publication number: 20130214838
    Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 22, 2013
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATION
    Inventors: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
  • Publication number: 20130200935
    Abstract: A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 8, 2013
    Applicant: Renesas Electronics Corporation
    Inventor: Renesas Electronics Corporation
  • Patent number: 8487681
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: July 16, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, G E (Francis) Yang
  • Patent number: 8456214
    Abstract: A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: June 4, 2013
    Assignee: ARM Limited
    Inventor: Marlin Wayne Frederick, Jr.
  • Patent number: 8451040
    Abstract: A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 28, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoijin Lee, Gunok Jung
  • Patent number: 8436668
    Abstract: A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: May 7, 2013
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Jason M. Hart
  • Patent number: 8432209
    Abstract: A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period star
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: April 30, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Vlad Goldman, Noam Sivan
  • Patent number: 8421503
    Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 16, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiki Uemura, Yoshiharu Tosaka
  • Publication number: 20130039666
    Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
    Type: Application
    Filed: October 17, 2012
    Publication date: February 14, 2013
    Applicant: BROADCOM CORPORATION
    Inventor: BROADCOM CORPORATION
  • Publication number: 20120314757
    Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John F. Bulzacchelli, Byungsub Kim
  • Patent number: 8299834
    Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 30, 2012
    Assignee: Broadcom Corporation
    Inventor: Armond Hairapetian
  • Patent number: 8237483
    Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 7, 2012
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Nitin Jain
  • Patent number: 8233306
    Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Publication number: 20120139600
    Abstract: Disclosed is a low power latch that includes a low threshold voltage (LThV) inverter inverting an input data value to provide an output data value and including a LThV pull-up transistor and LThV pull-down transistor that operate at a threshold voltage less than a reference threshold voltage. The low power latch also includes a high threshold voltage (HThV) transistor isolating unit configured to isolate a power supply voltage provided to the LThV inverter during a sleep mode indicated by a sleep mode signal, and including a first HThV transistor and a second HThV transistor that operate at a threshold voltage less than the reference threshold voltage.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Myeong-Eun Hwang
  • Patent number: 8189082
    Abstract: To provide a floating diffusion (FD) for converting accumulated electric charges to a voltage signal and a transistor in which a gate terminal is connected to the FD and a source terminal is connected to an output signal line. When the FD is reset, a power supply voltage is applied to the FD for a predetermined period to set a voltage of the output signal line as a first voltage, and thereafter, the set voltage of the output signal line is set as a second voltage higher than the first voltage.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomohiro Matsuura
  • Publication number: 20120092323
    Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.
    Type: Application
    Filed: March 26, 2010
    Publication date: April 19, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuhichiroh Murakami, Shige Furuta, Yasushi Sasaki, Makoto Yokoyama, Takahiro Yamaguchi
  • Patent number: 8120406
    Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: February 21, 2012
    Assignee: ATI Technologies ULC
    Inventors: Arun Iyer, Shibashish Patel, Animesh Jain
  • Patent number: 8072252
    Abstract: A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: December 6, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Daniel W. Bailey
  • Patent number: 8067970
    Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 29, 2011
    Inventor: Robert P. Masleid
  • Patent number: 8063685
    Abstract: A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.
    Type: Grant
    Filed: August 8, 2010
    Date of Patent: November 22, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kapil Narula, Amol Agarwal, Sumeet Aggarwal, Sunit K. Bansal, Sabaa Sandhu, Harkaran Singh
  • Patent number: 8035420
    Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Yeon Byeon
  • Publication number: 20110222349
    Abstract: According to one embodiment, a transfer circuit includes a first inverter, a second inverter, a first line, a second line, a first holder, and a second holder. The first inverter inverts data at a first node and transfers the inverted data to a second node. The second inverter inverts the data at the second node and transfers the inverted data to the first node. The first line connected to the first node. The second line connected to the second node. The first holder may output data to the first node. The second holder may output data to the second node. When the first holder outputs the data to the first line, the first and second inverters are turned off. When the second holder outputs the data to the first line through the second node, the first inverter is turned off.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 15, 2011
    Inventor: Hiromitsu Komai